JP2001189647A - Charge amount comparing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge amount comparing circuit, with which a charge amount can be accurately compared, without limiting an input signal nor being affected by a design error caused by the characteristic difference of the circuit or the like and ON current or transistor characteristics to be changed by a power source or temperature caused by the influence of process dispersion or operating environment and further, a time resolution or voltage resolution can be sensitively compared regardless of an operating frequency concerning the change point of a logical value based on the voltage of capacitance. SOLUTION: This circuit is provided with P channel transistors 14a and 14b and N channel transistors 16a and 16b for supplying electric charges corresponding to signals inputted to input terminals 10a, 12a, 10b and 12b, capacitors 18a and 18b for storing the electric charges supplied from the P channel transistors 16a and 16b and the N channel transistors 16a and 16b, and NAND circuits 20a and 20b for receiving the output voltages of the capacitors 18a and 18b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge amount comparison circuit, and more particularly to a charge amount comparison circuit for comparing the total charge amount of a digital signal propagating through a digital circuit such as a semiconductor integrated circuit.

[0002]

2. Description of the Related Art PLL (Phase Locked L)
In a circuit such as an (op) circuit or an A / D converter, a conventional charge amount comparison circuit in which two or more digital signals are compared with the total charge amount output or input within a fixed time is used. Is a circuit generally having the configuration shown in FIG. FIG. 11 is a circuit diagram showing a configuration of a conventional charge amount comparison circuit. As shown in FIG. 11, the conventional charge amount comparison circuit includes a P-channel transistor 52, an N-channel transistor 53, a capacitor 54, and an inverter circuit 55.

The gate electrodes of the P-channel transistor 52 and the N-channel transistor 53 are connected to the input terminal 50 and the input terminal 51, respectively. The source electrode of the P-channel transistor 52 is connected to the power supply VDD, and the drain electrode of the P-channel transistor 52. And the source electrode of the N-channel transistor 53 are connected, and the drain electrode of the N-channel transistor 53 is grounded.

A connection point C50 between the drain electrode of the P-channel transistor 52 and the source electrode of the N-channel transistor 53 is connected to one electrode of a capacitor and an input terminal of an inverter circuit 55. The output terminal of the inverter circuit 55 is connected to the output terminal 56.

Next, the operation of the conventional charge amount comparison circuit shown in FIG. 11 will be described with reference to FIG. FIG.
2 is a timing chart showing signal waveforms of various parts of the conventional charge amount comparison circuit. As shown in FIG. 12, the value of the input signal at the input terminal 51 is set to a constant value, for example, 0 [V], and the input signal IN10 shown in FIG.
, The N-channel transistor 53 maintains the off state, and the P-channel transistor 52
A switching operation is performed in accordance with 10. When the P-channel transistor 52 is in the ON state, charge is accumulated in the capacitor 54 from the power supply VDD via the P-channel transistor 52. When the amount of charge stored in the capacitor 54 is small and the output voltage V50 of the capacitor 54, that is, the input voltage of the inverter circuit 55 is low, the output of the inverter circuit 55 does not become H (high) level.

When the above switching operation is repeated, the amount of charge stored in the capacitor 54 increases, and the input voltage of the inverter circuit 55 gradually increases as shown in FIG. When the input voltage of the inverter circuit 55 becomes higher than a certain voltage, the output signal OUT10 of the inverter circuit 55
Becomes the L (low) level. When the output of the inverter circuit 55 becomes low, a predetermined amount of electric charge is
It can be seen that the input has been made.

[0007]

In the conventional charge amount comparison circuit shown in FIG. 11, when it is desired to compare the phases of input digital signals, as shown in FIG. There is a problem in that there is a restriction that the voltage of the must always be a fixed value. The reason is that, when a digital signal is input from both the input terminal 50 and the input terminal 51, the P-channel transistor 52 and the N-channel transistor 53 are simultaneously turned on and have an indefinite value, which may cause a malfunction. .

Further, since the input signal IN10 is input to the P-channel transistor 52 and the input signal IN20 is input to the N-channel transistor 53, variations in transistor characteristics cause a comparison error. Further, due to process variations, the inverter circuit 55 to which the transistor characteristics, the capacitance of the capacitor, and the output voltage V50 of the capacitor are input.
Have a drawback that they all result in a comparison error.

When the performance of the N-channel transistor 53 is good and the performance of the P-channel transistor 52 is bad,
Since the output signal OUT1 tends to be at a high level and is unlikely to be at a low level, there is a disadvantage that the comparison result is shifted. Further, when the capacitance of the capacitor 54 becomes large, the output voltage of the capacitor 54 stops near the threshold voltage as compared with the normal case. Further, when the threshold voltage of the inverter circuit 55 changes, there is a disadvantage that the comparison result is shifted.

The present invention has been made in view of the above circumstances, has no restrictions on input signals, and has a design error due to a characteristic difference between a P-channel transistor and an N-channel transistor, a process variation, and an influence of an operating environment. Accurately compares the amount of charge without being affected by the power supply, on-current that changes with temperature, and transistor characteristics.Furthermore, the change point of the logical value due to the voltage of the capacitance is independent of the operating frequency, and the time resolution, voltage resolution, etc. It is an object of the present invention to provide a charge amount comparison circuit capable of comparing the charge amount with high sensitivity.

[0011]

In order to solve the above problems, the present invention provides a charge supply means for supplying charge according to a signal input to an input terminal, and a charge supply means for supplying charge from the charge supply means. A first charge storage means for storing, a second charge storage means for storing charge supplied from the charge supply means, and a flip-flop for inputting output voltages of the first charge storage means and the second charge storage means. It is characterized by having. Further, the present invention is provided between the first charge storage means and the flip-flop, wherein the first buffer means determines a threshold value for an output voltage of the first charge storage means, the second charge storage means, A second buffer unit provided between the flip-flop and a threshold for the output voltage of the second charge storage unit. The present invention also provides at least one third buffer unit provided in parallel with the first buffer unit and having a threshold value set to a value different from the threshold value of the first buffer unit, and in parallel with the second buffer unit. At least one fourth buffer means having a threshold set to a value different from the threshold of the second buffer means; and the first buffer means or the third buffer means;
And selecting means for selecting the second buffer means or the fourth buffer means.
Here, according to the present invention, the flip-flop comprises two N
It is characterized by comprising an AND circuit and having one output terminal connected to the input terminal of the other NAND circuit. The present invention also provides first and second charge storage means for storing charge, and discharge means for discharging the charge stored in the first and second charge storage means in response to a signal input to an input terminal. And a flip-flop for inputting output voltages of the first charge storage means and the second charge storage means. The present invention provides the flip-flop,
It consists of two NOR circuits, and one output terminal is connected to the other NA
It is characterized in that it is connected to the input terminal of the ND circuit. Further, the present invention is characterized in that it is provided with a phase comparison means provided before the charge supply means and for comparing the phase of a signal inputted to the input terminal.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a charge comparison circuit according to an embodiment of the present invention; [First Embodiment] FIG. 1 is a diagram showing a configuration of a charge amount comparison circuit according to a first embodiment of the present invention. As shown in FIG. 1, the charge amount comparison circuit according to the first embodiment of the present invention includes:
A first circuit including a P-channel transistor 14a, an N-channel transistor 16a, and a capacitor 18a;
A second circuit including a P-channel transistor 14b, an N-channel transistor 16b, and a capacitor 18b. Further, the NAND circuit 20a and the NAND circuit 2
0b.

In the first circuit, the gate electrodes of the P-channel transistor 14a and the N-channel transistor 16a are connected to the input terminals 10a and 12a, respectively, and the source electrode of the P-channel transistor 14a is connected to the power supply VDD. The drain electrode of the N-channel transistor 16a is connected to the drain electrode of the N-channel transistor 16a, and the drain electrode of the N-channel transistor 16a is grounded.

A connection point C10 between the drain electrode of the P-channel transistor 14a and the source electrode of the N-channel transistor 16a is connected to one electrode of a capacitor 18a and one input terminal of a NAND circuit 20a.
The output terminal of the NAND circuit 20a is connected to the output terminal 22a.

Similarly, the gate electrodes of the P-channel transistor 14b and the N-channel transistor 16b in the second circuit are connected to the input terminals 10b and 12b, respectively, and the source electrode of the P-channel transistor 14b is connected to the power supply VDD. P-channel transistor 14
b is connected to the source electrode of the N-channel transistor 16b.
Are grounded.

A connection point C20 between the drain electrode of the P-channel transistor 14b and the source electrode of the N-channel transistor 16b is connected to one electrode of the capacitor 18b and one input terminal of the NAND circuit 20b.
The output terminal of the NAND circuit 20b is connected to the output terminal 22b. The output terminal of the NAND circuit 20a is:
NAN is connected to the other input terminal of the NAND circuit 20b.
The output terminal of the D circuit 20b is connected to the other input terminal of the NAND circuit 20a to form a flip-flop.

The operation principle of the charge amount comparison circuit according to the first embodiment of the present invention in the above configuration is as follows. For a signal to be compared, the supplied charge amount is determined by the two capacitors 18a and 18a.
8b, the output voltages V10 and V12 of the capacitors 18a and 18b are received by a flip-flop, and the data which exceeds the threshold voltage before the amount of charge stored in the two capacitors 18a and 18b increases and is held. To compare the charge amounts.

Next, the operation of the charge amount comparison circuit according to the first embodiment of the present invention will be described in detail. FIG. 2 is a timing chart showing signal waveforms of various parts of the charge amount comparison circuit according to the first embodiment of the present invention. First, input terminal 10
a, 12a, 10b, 12b to high level (power supply VD
D signal), the P-channel transistor 14a and the P-channel transistor 14b are turned off, and the N-channel transistors 16a and N
The channel transistor 16b is turned on. In this state, the potentials of the connection points C10 and C20 become substantially equal to the ground potential, the electric charges stored in the capacitors 18a and 18b are discharged, and the output voltages V10 and V12 of the capacitors 18a and 18b become low level. That is, it becomes 0. As a result, a low-level signal is input to one input terminal of the NAND circuit 20a and one input terminal of the NAND circuit 20b. As a result, a high-level signal is output from the output terminals 22a and 22b.

Next, low-level input signals IN2 and IN4 are input from the input terminals 12a and 12b, respectively, and input signals IN1 and IN3 to be compared are input from the input terminals 10a and 10b. Input terminal 12
a and 12b output low-level input signals IN2 and IN4.
, The N-channel transistor 16a
And the N-channel transistor 16b is turned off,
The P-channel transistor 14a and the P-channel transistor 14b are switched by the input signal IN1 and the input signal IN3, respectively. While the P-channel transistor 14a is on, charge is accumulated in the capacitor 18a, and while the P-channel transistor 14b is on, charge is accumulated on the capacitor 18b.

When the above-described switching operation is repeated, the amount of charge stored in the capacitors 18a and 18b increases, and the amount of charge stored in the output voltage V10 of the capacitor 18a and the output voltage V12 of the capacitor 18b as shown in FIG. Gradually increases in proportion to. Capacitor 1
Since the output voltages V10 and V12 of 8a and 18b are input to one input terminal of the NAND circuit 20a and the other input terminal of the NAND circuit 20b, for example, the capacitor 18b
When the output voltage V10 of the capacitor 18a becomes higher than the threshold voltage of the NAND circuit 20a before the output voltage V12 of the NAND circuit 20b becomes higher than the threshold voltage of the NAND circuit 20b,
The output of the NAND circuit 20a becomes low level, and a low level signal is output from the output terminal 22a.

In the above example, after the output voltage V10 of the capacitor 18a becomes equal to or higher than the threshold voltage of the NAND circuit 20a, the output voltage V12 of the
Even if the voltage exceeds the threshold voltage of the circuit 20b, the NAND circuit 2
0a outputs a low-level signal, and this signal is input to the other input terminal of the NAND circuit 20b. Therefore, a low-level signal is output from the output terminal 22a, and the output terminal 22b Outputs a high-level signal. When a high-level signal is input from the input terminals 12a and 12b, the circuit shown in FIG. 1 is in the initial state, that is, no charge is accumulated in the capacitors 18a and 18b, and the output voltages V10 and V12 are low. That is, it becomes 0, and a state in which a high-level signal is output from the output terminals 22a and 22b is established.

As described above, in the present embodiment, it is known that the output voltages V10 and V12 due to the accumulation of the charge amount exceed the predetermined values (threshold voltage values of the NAND circuits 20a and 20b) first. Input terminal 1
It is possible to know which of the input signal 0a or the input signal input to the input terminal 10b has the larger charge amount.

[Second Embodiment] Next, a charge amount comparison circuit according to a second embodiment of the present invention will be described in detail. FIG. 3 is a diagram showing the configuration of the charge amount comparison circuit according to the second embodiment of the present invention. The same members as those of the charge amount comparison circuit according to the first embodiment of the present invention shown in FIG. The reference numerals are used and the description is omitted. The difference between the charge amount comparison circuit according to the second embodiment of the present invention shown in FIG. 3 and the charge amount comparison circuit according to the first embodiment of the present invention shown in FIG. 1 is that a connection point C10 is connected to the input terminal of the inverter circuit 25a. And connect
An inverter circuit 26a having an input terminal connected to the output terminal of the inverter circuit 25a is further provided.
6a is connected to one input terminal of the NAND circuit 20a, and inverter circuits 25b and 26b similar to the inverter circuits 25a and 26a are further connected to a connection point C20 and NAN.
This is a point connected to one input terminal of the D circuit 20b.

FIG. 4 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the second embodiment shown in FIG. The charge amount comparison circuit shown in FIG. 3 is substantially the same as the operation of the charge amount comparison circuit shown in FIG. 1, but includes inverter circuits 25a, 25b, 2a, and 26b, so that input to NAND circuits 20a and 20b is performed. The signal is shaped.

That is, as shown in FIG. 4, when the output voltage of the capacitor 18a gradually increases, at time t1
In this case, the output signal V14 of the inverter circuit 26a goes high, and as a result, the signal output from the output terminal 22a goes low. When the output voltage of the capacitor 18b gradually increases, at time t2,
Although the output signal V16 of the inverter circuit 26b becomes high level, the level of the signal output from the output terminals 22a and 22b does not change due to the characteristics of the flip-flop including the NAND circuits 20a and 20b.

In this embodiment, the inverter circuit 2
5a, 26a, 25b, and 26b, and the NAND circuit 2
Since the signals input to 0a and 20b are shaped, malfunction due to noise or the like can be prevented. Further, in the present embodiment, the threshold voltage can be changed by changing the characteristic ratio of the P-channel transistor and the N-channel transistor forming the inverter circuit, and the magnitude of the capacitance of the capacitors 18a and 18b and the inverter circuit 25a , 26a, 25b, 26b, it is possible to control the time until the output voltages V10, V12 exceed the threshold values of the inverter circuits 25a, 26a, 25b, 26b.

[Third Embodiment] Next, a charge amount comparison circuit according to a third embodiment of the present invention will be described in detail. FIG. 5 is a diagram showing the configuration of the charge amount comparison circuit according to the third embodiment of the present invention. The components of the charge amount comparison circuit according to the first and second embodiments of the present invention shown in FIGS. The same members are denoted by the same reference numerals, and description thereof will be omitted. The difference between the charge amount comparison circuit according to the third embodiment of the present invention shown in FIG. 5 and the charge amount comparison circuit according to the second embodiment of the present invention shown in FIG. 3 is that the inverter circuits 25a and 25 shown in FIG.
6a are provided in parallel with the inverter circuits 27a and 28a, and the inverter circuit 2 is provided in parallel with the inverter circuits 25b and 26b.
7b and 28b, and inverter circuits 26a and 28
a and a NAND circuit 20a, a selector circuit 29a is provided between the inverter circuits 26b and 28b and the NAND circuit 2a.
0b is provided with the selector circuit 29b.

The threshold values of the inverter circuits 27a and 28a are set to values different from the threshold values of the inverter circuits 25a and 26a, and the threshold values of the inverter circuits 27b and 28b are set to values different from the threshold values of the inverter circuits 25b and 26b. I have. In addition, the selector circuits 29a and 29b, based on the selection signal input from the selection signal input terminal 30, provide the inverter circuit 25a or 26a or the inverter circuit 27a,
28a and the inverter circuits 25b and 26b or the inverter circuits 27b and 28b.

In this embodiment, the selector circuit 29
a and the selector circuit 29b, the inverter circuits 25a and 26a or the inverter circuits 27 having different thresholds.
a and 28a and the inverter circuits 25b and 26b or the inverter circuits 27b and 28b are selected.
Output signals V18, V input to ND circuits 20a, 20b
20 timings can be changed. The inverter circuits 25a and 26a and the inverter circuits 25b and 26
The number of inverter circuits provided in parallel with b may be arbitrary.

For example, with respect to the input signals IN1 and IN3 input from the input terminals 10a and 10b, respectively, the current flowing into the capacitors 18a and 18b is small, and the inverter circuits 25a and 26a and the inverter circuits 25b and 26b When the threshold value is high, a case occurs in which the output voltages V18 and V20 do not change from the low level to the high level. In such a case, the charge amount comparison circuit can be operated by selecting the inverters 27b and 28b and the inverter circuits 27b and 28b whose threshold values are set low. FIG. 6 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the third embodiment shown in FIG. Comparing the output voltage V18 in FIG. 6 with the output voltage V14 in FIG. 4, and the output voltage V20 in FIG. 6 with the output voltage V16 in FIG. 4, the timing of switching to the high level is the output voltage V18 shown in FIG. , V20 are faster.

[Fourth Embodiment] Next, a charge amount comparison circuit according to a fourth embodiment of the present invention will be described in detail. FIG. 7 is a diagram showing the configuration of the charge amount comparison circuit according to the fourth embodiment of the present invention. The same members as those of the charge amount comparison circuit according to the first embodiment of the present invention shown in FIG. The reference numerals are used and the description is omitted. The difference between the charge comparison circuit according to the fourth embodiment of the present invention shown in FIG. 7 and the charge comparison circuit according to the first embodiment of the present invention shown in FIG.
A third circuit including a channel transistor 14c, an N-channel transistor 16c, and a capacitor 18c is provided, and a NAN is provided in parallel with the NAND circuits 20a and 20b.
The point is that a D circuit 20c is provided to form a three-input flip-flop. FIG. 8 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the fourth embodiment shown in FIG. In the charge amount comparison circuit according to the fourth embodiment of the present invention shown in FIG. 7, a signal having the largest charge amount among the three inputs can be selected.

[Fifth Embodiment] Next, a charge amount comparison circuit according to a fifth embodiment of the present invention will be described in detail. FIG. 9 is a diagram showing the configuration of the charge amount comparison circuit according to the fifth embodiment of the present invention. The same members as those of the charge amount comparison circuit according to the first embodiment of the present invention shown in FIG. The reference numerals are used and the description is omitted. The charge amount comparison circuit according to the fifth embodiment of the present invention shown in FIG. 9 differs from the charge amount comparison circuit according to the first embodiment of the present invention shown in FIG. 1 in that an external signal input terminal 42a for inputting an external signal is provided. , 42b are connected to each other, and a comparison result of the phase comparator 40 is output to the gate electrodes of the P-channel transistor 14a and the P-channel transistor 14b, respectively, and a CLR signal input for inputting an external CLR signal is further provided. End 43
In that the CLR signal input terminal 43 is connected to the gate electrodes of the N-channel transistor 16a and the N-channel transistor 16b.

FIG. 10 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the fifth embodiment shown in FIG. As can be seen from FIG. 10, the phase comparator 40 detects the external signal S input to the external signal input terminal 42a.
The rising edge of IG1 is detected and output as the input signal IN1 to the input terminal of the P-channel transistor 14a. The rising edge of the external signal SIG2 input to the external signal input terminal 42b is detected, and the input terminal of the P-channel transistor 14b is detected. Output as input signal IN2. Thus, by providing the phase comparator 40, the phase difference between the rising of the external signal SIG1 and the rising of the external signal SIG2 can be detected. Further, by controlling the ON state and the OFF state of the N-channel transistor 16a and the N-channel transistor 16b by the CLR signal input to the CLR signal input terminal 43, the capacitor 18
a, 18b can be controlled. The configuration shown in the present embodiment, that is, the phase comparator 40 and the CLR signal input terminal 43 can be applied to the above-described first to fourth embodiments, and the same effects as those of the present embodiment can be obtained. .

While the embodiment of the present invention has been described above, in the above-described third embodiment, the selector circuit is used to control the inverter circuits 25a and 26a or the inverter circuits 27a and 28a and the inverter circuits 25b and 26b.
Alternatively, the threshold voltage is determined by selecting the inverter circuits 27b and 28b, but the NA of the first embodiment shown in FIG.
ND circuits 20a and 20b and inverter circuit 25 of FIG.
In a, 26a, 25b, and 26b, the threshold voltage can be changed by changing the power supply (VDD) connected to the circuit.

Further, in the first embodiment shown in FIG. 1, a NAND circuit is used as a flip-flop. However, a NOR circuit is used instead of the NAND circuit, and low-level signals (input signals IN1 to IN4) are input. By applying (GND), the output voltages of the two capacitors 18a and 18b become high level (VDD) and can be set to the initial state. Then, a high-level (VDD) input signal IN
2 and IN4, and the input signals IN1 and IN3 are inverted in phase with respect to the input signals IN1 and IN3 shown in FIG. 2, so that when the output voltages V10 and V12 are at a high level, the capacitors 18a and 18b The circuit having the same function as the first embodiment, in which the amount of charge stored in the first embodiment is large and the amount of charge is low when the level is low, can be realized. This can be similarly realized for the charge amount comparison circuits of the second to fourth embodiments.

[0036]

As described above, according to the present invention, the logical value of the input signal to be compared (the two input signals are simultaneously at the high level or the low level) is not restricted. Further, there is an effect that the comparison can be performed without being affected by the pulse width. In addition, since all circuit configurations are configured symmetrically, design errors due to differences in characteristics of components such as transistors constituting the circuit,
There is an effect that the charge amount can be compared with high accuracy without being affected by the power supply, the on-current that changes with temperature, and the transistor characteristics due to the influence of the process variation and the operating environment. Further, since the change point of the logical value due to the voltage of the capacitor is stored in the flip-flop without depending on the clock or the like, the comparison result can be held regardless of the operating frequency,
In addition, since the output of the NAND circuit which has exceeded the threshold value directly controls the other NAND circuit and can be controlled with almost no delay, there is an effect that comparison can be performed with high sensitivity.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a charge amount comparison circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms of various parts of the charge amount comparison circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a charge amount comparison circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the second embodiment shown in FIG. 3;

FIG. 5 is a diagram illustrating a configuration of a charge amount comparison circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the third embodiment shown in FIG.

FIG. 7 is a diagram showing a configuration of a charge amount comparison circuit according to a fourth embodiment of the present invention.

8 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the fourth embodiment shown in FIG. 7;

FIG. 9 is a diagram showing a configuration of a charge amount comparison circuit according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart showing signal waveforms at various parts of the charge amount comparison circuit according to the fifth embodiment shown in FIG.

FIG. 11 is a circuit diagram showing a configuration of a conventional charge amount comparison circuit.

FIG. 12 is a timing chart showing signal waveforms of various parts of a conventional charge amount comparison circuit.

[Explanation of symbols]

10a, 10b, 10c, 12a, 12b, 12c
Input terminals 14a, 14b, 14c P-channel transistors (charge supply means, discharge means) 16a, 16b, 16c N-channel transistors (charge supply means, discharge means) 18a Capacitor (first charge storage means) 18b Capacitor (second charge storage) Means) 20a, 20b NAND circuit (flip-flop) 25a, 26a Inverter circuit (first buffer means) 25b, 26b Inverter circuit (second buffer means) 27a, 28a Inverter circuit (third buffer means) 27b, 28b Inverter circuit ( 4th buffer means) 40 Phase comparator (phase comparing means)

Claims (7)

[Claims] A charge supply unit configured to supply charge according to a signal input to an input terminal; a first charge storage unit configured to store charge supplied from the charge supply unit; A charge comparison circuit comprising: a second charge storage unit configured to store a charge; and a flip-flop configured to input output voltages of the first charge storage unit and the second charge storage unit. 2. A first buffer means provided between the first charge storage means and the flip-flop and defining a threshold value for an output voltage of the first charge storage means; the second charge storage means and the flip-flop. 2. A charge amount comparison circuit according to claim 1, further comprising: a second buffer means provided between the first charge storage means and the second charge storage means for determining a threshold value for an output voltage of the second charge storage means. 3. At least one third buffer unit provided in parallel with the first buffer unit and having a threshold set to a value different from the threshold of the first buffer unit; and in parallel with the second buffer unit. At least one fourth buffer means provided and having a threshold set to a value different from the threshold of the second buffer means; the first buffer means or the third buffer means; and the second buffer means or the second buffer means. 3. The charge amount comparison circuit according to claim 2, further comprising a selection means for selecting four buffer means. 4. First and second charge accumulating means for accumulating electric charge, discharging means for discharging electric charge accumulated in the first and second charge accumulating means in response to a signal input to an input terminal, A charge amount comparing circuit, comprising: a flip-flop for inputting output voltages of the first charge storage means and the second charge storage means. 5. The flip-flop comprises two NANs.
4. The charge amount comparison circuit according to claim 1, comprising a D circuit, wherein one output terminal is connected to an input terminal of the other NAND circuit. 6. The flip-flop comprises two NORs.
5. The charge amount comparing circuit according to claim 4, wherein the circuit comprises a circuit and one output terminal is connected to an input terminal of the other NAND circuit. 7. The semiconductor device according to claim 1, further comprising a phase comparison unit provided before the charge supply unit and comparing a phase of a signal input to the input terminal. Charge amount comparison circuit.