JP2001188764A - Multi-processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the executing performance of a whole Neumann type computer system constituting a multi-processor system is largely limited since the transfer of an instruction code from a main storage to a processor is affected by the capabilities of a bus, and that the storage capacity of the main storage which can be integrated on a semiconductor chip is limited in a Neumann type computer system integrated into one chip. SOLUTION: This system is provided with plural semiconductor chips equipped with a processor and a main storage and a bus connecting the processor to the main storage, and one address space is constituted of the main storage of each semiconductor chip, and a program recorded in the main storage to which the prescribed area of the address space is assigned is processed by a processor arranged in the same semiconductor chip as the main storage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for executing an execution program in a computer system, and more particularly to a multiprocessor system.

[0002]

2. Description of the Related Art An example of a multiprocessor system is shown in FIG. FIG. 13 is a configuration diagram showing a configuration of a conventional multiprocessor system. In addition,
The multiprocessor system referred to here is a distributed processing system in which a plurality of processors are connected. In FIG. 13, reference numeral 301 denotes a first processor, 311 denotes a second processor, and 302 denotes a main memory. The main memory 302
Is also called memory. A bus 303 connects the first processor 301 and the main memory 302. The bus 303 is connected to the second processor 311 and the main memory 30.
2 is connected. The instruction code is transferred to the first processor 301 or the second processor 311 via the bus 303. 304 is the direction of the flow of the instruction code,
The direction of the flow of the instruction code toward the first processor 301 on the bus 303 is shown. Reference numeral 314 denotes the direction of the flow of the instruction code, which indicates the direction of the flow of the instruction code on the bus 303 toward the second processor 311.

The configuration of a Neumann computer system, which is the basic configuration of the above-described conventional multiprocessor system, will be described with reference to FIG. FIG. 14 is a configuration diagram showing a configuration of a Neumann computer system which is a basic configuration of a conventional multiprocessor system.
In FIG. 14, reference numeral 201 denotes a processor,
02 is retrieved and processed. 2
Reference numeral 02 denotes a main memory in which an execution program is stored as an instruction code. Reference numeral 203 denotes a bus, and the processor 201
And the main memory 202 are connected, and the instruction code stored in the main memory 202 is sent to the processor 201. Reference numeral 204 denotes a flow direction of the instruction code, which indicates a flow direction of the instruction code toward the processor 201 on the bus 203.

The conventional multiprocessor system shown in FIG. 13 is a combination of a plurality of Neumann-type computer systems shown in FIG. 14, and a first processor 301 and a second processor 311 are respectively provided. The two processors are connected to the main memory 302, and these two processors independently take out instruction codes and data from the main memory 302 and execute the execution programs stored in the main memory 302. The main memory 202 stores data to be processed by the execution program,
01 also stores data such as an execution environment temporarily used in the processing of the execution program.

[0005] The processor 201 has a main memory 202.
The instruction codes of the execution program stored in the program are sequentially extracted and the execution program is executed. However, the main memory 20
If the transfer speed of the bus 203, which is the transmission speed of the instruction code from the processor 2, is lower than the execution speed of the processor 201, the processor 201 waits until the arrival of the instruction code, and the execution of the execution program is temporarily stopped. Or postponed. Such a situation is called a bus bottleneck of the Neumann computer system.
In order to avoid such a situation, the processor 201
It is sufficient that the transfer speed of the bus 203 be sufficiently higher than the execution speed, which is the processing speed of.

The problem of the bus bottleneck of the Neumann computer system can be alleviated by using a configuration as shown in FIG. FIG. 15 is a configuration diagram showing a configuration of a Neumann computer system that alleviates the problem of a bus bottleneck. In FIG. 15, reference numeral 401 denotes a processor, and 402 denotes a main memory. Reference numeral 403 denotes a bus, and a processor 401
And the main memory 402 are connected. The instruction code stored in the main memory 402 is transferred to the processor 401 via the bus 403. Reference numeral 404 denotes the flow direction of the instruction code.
It shows the direction of the flow of the instruction code toward. 405 is a semiconductor chip, and on this one semiconductor chip 405,
A processor 401, a main memory 402, and a bus 403 are integrated.

Generally, the operating speed inside a semiconductor chip is higher than the operating speed outside a semiconductor chip. Therefore, by providing a bus on the semiconductor chip 405 that can cause a bus bottleneck problem, the bus bottleneck problem can be alleviated. Further, the wiring inside the semiconductor chip can be finely processed than the wiring outside the semiconductor chip, and the number of bits can be increased more easily in the bus in the semiconductor chip than in the bus outside the semiconductor chip. Can improve the transfer speed of
The problem of the bus bottleneck can be mitigated.

Next, a description will be given of a case where a main memory is added to the Neumann computer system as shown in FIG. 15 with reference to FIG. FIG. 16 is a configuration diagram showing a configuration of a one-chip Neumann computer system in which a main memory is additionally provided outside. Note that the processor 201, the main memory 202, and the bus 20
3 is called a one-chip Neumann computer system or a one-chip Neumann computer system.

In FIG. 16, reference numeral 501 denotes a processor, and 502 denotes a main memory. Note that the main memory 502 is also called a memory. 503, a bus;
1 and the main memory 502 are connected. The instruction code stored in the main memory 502 is transferred to the processor 501 via the bus 503. Reference numeral 504 denotes the direction of the flow of the instruction code.
The direction of the flow of the instruction code toward 1 is shown. Reference numeral 505 denotes a semiconductor chip, on which the processor 501, the main memory 502, and the bus 503 are integrated and built. Thus, the semiconductor chip 50
5, a processor 501, a main memory 502, and a bus 503.
The integration of these is called one-chip integration.

Reference numeral 515 is a semiconductor chip. Reference numeral 512 denotes a main memory, which is provided on the semiconductor chip 515. Also,
The main memory 512 is added outside the semiconductor chip 405. A bus 513 connects the processor 201 and the main memory 512. The bus 513 transfers the instruction code from the main storage 512 to the processor 201. 51
Reference numeral 4 denotes a flow direction of the instruction code, which indicates a flow direction of the instruction code from the main memory 512 to the processor 201 on the bus 513.

In a Neumann computer system as shown in FIG. 16, an execution program is stored in a built-in main memory 202 and an external main memory 512. And
The processor 201 reads an instruction code stored in each main storage as described below and executes an execution program stored in the main storage. That is, the built-in main memory 2
When executing the execution program stored in the main memory 202, the instruction code stored in the built-in main memory 202 is transferred to the bus 20.
3 and read into the processor 201 to execute the execution program. When executing the execution program stored in the external main memory 512, the external main memory 51
2 is read into the processor 201 via the bus 513 and executed.

[0012]

As described above, the Neumann-type computer system constituting the conventional multiprocessor system stores an execution program in a main memory, and executes an instruction code of the execution program stored in the main memory.
The execution program was executed by sequentially transferring the data to the processor one by one and decoding it. However, transferring the instruction code from the main memory to the processor can be a major bottleneck in executing the execution program,
The execution performance of the Neumann-type computer system was greatly limited.

More specifically, in the conventional multiprocessor system shown in FIG. 13, the first processor 301 and the second processor 311 are provided, so that the processing capability itself which can be processed by the multiprocessor system is improved. However, if the transfer capability of the bus 303 itself for transferring the instruction code stored in the main memory 302 to each processor has no margin, the actual processing capability of the multiprocessor system becomes the transfer capability of the instruction code of the bus 303. Limited by That is, if there is no transfer capability of the bus 203 that is equal to or greater than the sum of the execution speed of the first processor 301 and the execution speed of the second processor 311, the execution capability of the multiprocessor system is potentially lower. Processing capacity does not increase. Naturally, in the Neumann computer system shown in FIG. 14, if the transfer speed of the bus 203 is low, it becomes a bottleneck and hinders high-speed execution of the execution program.

On the other hand, in a one-chip Neumann computer system as shown in FIG. 15, a processor 401, a main memory 402, and a bus 403 are connected to a semiconductor chip 4.
By integrating them on the network 05, the transfer capability of the bus 403 is increased, and the bottleneck problem is reduced. But,
A new problem arises in that the storage capacity of the main memory 402 that can be integrated on the semiconductor chip 405 is limited. Of course,
In a one-chip Neumann computer system in which main memory is externally added as shown in FIG.
If the transfer speed is low, the bottleneck problem will recur,
High-speed execution of the execution program stored in the externally added main memory 512 is hindered.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and is intended to be used when an execution program having a large storage capacity that cannot be integrated on one semiconductor chip is integrated on one semiconductor chip. It is an object of the present invention to obtain a multiprocessor system capable of high-speed execution.

[0016]

A multiprocessor system according to the present invention has a plurality of semiconductor chips each having a processor, a main memory, and a bus connecting the processor and the main memory. One address space is configured, and a program recorded in a main memory to which a predetermined area of the address space is allocated is processed by a processor provided on the same semiconductor chip as the main memory.

Further, the multiprocessor system according to the present invention, when the processing shifts from a program recorded in a certain main memory to a series of programs recorded in another main memory, a processor corresponding to the certain main memory. Then, setting environment data set in a processor corresponding to a certain main storage is output to a processor corresponding to another main storage to a processor corresponding to another main storage.

Further, in the multiprocessor system according to the present invention, the transition of the processing from a program recorded in a certain main memory to a series of programs recorded in another main memory is performed by changing a program recorded in a certain main memory. The determination is made based on whether the address has exceeded a predetermined address.

Further, in the multiprocessor system according to the present invention, the entire program can be divided for each functional module, and is recorded in the main memory for each module.

Further, in the multiprocessor system according to the present invention, the processor converts an address in the address space into an address of a main memory corresponding to the processor.

In the multiprocessor system according to the present invention, the address of the address space is converted into the address of the predetermined main memory when a program is recorded in the main memory or an address referred to by the program is used. It is time.

Further, the multiprocessor system according to the present invention outputs setting environment data set in a certain processor from one processor to another processor to another processor as needed.

Further, in the multiprocessor system according to the present invention, a plurality of setting environment data are accumulated, and when the output destination is the same among the plurality of accumulated setting environment data, the last setting environment data is stored. Only the setting environment data of the call is output.

Further, the multiprocessor system according to the present invention monitors the execution of the program and delays the output of the setting environment data.

In the multiprocessor system according to the present invention, the setting environment data is transmitted via a dedicated line.
This is output from one processor to another processor.

Further, in the multiprocessor system according to the present invention, a part of the program is recorded in the main memory of each semiconductor chip, and the processor corresponding to the main memory executes the part of the program in parallel.

Further, in the multiprocessor system according to the present invention, the first main memory in which a part of the first program and the second program are recorded and the other part of the first program different from the part are provided. A second main memory recorded,
When the other part of the first program is executed by the processor corresponding to the second main memory, the processor corresponding to the first main memory executes the second execution program.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 One embodiment of a multiprocessor system according to the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram showing a configuration of the multiprocessor system according to the first embodiment of the present invention. In FIG. 1, 101 is a first processor, 111 is a second processor, and 121 is an n-th processor.
These processors are connected to the main memories, retrieve instruction codes from the main memories, and execute execution programs.
Reference numerals 102, 112, and 122 denote main memories, which store execution programs. Note that storing the execution program in the main memory is also referred to as storing the execution program in the main memory.

A bus 103 transfers an execution program from the main memory 102 to the first processor 101. 1
A bus 13 also transfers an execution program from the main memory 112 to the second processor 111. A bus 123 transfers an execution program from the main memory 122 to the n-th processor 121. 104 indicates the direction of the flow of the instruction code transferred from the main memory 102 to the first processor 101. 114 is the second processor 1 from the main memory 112
11 shows the direction of the flow of the instruction code transferred. 12
4 indicates the direction of the flow of the instruction code transferred from the main memory 122 to the n-th processor 121.

Reference numeral 105 denotes an LSI as a semiconductor chip, in which the first processor 101, the main memory 102, and the bus 103 are integrated into one chip. Note that LSI
The instruction code is input to the first processor 101 from the main memory 102 via the bus 103 at high speed. Reference numeral 115 denotes an LSI which is a semiconductor chip.
Processor 111, main memory 112, and bus 113 are integrated into one chip. Note that, on the LSI 115, the second processor 111
An instruction code is input from the main memory 112 at high speed. 1
Reference numeral 25 denotes an LSI which is a semiconductor chip, in which the n-th processor 121, the main memory 122, and the bus 123 are integrated into one chip. Note that the n-th LSI
Of the main memory 1 via the bus 123
From 22, an instruction code is input at a high speed.

Reference numeral 106 denotes an external bus.
To 125 are connected. That is, the external bus 106 connects the bus 103, the bus 113, and the bus 123. By using the external bus 106, each of the main memories 102 to 1
The execution program can be stored separately in the storage 22.

Next, a memory map in the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 2 is a conceptual diagram showing a memory map in the multiprocessor system of the present embodiment. In FIG.
600 is an address space. 601 is address space 6
At 00, a first processor area, 602 is a second processor area, and 603 is an n-th processor area. 604 is a free area. Note that address space 6
00 includes a first processor area 601 to an n-th processor area 603, and a free area 604.

The first processor area 601 is:
It starts from address 0 of the address space 600. In addition, the first processor area 601 and the second processor area 60
The processor areas of the second to n-th processor areas 603 are ordered from the one closer to address 0 in the memory map. The order assigned to each of these processor areas,
For example, “first” is also the identification number of the corresponding processor. Further, the first processor area 601 is allocated to the main storage 102. The second processor area 602 is allocated to the main storage 112. Further, the n-th processor area 603 is allocated to the main memory 122.

Note that the access from the first processor 101 to the main memory 102 via the bus 103 is more efficient than the access from another processor via the external bus 106.
Be fast. In addition, the access from the second processor 111 to the main memory 112 via the bus 113 is higher than the access from another processor via the external bus 106.
Be fast. Further, access from the n-th processor 121 to the main memory 122 via the bus 123 is faster than access from another processor via the external bus 106.

Next, the configuration at the time of execution of the execution program in the multiprocessor system of this embodiment will be described with reference to FIG. FIG. 3 is a configuration diagram showing a configuration at the time of execution of an execution program in the multiprocessor system of the present embodiment. In FIG. 3, reference numeral 701 denotes a first processor, 711 denotes a second processor, and
1 is an n-th processor. 702, 712, 722
Is a main memory in which an execution program is stored. 703
Is a bus, and an execution program is transferred from the main memory 702 to the first processor 701 via the bus 703. Reference numeral 713 denotes a bus through which an execution program is transferred from the main memory 712 to the second processor 711. Reference numeral 723 denotes a bus through which an execution program is transferred from the main memory 722 to the n-th processor 721.

Reference numeral 704 denotes the direction of the flow of the instruction code transferred from the main memory 702 to the second processor 711;
Indicates the direction of the flow of the instruction code transferred from the main storage 712 to the second processor 711, and 724 indicates the direction of the flow of the instruction code transferred from the main storage 722 to the second processor 711. Reference numeral 705 denotes an LSI in which the first processor 701, the main memory 702, and the bus 703 are integrated into one chip. Reference numeral 715 denotes an LSI in which the second processor 711, the main memory 712, and the bus 713 are integrated into one chip. An LSI 725 includes an n-th processor 721, a main memory 722, and a bus 723.
Is one chip. An external bus 706 connects the LSI 705, the LSI 715, and the LSI 725.

In FIG. 3, the instruction code of the execution program is transferred from each main memory to the second processor 711. This is because it is assumed that the frequently used portion of the execution program has been stored in the main memory 712 formed as one chip together with the second processor 711. As described above, the second processor 711 corresponding to the main memory 712 storing the frequently used part of the execution program includes:
By processing the instruction code of the execution program,
Frequently used portions of the execution program can be processed at high speed, and the execution program can be executed efficiently.

Note that the second processor 711 corresponding to the main memory 712 refers to the second processor 711 integrated with the main memory 712 into one chip. A main processor 712 and a second processor 711 integrated into one chip
Transfers the instruction code of the execution program from the main memory 712 to the second processor 711 at high speed using the bus 713 also formed as one chip. Therefore, the second processor 711 can process a frequently used portion of the execution program at a high speed, and can efficiently execute the execution program. Further, the frequently used portion of the execution program is a portion that requires a lot of time to execute, that is, a portion in which the number of steps of the execution program or the number of instruction codes corresponding to the execution program is large.

As described above, the multiprocessor system according to the present embodiment selects the one-chip processor together with the main memory in which the most frequently used portion of the execution program is stored, which takes the longest time to execute the execution program. However, since the execution program is executed by using the selected processor, a region where the execution program can be executed at a high speed and a region where the execution program cannot be executed are fixed as in a conventional multiprocessor system, In many cases, the execution efficiency of the execution program can be increased.

Embodiment 2 Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is the same as the first embodiment shown in FIG.
Next, a memory map in the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 4 is a conceptual diagram showing a memory map in the multiprocessor system of the present embodiment. FIG. 4 is a layout diagram showing the layout of the execution programs. In FIG. 4, reference numeral 800 denotes an address space. 801 is the first processor area in the address space 800, and 802 is the address space 8
Reference numeral 803 denotes a second processor area in the address space 800.
Note that the first processor area 801 starts from address 0 of the address space 800.

Reference numeral 804 denotes a processor change code area, which is located between the first processor area 801 and the second processor area 802, between the second processor area 802 and the third processor area 803, And so on. The processor change code area 804 includes
An instruction code, which is a switching instruction of a processor responsible for executing the execution program, is set. 805 is an address space 80
0 is an empty area. Note that the address space 800
Is composed of a first processor area 801 to a third processor area 803, a processor change code area 804, and a free area 805.

Normally, the execution program is executed in ascending order of the address which is the address. That is, in FIG. 4, the processing is performed in order from the bottom. For example,
When the instruction code of the execution program stored in the main memory 102, which is one processor area 801, is executed first, then the instruction code in the processor change code area 804 is executed. Then, according to the instruction code in the processor change code area 804, the third processor area 8
03 is designated, the first processor 101 which has been responsible for executing the execution program up to that point is designated.
The data of the execution environment of the third
To the processor. The data of the execution environment refers to the value of the execution program counter, the value of the plug, and the value of the register of the processor that is executing the execution program. And the data of the execution environment of the first processor is the third
When the instruction code of the first processor area 801 is executed, the instruction code of the third processor area 803 is not executed after the instruction code of the second processor area 802 is executed. Be executed. Of course,
The instruction code of the third processor area 803 is
Executed by the processor.

After the instruction code in the first processor area 801 is executed, the processor change code area 8
04 is executed, and when the instruction code in the processor change code area 804 specifies that the processing proceeds to the second processor area 802, the first execution code that has been responsible for executing the execution program up to that point is executed. Processor 1
01 is transferred to the second processor 111 via the external bus 106. When the data of the execution environment of the first processor 101 is transferred to the second processor 111, the first processor area 801
Are executed, the instruction codes in the second processor area 802 are sequentially executed. Naturally, the instruction code in the second processor area 802 is executed by the second processor 111.

After the execution of the instruction code in the second processor area 802, the processor change code area 8
04 is executed, and when the instruction code of the processor change code area 804 specifies that the processing proceeds to the third processor area 803, the second execution code that has been responsible for executing the execution program up to that point is executed. Processor 1
The data of the eleventh execution environment is transferred to the third processor via the external bus 106. Then, when the data of the execution environment of the second processor 111 is transferred to the third processor, the instruction code of the second processor area 802 is executed, and then the instruction code of the third processor area 803 is changed. It is executed in order. Naturally, the instruction code in the third processor area 803 is executed by the third processor.

Note that the instruction code of the first processor area 801 is the instruction code of the execution program stored in the main storage 102, and the second processor area 8
02 is the instruction code of the execution program stored in the main storage 112, and the instruction code of the third processor area 803 is the instruction code of the execution program stored in the corresponding main storage. It is.

As described above, the instruction code of the execution program stored in each main memory is changed every time the main memory is switched.
By switching the processing to be performed by the corresponding processor, access to the main storage by the processor via the bus is speeded up, and the execution efficiency of the execution program is improved. That is, the processor does not use the external bus 106 to access the instruction code of the execution program stored in the main storage, thereby preventing the execution efficiency of the execution program from lowering. The corresponding processor is
This is a processor integrated with the main memory via a bus.

Further, switching the processor every time the main memory is switched makes it possible to achieve a higher speed process than processing only a portion where the execution program is frequently used by using a high speed bus. This is because even an infrequently used place of the execution program is transferred and processed using a high-speed bus. Switching between the main memory and the processor and switching is performed by an instruction code set in a processor change code area provided between adjacent processor areas. The instruction code set in the processor change code area transfers and sets data of the execution environment of the execution program to the processor corresponding to the next processor area using the external bus 106.

Embodiment 3 Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is substantially the same as the embodiment shown in FIG. Next, a mechanism for transferring data of the execution environment of the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 5 is a configuration diagram showing a configuration of a mechanism for transferring data of an execution environment included in the multiprocessor system of the present embodiment. In FIG. 5, reference numeral 900 denotes a 0th general-purpose register included in each processor, 901 denotes a first general-purpose register included in each processor, and 902 denotes an nth general-purpose register included in each processor.

A validity flag 910 indicates whether or not the data of the execution environment stored in the 0th general-purpose register 900 is valid. Reference numeral 911 denotes a validity flag.
Indicates whether the data of the execution environment stored in the general-purpose register 901 is valid. A validity flag 912 indicates whether the data of the execution environment stored in the n-th general-purpose register 902 is valid. Note that the initial value of the validity flag is 0, indicating that the data stored in the corresponding general-purpose register is invalid. When the value of the validity flag is 1, it indicates that the data stored in the corresponding general-purpose register is valid. The value of the validity flag becomes 1 when data is written to the corresponding general-purpose register from outside such as main memory, when data is transferred from another general-purpose register to the corresponding general-purpose register, For example, a case where some operation result is written to the corresponding general-purpose register. A next execution processor number register 920 stores the identification number of the processor that executes the next execution program. The processor that next executes the execution program is determined during the execution of the execution program.

When an arbitrary processor included in the multiprocessor system of the present embodiment fetches an instruction code from the main memory which is a processor area corresponding to another processor during execution of the execution program, The validity flags 910 to 912 are automatically set to 1,
The valid data stored in the general-purpose register corresponding to the validity flag is transferred to the processor of the identification number recorded in the next execution processor number register 920. In addition,
For example, the valid data stored in the 0th general-purpose register is transferred from the 0th general-purpose register of the processor currently executing the execution program to the 0th general-purpose register of the processor executing the next execution program. The valid data stored in the first general-purpose register conforms to this. Then, the validity flag of the processor that has transmitted the valid data stored in the general-purpose register is reset to 0, and the validity flag of the processor that has received the transmitted valid data indicates 1. The validity flags of the processors not related to the transmission / reception of the valid data are also reset to 0. The processor that has received the valid data immediately starts executing the execution program.

By providing such a data transfer mechanism of the execution environment in the multiprocessor system, an instruction code for switching the processor and an instruction code for transferring the execution environment data to the processor are embedded in the execution program in advance. This eliminates the necessity, facilitates the construction of the execution program, and makes it possible to automatically transfer the data of the execution environment when the processor is switched.

Embodiment 4 FIG. Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is substantially the same as the embodiment shown in FIG. Next, a mechanism for detecting a departure from an area of the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 6 is a configuration diagram showing a configuration of a mechanism for detecting that the multiprocessor system according to the present embodiment has deviated from an area. The area is an area for a processor. In FIG. 6, reference numeral 1001 denotes a lower limit storage register of an area, which is provided in each processor. Each processor has a unique area lower limit storage register 10.
01, and the lower limit address of the area allocated to the processor is set in advance.

Reference numeral 1011 denotes an area upper limit storage register provided in each processor. Each processor has a unique region upper limit storage register 1011, and the upper limit address of the region assigned to the processor is set in advance. A program counter 1002 counts the address of an execution program. A processor having the program counter 1002 outputs a program counter output 101 which is an output of the program counter 1002.
2, the instruction code is extracted.

A comparator 1003 compares the address value of the program counter output 1012 with the set value set in the lower limit storage register 1001 of the area. Then, the address value of the program counter output 1012 is
When the value becomes smaller than the set value set in the lower limit storage register 1001 of the area, a signal 1004 is output. 1
Reference numeral 013 denotes a comparator, which is a program counter output 101
2 is compared with the set value set in the upper limit storage register 1011 of the area. Then, when the address value of the program counter output 1012 becomes larger than the set value set in the area upper limit storage register 1011, a signal 1014 is output. Reference numeral 1005 denotes an OR gate circuit, which outputs the signal 1 output from the comparator 1003.
004, the signal 1014 output from the comparator 1013 is input. Reference numeral 1015 denotes a detection signal output, which is output from the OR gate circuit 1005. The detection signal output 10
15, it is determined whether or not the execution address of the execution program has deviated from the predetermined processor area.

As described above, by providing a mechanism for detecting the departure from the area, it is possible to easily change the processor area and the processor in the execution program.

Embodiment 5 Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is the same as the first embodiment shown in FIG.
Next, a memory map in the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 7 is a conceptual diagram showing a memory map in the multiprocessor system of the present embodiment. 7, reference numeral 1111 denotes an execution program module 1 use area, 1112 denotes an execution program module 2 use area, 1113 denotes an execution program module 3 use area, and 1114 to 1115 denote unused areas.

Reference numeral 1101 denotes a first processor area, which has an execution program module 1 use area 1111 and an unused area 1114. Reference numeral 1102 denotes a second processor area, which is an execution program module 2 use area 1112 and an execution program module 3 use area 11
13 and an unused area 1115. 1103 is a free area, which is not implemented in the main storage. 1
An address space 100 includes a first processor area 1101, a second processor area 1102, and a free area 1103.

As described above, by storing the execution program stored in the main memory of each processor area in units of modules for each operation, an instruction command group of an operation to be included in one module is divided into a plurality of groups. Is stored in the processor area, that is, a plurality of main memories. It is assumed that the command command group is a set of a plurality of command commands. In other words, the frequency of switching between the main memory and the processor corresponding to the main memory due to the division of a module that is a certain operation into a plurality of main memories can be suppressed, and the processing of the execution program can be performed smoothly and at high speed. Done in For example, when an instruction command group relating to a repetitive operation, that is, a loop operation is divided and recorded in a plurality of main memories, the frequency of switching between the main memory and the processor becomes extremely high, and such an instruction command group is regarded as one module. Storing in one main memory and processing by one corresponding processor makes the execution of the execution program extremely smooth and faster.
This is generally called locality of an execution program.

Embodiment 6 FIG. Another embodiment of the multiprocessor system according to the present invention will be described with reference to FIG. FIG. 8 is a configuration diagram showing a configuration of a multiprocessor system according to Embodiment 6 of the present invention. In FIG. 8, 1
201 is a first processor, 1211 is a second processor, and 1221 is an n-th processor. Reference numeral 1202 denotes a main memory, which corresponds to the first processor 1201. 1
212 is a main memory, which corresponds to the second processor 1211. Reference numeral 1222 denotes a main memory, and the n-th processor 1
221. Reference numeral 1203 denotes an address bus.
One processor 1201 and main memory 1202 are connected. An address bus 1213 connects the second processor 1211 and the main memory 1212. An address bus 1223 connects the n-th processor 1221 to the main memory 1222. An address conversion circuit 1206 is provided on the address bus 1203. An address conversion circuit 1216 is provided on the address bus 1213. An address conversion circuit 1226 is provided on the address bus 1223.

An offset address register 1204 is connected to the address conversion circuit 1206. The offset address register 1204 stores an offset value that is an offset address. The offset address register 1204 is connected to the address conversion circuit 1206. Reference numeral 1214 denotes an offset address register, which is connected to the address conversion circuit 1216. In this offset address register 1214,
The offset address is stored. Further, the offset address register 1214 stores the address conversion circuit 12
16 is connected. Reference numeral 1224 denotes an offset address register, which is connected to the address conversion circuit 1226.
This offset address register 1224 stores an offset address. The offset address register 1224 is connected to the address conversion circuit 1226.

Reference numeral 1205 denotes a semiconductor chip, which includes a first processor 1201, a main memory 1202, and an address bus 12.
03, the address conversion circuit 1206 and the offset address register 1204 are integrated into one chip.
Reference numeral 1215 denotes a semiconductor chip.
11, main memory 1212, address bus 1213, address conversion circuit 1216 and offset address register 1
Reference numeral 214 denotes a single chip. Reference numeral 1225 denotes a semiconductor chip, which is an n-th processor 1221, a main memory 1222, an address bus 1223, an address conversion circuit 1
226 and the offset address register 1224 are integrated into one chip.

The address conversion circuit 1206 stores the address indicated by the address signal of the instruction code in the main memory 120.
2 is converted into the address. The address conversion circuit 1216 converts an address indicated by the address signal of the instruction code into an address in the main memory 1212. Further, the address conversion circuit 1226 stores the address indicated by the address signal of the instruction code in the main memory 122.
2 is converted into the address. The address indicated by the instruction code address signal is the address of the instruction code on the memory map. The address signal passes through the address bus. As described above, since the multiprocessor system of the present embodiment is provided with the address translation mechanism, the instruction code of the execution program to which a series of addresses on the memory map is assigned is stored in each processor area, that is, in each main memory. Addresses are easily translated.

For example, the second processor 1211 outputs an address signal based on a memory map in order to read a certain instruction code from the main memory 1212. An address signal based on the memory map output from the second processor 1211 is input to an address conversion circuit 1216 through an address bus 1213. The address signal based on the memory map input to the address conversion circuit 1216 is added with the offset value “-1002” (hexadecimal notation) stored in the offset address register 1214, and the memory map output from the second processor 1211 is added. Is converted into an instruction code address in the main memory 1216 stored in the main memory 1216. In this example, the offset value is “−100”.
2 "(in hexadecimal notation).
Has a storage capacity of 1002 bytes (hexadecimal notation).
KB. When the storage capacity of the main memory is 2 to the power of n, the address conversion circuit does not add the offset value, but may simply mask a higher-order part than the address signal required by the main memory. .

Note that the conversion of the address, which is the address in the memory map, into the address in each main memory may be realized by software instead of hardware. Also,
The conversion of the address in the memory map into the address in each main memory may not be performed when executing the execution program, but may be performed when loading the execution program. In addition,
When converting an address in the memory map into an address in each main memory, it is necessary to convert a jump destination address to which a jump instruction is issued.

Embodiment 7 FIG. Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is substantially the same as the embodiment shown in FIG. Next, a method of occasionally outputting a change in data of the execution environment performed by the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 9 is a conceptual diagram showing a method of outputting a change in the data of the execution environment performed by the multiprocessor system of the present embodiment at any time. In FIG. 9, reference numeral 1300 denotes a 0th general-purpose register, 1301 denotes a first general-purpose register, and 1302 denotes an n-th general-purpose register.

Reference numerals 1310 denote register write request commands to general-purpose registers. Note that the register write request command 1310 includes the case of storing an operation result in a general-purpose register or the like, in addition to the data transfer from the outside or another general-purpose register. Although the above description has been given of a general-purpose register, the same applies to other dedicated registers. 1320 is a processor. An execution environment change output 1311 is output to another processor different from the processor 1320 as needed. That is, the register write request 1310 to the general-purpose register is used for writing to the general-purpose register, and is also transferred to another processor as it is, and is used as the execution environment change output 1311.

As described above, in the multiprocessor system of the present embodiment, the transfer of data relating to the execution environment to the processor that executes the execution program is performed by the processor (the old processor) that has been executing the execution program. Next, instead of performing the switching at the time of switching to the processor that executes the execution program (hereinafter referred to as a new processor), the processing is performed every moment before the switching. In other words, the transfer of data about the execution environment
Rather than suddenly transfer to the new processor when switching from the old processor, while the execution program is running on the old processor, data about the execution environment is transferred to other processors other than the old processor including the new processor at any time Then, when switching from the old processor to the new processor, the execution of the execution program can be switched more smoothly and efficiently.

It should be noted that it is better to write the change of the execution environment data into the register of the processor executing the execution program quickly in order to execute the execution program efficiently. However, the writing of the change of the execution environment data to the register of another processor that is not executing the execution program may be performed after the change is written to the register of the processor that is executing the execution program. The writing of the change of the execution environment data to the register of the processor executing the execution program is based on the register write request command. The writing of the change of the execution environment data to the register of another processor which is not executing the execution program is based on the execution environment change output.

Embodiment 8 FIG. Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is substantially the same as the embodiment shown in FIG. Next, a method for occasionally outputting a change in execution environment data performed by the multiprocessor system of the present embodiment will be described.
This will be described with reference to FIG. FIG. 10 is a conceptual diagram showing a method of outputting a change in execution environment data performed by the multiprocessor system of the present embodiment at any time. In FIG. 10, reference numerals 1401 denote register write request commands. Note that a plurality of register write request commands form a continuous queue. Reference numeral 1402 denotes a process of writing a register write request command to a register, and also an output of a change in execution environment data. In FIG. 10, the same or corresponding parts as those in the seventh embodiment shown in FIG. 9 are not described, and the parts different from FIG. 9 are described.

FIG. 10 shows a state in which four register write request commands 1401 are waiting in a queue. The write destinations of these four register write request commands 1401 are R1, R2, R3, and R2 in the order in which the write processing is performed. Note that R1
Is a first general register, R2 is a second general register, and R3 is a third general register. From these, the processor knows that the two register write request commands to R2 are waiting in the queue, and the previous register write request command to R2 is rewritten by the subsequent register write request command to R2. I understand that.
Therefore, the processor cancels the previous register write request command to R2. As described above, in the case of a plurality of register write request commands waiting in the queue, if there are a plurality of register write request commands to which the write destination is the same, only the last register write request command is left, and the previous register write request command is left. The register write request command to the register is canceled. Therefore, the occurrence of redundant processing inside and outside the processor is suppressed, and the execution of the execution program can be performed efficiently.

Embodiment 9 FIG. Another embodiment of the multiprocessor system according to the present invention will be described. In addition,
The configuration of the multiprocessor system of the present embodiment is shown in FIG.
Is substantially the same as the embodiment shown in FIG. Next, a method for occasionally outputting a change in execution environment data performed by the multiprocessor system of the present embodiment will be described.
This will be described with reference to FIG. FIG. 11 is a conceptual diagram showing a method of outputting a change in execution environment data performed by the multiprocessor system of the present embodiment as needed. In FIG. 11, reference numeral 1500 denotes a 0th general-purpose register, 1501 denotes a first general-purpose register, and 1502 denotes an n-th general-purpose register. 151
0 is a register write request command.
Reference numeral 1511 denotes an execution environment change output. Reference numeral 1512 denotes an order in which the register write request command 1510 is generated. 1
520 is a processor. In FIG. 11, the description of the parts corresponding to the seventh embodiment shown in FIG. 9 is omitted, and the parts different from FIG. 9 are described.

The transfer of the execution environment data to the general-purpose register of a certain processor may be performed until the general-purpose register is used for the first time after switching to the processor. Thus, when the execution environment change output is output from the queue in consideration of the order of use of the general-purpose registers after the switching of the processor, efficient execution of the execution program can be realized. Therefore, when creating the execution program, it is desirable to create the execution program so that the execution environment change output is output in consideration of the order and timing of the general-purpose registers used. Further, the execution environment change output may be output to the outside in the execution order of the instruction commands, that is, in the order in which the register write request command to the register is generated. This is because, in a processor adopting the pipeline system, the access from the general-purpose register may not be possible immediately after writing the change of the execution environment data to the general-purpose register. This is because the instruction code is output so as not to use the general-purpose register immediately after writing as much as possible.

Embodiment 10 FIG. Another embodiment of the multiprocessor system according to the present invention will be described. The configuration of the multiprocessor system of the present embodiment is as follows.
This is almost the same as the embodiment shown in FIG. 1, and the description thereof is omitted. Next, a method for occasionally outputting a change in execution environment data performed by the multiprocessor system of the present embodiment will be described with reference to FIG. FIG. 12 is a conceptual diagram showing a method of outputting a change in execution environment data performed by the multiprocessor system of the present embodiment at any time. In FIG. 12, each of 1601 is a register write request command. 1602 is an instruction decoder. 160
3 is an instruction code.

Reference numeral 1611 denotes a write register signal.
When the instruction code 1603 is decoded by the instruction decoder 1602, it is output from the instruction decoder 1602. The write register signal 1611 specifies a general-purpose register that processes the register write request command. When the write register signal 1611 is output from the instruction decoder 1602, it is determined whether the processing order of an arbitrary register write request command is changed or whether the arbitrary register write request command is canceled. In FIG. 12, a register write request command 1601 to R2 is a write register signal 161.
1 and its rank has been lowered. 161
Reference numeral 2 denotes a process of writing a register write request command to a register, and also an output of a change in execution environment data.

In FIG. 12, portions corresponding to the eighth embodiment shown in FIG. 10 are not described, and portions different from FIG. 10 are described. In a processor employing a pipeline system, decoding of an instruction code,
Operations such as execution of an instruction code and writing of an execution result are sequentially executed. Then, there is a time difference of several clocks from when the instruction code is decoded to when the execution result of the instruction code is actually written to a predetermined general-purpose register. Therefore, at the time of decoding by the instruction decoder, the general-purpose register to which the execution result of the instruction code is written can be specified, and when the instruction code is decoded by the instruction decoder, the execution environment data is set in the general-purpose register. When the register write request command, which is the execution environment change output, is in the queue, the order in which the register write request command is output is lowered, or the execution result of the instruction code is reliably written to the general-purpose register. , The output of the register write request command can be canceled.

The output of the execution environment change from one processor to another different processor normally uses an external bus. Also, the execution environment change output is provided with a dedicated bus,
The output may be from one processor to another different processor. As described above, when the execution environment change output is output using the dedicated bus, the data transfer relating to the execution program and the data transfer relating to the change in the execution environment data can be transmitted separately, and the occurrence of a failure in the mutual data transfer can occur. The probability can be suppressed, and the execution program can be executed efficiently.

In the multiprocessor system according to the present embodiment, for example, the first execution program is stored so as to straddle the first and second main memories, and the second execution program is stored in the first main memory. When stored together with the first execution program, when the first execution program is executed by the processor corresponding to the second main storage, the processor corresponding to the first main storage executes the second execution program by the second main storage. 1
Program can be executed simultaneously. That is,
In at least one main memory of the plurality of main memories, for example, the first
And the second execution program are loaded, the first processor corresponding to the first main storage and the second processor corresponding to the second main storage have different first execution programs and second execution programs. 2 can be executed simultaneously, and a plurality of execution programs can be executed efficiently.

Further, an execution program in a certain main memory may be loaded, and the execution program may be executed using a plurality of processors. As described above, by causing a plurality of processors to simultaneously execute one execution program, the execution program can be efficiently executed. In the case where one execution program is executed by a plurality of processors, the execution program is copied to the corresponding main storages, and the execution of the execution program by the plurality of processors is realized.

[0079]

As described above, the multiprocessor system according to the present invention has a plurality of semiconductor chips each having a processor, a main memory, and a bus connecting the processor and the main memory. One address space is configured, and a program recorded in the main memory to which a predetermined area of the address space is allocated is processed by a processor provided on the same semiconductor chip as the main memory, and is stored in one semiconductor chip. Even a program having a large storage capacity that cannot be integrated on the above can be executed at high speed as when integrated on one semiconductor chip.

Further, the multiprocessor system according to the present invention, when the processing shifts from a program recorded in a certain main memory to a series of programs recorded in another main memory, a processor corresponding to the certain main memory. To the processor corresponding to the other main memory, and outputs the setting environment data set in the processor corresponding to the certain main memory to the processor corresponding to the other main memory. Each time the main memory is switched,
The processing is switched so as to be processed by the corresponding processor, the access to the main memory by the processor via the bus is sped up, and the execution efficiency of the program is improved.

Further, in the multiprocessor system according to the present invention, the entire program can be divided into functional modules and recorded in the main memory in units of the modules. Is not divided and stored in a plurality of main memories, the frequency of switching processing between the main memory and the processor corresponding to the main memory can be suppressed, and the processing of the program is performed smoothly and at high speed.

The multiprocessor system according to the present invention outputs setting environment data set in a certain processor from one processor to another processor to another processor as needed, and transfers the setting environment data to another processor. Since the transfer can be performed gradually, not suddenly, the switching of the processor is performed more smoothly.

Further, in the multiprocessor system according to the present invention, a plurality of setting environment data are accumulated, and if the output destination is the same among the plurality of accumulated setting environment data, the last setting environment data is stored. Only the generated setting environment data is output, and the occurrence of redundant processing inside and outside the processor is suppressed, and the program can be executed efficiently.

The multiprocessor system according to the present invention records a part of a program in a main memory of each semiconductor chip, and executes a part of the program in parallel by a processor corresponding to the main memory. The program can be executed efficiently.

Further, in the multiprocessor system according to the present invention, a first main memory in which a part of the first program and a second program are recorded, and a first main memory different from the first main memory.
A second main memory in which the other part of the first program is recorded, and when the other part of the first program is executed by a processor corresponding to the second main memory, a processor corresponding to the first main memory is provided. In this case, the second execution program is executed, different programs can be executed simultaneously by the two processors, and a plurality of programs can be executed efficiently.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of a multiprocessor system according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a memory map in the multiprocessor system according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram illustrating a configuration at the time of execution of an execution program in the multiprocessor system according to the first embodiment of the present invention;

FIG. 4 is a conceptual diagram showing a memory map in a multiprocessor system according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating a configuration of a mechanism for transferring data of an execution environment included in a multiprocessor system according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram illustrating a configuration of a mechanism that detects a departure from an area of a multiprocessor system according to a fourth embodiment of the present invention.

FIG. 7 is a conceptual diagram showing a memory map in a multiprocessor system according to a fifth embodiment of the present invention.

FIG. 8 is a configuration diagram illustrating a configuration of a multiprocessor system according to a sixth embodiment of the present invention.

FIG. 9 is a conceptual diagram illustrating a method of outputting a change in data of an execution environment performed by a multiprocessor system according to a seventh embodiment of the present invention as needed.

FIG. 10 is a conceptual diagram illustrating a method for outputting a change in execution environment data performed by a multiprocessor system according to an eighth embodiment of the present invention as needed.

FIG. 11 is a conceptual diagram illustrating a method for outputting a change in execution environment data performed by a multiprocessor system according to a ninth embodiment of the present invention as needed.

FIG. 12 is a conceptual diagram illustrating a method for outputting a change in execution environment data performed by a multiprocessor system according to a tenth embodiment of the present invention as needed.

FIG. 13 is a configuration diagram showing a configuration of a conventional multiprocessor system.

FIG. 14 is a configuration diagram showing a configuration of a Neumann computer system which is a basic configuration of a conventional multiprocessor system.

FIG. 15 is a configuration diagram showing a configuration of a conventional Neumann computer system that alleviates the problem of a bus bottleneck.

FIG. 16 is a configuration diagram showing a configuration of a conventional one-chip Neumann computer system in which a main memory is additionally provided.

[Explanation of symbols]

301 first processor, 302 main memory, 303
Bus, 304 instruction code flow direction, 311 second
Processor, 314 instruction code flow direction, 20
1 processor, 202 main memory, 203 bus, 20
4 Instruction code flow direction, 401 processor, 4
02 main memory, 403 bus, 404 instruction code flow direction, 405 semiconductor chip, 501 processor, 502 main memory, 503 bus, 504 instruction code flow direction, 505 semiconductor chip, 512 main memory, 513 bus, 514 instruction The direction of code flow,
515 semiconductor chip, 101 first processor, 10
2 main memory, 103 bus, 104 instruction code flow direction, 105 semiconductor chip, 106 external bus, 1
11 second processor, 112 main memory, 113 bus, 114 instruction code flow direction, 115 semiconductor chip, 121 nth processor, 122 main memory, 1
23 bus, 124 instruction code flow direction, 125
Semiconductor chip, 600 address space, 601 first
Processor area, 602 second processor area, 603 nth processor area, 604 free area, 701 first processor, 702 main storage, 70
3 Bus, 704 Instruction flow direction, 705
LSI, 706 external bus, 711 second processor, 712 main memory, 713 bus, 714 instruction code flow direction, 715 LSI, 721 nth processor, 722 main memory, 723 bus, 724 instruction code flow direction , 725 LSI, 800 address space, 801 area for first processor, 802 area for second processor, 803 area for third processor, 804 processor change code area, 805 free area, 900th general-purpose register, 901 1 general-purpose register, 902 n-th general-purpose register, 910 validity flag, 911 validity flag, 912 validity flag, 9
20th execution processor number register, 1001 lower limit storage register, 1002 program counter, 100
3 comparator, 1004 signal, 1005 OR gate circuit, 1011 upper limit storage register, 1012 program counter output, 1013 comparator, 1014 signal, 1015 detection signal output, 1100 address space, 1101 area for first processor, 1102 second Processor area, 1103 free area, 1111
Execution program module 1 use area, 1112 execution program module 2 use area, 1113 execution program module 3 use area, 1114 unused area, 1115 unused area, 1201 first processor, 1202 main storage, 1203 address bus, 12
04 offset address register, 1205 semiconductor chip, 1206 address conversion circuit, 1211 second
Processor, 1212 main memory, 1213 address bus, 1214 offset address register, 121
5 semiconductor chip, 1216 address conversion circuit, 12
21 nth processor, 1222 main memory, 1223
Address bus, 1224 offset address register, 1225 semiconductor chip, 1226 address conversion circuit, 1300 0th general-purpose register, 1301 first general-purpose register, 1302 nth general-purpose register, 1310
Register write request command, 1311 Execution environment change output, 1320 processor, 1401 register write request command, 1402 Write processing to register, 1500 0th general register, 1501 1st general register, 1502 nth general register, 1510
Register write request command, 1511 execution environment change output, 1512 register write request command generation order, 1520 processor, 1601 register write request command, 1602 instruction decoder, 160
3 instruction code, 1611 write register signal, 1
612 Write processing to register.

Claims (12)

[Claims] A plurality of semiconductor chips each including a processor, a main memory, and a bus connecting the processor and the main memory, wherein one main memory of each semiconductor chip forms one address space; A program recorded in the main memory to which the area is assigned is processed by a processor provided on the same semiconductor chip as the main memory. 2. When a process shifts from a program recorded in a certain main memory to a series of programs recorded in another main memory, a processor corresponding to the certain main memory transfers the program to the other main memory. 2. The multiprocessor system according to claim 1, wherein setting environment data set in a processor corresponding to the certain main storage is output to a processor corresponding to the other main storage. 3. The process transition from a program recorded in a certain main memory to a series of programs recorded in another main memory is performed by changing the address of the program recorded in the certain main memory to a predetermined address. 3. The multiprocessor system according to claim 2, wherein the determination is made based on whether or not the number has exceeded. 4. The multiprocessor system according to claim 1, wherein the entire program can be divided for each function module, and is recorded in the main memory in units of the module. 5. The processor according to claim 1, wherein the address in the address space is:
2. The multiprocessor system according to claim 1, wherein the address is converted into an address of a main memory corresponding to the processor. 6. The method according to claim 1, wherein the address of the address space is converted into an address of a predetermined main memory when a program is recorded in the main memory or when an address referred to by the program is used. The multiprocessor system according to claim 1. 7. From one processor to another processor,
2. The multiprocessor system according to claim 1, wherein the setting environment data set in the certain processor is output to the other processor as needed. 8. A plurality of setting environment data are accumulated, and among the accumulated plurality of setting environment data, when there is the same setting environment data whose output destination is the same, only the last setting environment data is output. The multiprocessor system according to claim 7, wherein: 9. The multiprocessor system according to claim 7, wherein execution of the program is monitored and output of the setting environment data is delayed. 10. The setting environment data is transmitted via a dedicated line.
3. The multiprocessor system according to claim 2, wherein a signal is output from one processor to another processor. 11. The program according to claim 1, wherein a part of the program is recorded in a main memory of each semiconductor chip, and a part of the program is executed in parallel by a processor corresponding to the main memory. Multiprocessor system. 12. A first main memory in which a part of a first program and a second program are recorded, and a second main memory in which another part of the first program different from the part is recorded. A main memory, wherein when the other part of the first program is executed by a processor corresponding to the second main memory, the processor corresponding to the first main memory executes the second execution program. A multiprocessor system characterized by being performed.