JP2001186372A - Horizontal deflection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the amplitude of horizontal deflection current constant regardless of switching of a horizontal deflection frequency. SOLUTION: When the horizontal deflection frequency is low, a switch S1 is turned on and the capacitance of a resonance capacitor C2 equivalently increases. Thus, DC voltage generated in an S curve correction capacitor C3 drops. Even if the deflection frequency is low and a scanning period is long, the amplitude of horizontal deflection current does not become large and the amplitude of horizontal deflection current can be set to a constant regardless of the change of the deflection frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection circuit such as a television receiver capable of receiving signals of a plurality of horizontal deflection frequencies.

[0002]

2. Description of the Related Art Conventionally, television receivers capable of receiving video signals of a plurality of horizontal frequencies have been commercialized. In order to keep the horizontal amplitude on the screen constant even when the horizontal frequency of the video signal changes, it is necessary to keep the amplitude I HPP of the horizontal deflection current flowing through the horizontal deflection coil constant. The horizontal deflection current amplitude I HPP is proportional to the power supply voltage V B supplied to the horizontal output circuit, and the horizontal deflection coil inductance L H
Is inversely proportional to

That is, assuming that the horizontal scanning period is TSH and the inductance of the horizontal deflection coil L1 is L1, the horizontal deflection current amplitude IPP can be expressed by the following equation (1).

[0004] IPHP = VB · TSH / LH ...
(1) As is apparent from the equation (1), in order to display images based on video signals of different horizontal frequencies on a common display screen with the same amplitude, the power supply voltage VB is set to the effective scanning period of each video signal. The level may be based on the ratio of. In other words, when receiving a video signal with a high horizontal frequency,
An equivalently high power supply voltage must be applied to both ends of the horizontal deflection yoke.

However, if this is done, the retrace pulse voltage generated at both ends of the deflection yoke during the retrace period also increases, exceeding the breakdown voltage of a general horizontal output transistor. Therefore, in Japanese Patent Application Laid-Open No. H11-127364, a horizontal deflection current is obtained by a horizontal output transistor having a relatively low withstand voltage even when the power supply voltage is increased by using two horizontal output transistors connected in series. Proposals have been made that make it possible.

FIG. 3 is a circuit diagram showing such a conventional horizontal deflection circuit.

In FIG. 3, a horizontal output transistor Q1
, Q2 are supplied with drive pulses at a predetermined timing from a drive circuit (not shown). The horizontal output transistor Q2 has a damper diode D2 and a resonance capacitor C2 connected in parallel between the collector and the emitter, and a horizontal deflection yoke DY and an S-shaped correction capacitor C3 connected between the collect and the reference potential point. Have been.

The horizontal output transistor Q1 has a collector connected to the emitter of the transistor Q2, an emitter connected to a reference potential point, a damper diode D1 and a resonance capacitor C1, a winding Lp and a DC power supply + B between the collector and the emitter. Are connected in parallel. As the winding Lp, a primary winding of a flyback transformer that generates a secondary winding with an anode voltage of a cathode ray tube and a voltage to be used in other circuits may be used.

In the conventional example configured as described above,
By supplying drive pulses to the bases of the transistors Q1 and Q2, a voltage higher than the power supply voltage + B is generated across the S-shaped correction capacitor C3. A retrace pulse generated at both ends of the deflection yoke DY during the retrace period is divided by the resonance capacitors C1 and C2 and applied to the transistors Q1 and Q2.

That is, even when the retrace pulse voltage is high, 1
The voltage applied to the horizontal output transistors is relatively low. Therefore, when the breakdown voltage is the same, the horizontal deflection circuit can be operated with a higher retrace pulse voltage when two horizontal output transistors are used than when one horizontal output transistor is used. The DC voltage generated in the capacitor C3 and the deflection current flowing in the deflection yoke DY can be changed by controlling the off-start timing and the off-period of the transistor Q2 by controlling the drive circuit.

It is also possible to change the horizontal deflection frequency by setting a drive pulse supplied to the horizontal output transistors Q1 and Q2. If the power supply voltage of the DC power supply + B (hereinafter, referred to as + B voltage) is not changed merely by changing the deflection frequency, as described above, the scanning period T
The deflection current I HPP fluctuates due to the change in SH, and the ratio of the raster display area to the effective display area of the display screen (hereinafter referred to as the scan rate) also changes. For example, when the horizontal deflection frequency is set low and the + B voltage is not changed, the peak-to-peak value of the deflection current increases, and the scan rate increases.

Therefore, by changing the drive pulse from the drive circuit to adjust the off timing of the transistor Q2, the + B voltage is changed, and a constant scan rate is obtained regardless of the change in the deflection frequency. I have.

However, the amount of change in the + B voltage by the drive circuit is relatively small, and cannot respond to a relatively large change in horizontal frequency.

[0014]

As described above, in the above-described conventional horizontal deflection circuit, a sufficient change amount of the power supply voltage corresponding to the change of the horizontal frequency cannot be obtained.
There has been a problem that the amplitude of the horizontal deflection current changes with the change of the horizontal frequency and the scan rate may change.

The present invention has been made in view of such a problem, and when two horizontal output transistors connected in series are used, regardless of a change in the horizontal frequency,
It is an object of the present invention to provide a horizontal deflection circuit capable of obtaining a horizontal deflection current having a constant amplitude.

[0016]

A horizontal deflection circuit according to the present invention comprises a first transistor having a base supplied with a horizontal period drive pulse, and a base having a horizontal period drive pulse supplied thereto and having an emitter having the first period. A second transistor connected to the collector of the first transistor, a first resonant capacitor connected between the collector and the emitter of the first transistor, and a second transistor connected between the collector and the emitter of the second transistor. A second resonance capacitor connected to the collector of the second transistor;
A series circuit of a horizontal deflection yoke and an S-shaped correction capacitor connected between the second deflection transistor and the emitter of the second transistor;
And capacitance switching means for equivalently changing the capacitance of the resonant capacitor according to the horizontal deflection frequency.

In the present invention, the first and second transistors are individually controlled, and a horizontal deflection current is caused to flow through the horizontal deflection yoke utilizing the resonance between the first and second resonance capacitors and the horizontal deflection yoke. . Due to the terminal voltages of the first and second resonance capacitors, a DC voltage higher than the power supply voltage is generated in the S-shaped correction capacitor. The capacitance switching means changes the DC voltage generated in the S-correction capacitor by equivalently changing the capacitance of the second resonance capacitor in accordance with the switching of the horizontal deflection frequency, thereby changing the horizontal deflection frequency. Irrespective of this, the horizontal deflection current is kept constant.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the horizontal deflection circuit according to the present invention. FIG.
3, the same components as those in FIG. 3 are denoted by the same reference numerals.

In FIG. 1, a drive pulse from a drive circuit (not shown) is supplied to the base of the transistor Q1. The transistor Q1 has its base connected to the reference potential point, and has a damper diode D1, a resonance capacitor C1 and a winding Lp between the collector and the emitter.
And a DC power supply + B series circuit are connected in parallel.

A drive pulse from a drive circuit (not shown) is also supplied to the base of the transistor Q2. The transistor Q2 has an emitter connected to the collector of the transistor Q1.
The damper diode D2 and the resonance capacitor C2 are connected in parallel. The collector of the transistor Q2 is connected to a reference potential point via a series circuit of a horizontal deflection yoke DY and an S-shaped correction capacitor C3.

In this embodiment, the transistor Q
A series circuit of a capacitor C4 and a switch S1 is also connected between the collector and the emitter of 2. The switch S1 is turned off (disconnected) when receiving a video signal having a high horizontal frequency, and turned on (conductive) when receiving a video signal having a low horizontal frequency.

Next, the operation of the embodiment configured as described above will be described.

Now, it is assumed that the switch S1 is turned off (non-conducting) in order to set the horizontal deflection frequency high in response to the reception of a video signal having a high horizontal frequency. In this case, the capacitor C4 and the switch S1 have no effect. Therefore, in this case, the same operation as the conventional circuit is exhibited.

That is, during the latter half of the horizontal period, a drive pulse from a horizontal drive circuit (not shown)
The transistors Q1 and Q2 are turned on at the same time. When the transistors Q1 and Q2 are turned on, a deflection current flows through the horizontal deflection yoke DY. In this case, the operation is the same as that of the horizontal deflection circuit using only one horizontal output transistor, and the horizontal deflection current increases at a gradient corresponding to the voltage across the S-shaped correction capacitor C3.

Next, when the horizontal period ends and the first half of the horizontal retrace period starts, only the transistor Q1 is first turned off by the drive pulse. At this point, the current flowing through the horizontal deflection yoke DY flows through the resonance capacitor C1 because the transistor Q2 is still conducting. That is, resonance starts.

If the transistor Q2 is turned off by a drive pulse before the deflection current reaches 0, another resonance capacitor C2 is connected in series with the horizontal deflection yoke DY, and the deflection current is also applied to the resonance capacitor C2. Flow in. As a result, a voltage is also generated at both ends of the resonance capacitor C2, and a pulse voltage larger than the pulse at both ends of the transistor Q1 can be applied to both ends of the horizontal deflection yoke DY.

In the latter half of the horizontal retrace period, the electric charge flowing into the resonance capacitors C1 and C2 flows out and flows to the deflection yoke DY. When the voltage across the capacitors C1 and C2 becomes zero, the damper diodes D1 and D2 automatically conduct. Since the current flowing into the resonance capacitor C2 is always smaller than the current flowing into the resonance capacitor C1, the resonance capacitor C2 loses its charge earlier, and the damper diode D2 conducts earlier than the damper diode D1.

When the damper diode D2 conducts in this way, a current flows through the deflection yoke DY via the damper diode D2 until the voltage across the resonance capacitors C1 and C2 becomes zero.

When the horizontal retrace period ends and the horizontal period begins, the horizontal deflection yoke DY supplies the damper diodes D1, D
2, the horizontal deflection current flows in the forward direction. By keeping the transistors Q1 and Q2 conductive during this time, the operation in the latter half of the horizontal period is performed again. Thus, a sawtooth horizontal deflection current flows through the horizontal deflection yoke DY.

Since the damper diode D2 always conducts earlier than the damper diode D1, the pulse generated at both ends of the transistor Q2 is higher than that of the transistor Q1.
The pulse width is narrower than the pulse generated at both ends of the pulse. If the off-timing of the transistor Q2 is further delayed, the current flowing into the resonance capacitor C2 is further reduced, so that the pulse width at both ends of the transistor Q2 becomes narrower and the pulse height becomes lower. That is, by controlling the phase of the off timing of the transistor Q2, the pulse voltage at both ends of the horizontal deflection yoke DY can be controlled, and as a result, the amplitude of the deflection current can be changed as described above.

In this case, the DC voltage generated at the S-correction capacitor C3 is higher than the voltage + B by the terminal voltage of the capacitor C2.

Here, it is assumed that a video signal having a low horizontal frequency is received. In this case, the switch S1 conducts. Then, the capacitor C4 is connected to the resonance capacitor C2.
Are connected in parallel. Therefore, assuming that the capacitances of the resonance capacitors C2 and C4 are C2 and C4, respectively, the capacitances of the resonance capacitors are equivalent to (C2 +
C4).

Also in this case, transistors Q 1,
The timing of conduction and non-conduction of Q2 and diodes D1 and D2 and the timing of charging and discharging of capacitors C1 and C2 are the same. That is, in the first half of the scanning period, the diodes D1 and D2 conduct. The diodes D1 and D2 are output from the horizontal deflection coil DY by the back electromotive force of the deflection coil DY.
A deflection current flows in the forward direction of. In the latter half of the scanning period, the transistors Q1 and Q2 are turned on, and a horizontal deflection current that flows in the horizontal deflection coil DY and increases substantially linearly in a direction opposite to the first half of the scanning period.

In the flyback period, the conduction is cut off in the order of the transistors Q1 and Q2, and the deflection current is first supplied to the resonance capacitor C1.
Next to 1, it is also applied to capacitors C2 and C4. When the current supply to the capacitors C1, C2, C4 stops,
The capacitors C1, C2 and C4 start discharging, and a current starts to flow in the horizontal deflection coil DY in the opposite direction. When the terminal voltages of the capacitors C2 and C4 become 0 first and then the terminal voltage of the resonance capacitor C1 becomes 0, the diodes D2 and C4
D1 sequentially conducts, and a new horizontal scan is started.

The DC voltage generated at the S-shaped correction capacitor C3 is the sum of the terminal voltage of the resonance capacitor C1 and the terminal voltages of the resonance capacitors C2 and C4, and the value is the capacitance of the resonance capacitor C1 and the resonance capacitors C2 and C2. It is determined by the ratio to the capacitance of C4 and the + B voltage value. Therefore, in this case, the DC voltage generated in the S-correction capacitor C3 is smaller than when the switch S1 is off.

By changing the capacitance C4 of the capacitor C4, the DC voltage generated at the S-shaped correction capacitor C3 can be changed. Accordingly, by appropriately setting the capacitance C4 in accordance with the scanning cycle of the video signal, the value of the deflection current flowing through the horizontal deflection yoke DY can be kept substantially constant regardless of the change in the deflection frequency.

As described above, in this embodiment, the value of the deflection current flowing through the horizontal deflection yoke DY can be kept substantially constant irrespective of the change in the deflection frequency, and the scan rate is kept constant even when the deflection frequency changes. Can be

FIG. 2 is a circuit diagram showing another embodiment of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment differs from the embodiment of FIG. 1 in that a switch S2 is provided instead of the series circuit of the capacitor C4 and the switch S1. The switch S2 becomes non-conductive when receiving a video signal having a high horizontal frequency,
When a video signal with a low horizontal frequency is being received, conduction is achieved.

Next, the operation of the embodiment configured as described above will be described.

Now, assume that a video signal having a high horizontal frequency is received. In this case, switch S2 is non-conductive. Therefore, switch S2 has no effect on the circuit. Therefore, in this case, the same operation as the conventional circuit is exhibited. The DC voltage generated at the S-shaped correction capacitor C3 is higher than the + B voltage.

On the other hand, when a video signal having a low horizontal frequency is being received, the switch S2 is turned on. As a result, the winding Lp is connected to the deflection yoke DY via the switch S2, and the operation of the transistor Q2, the damper diode D2 and the resonance capacitor C2 stops. That is, in this case, the horizontal output transistor Q1
An operation similar to that of a general horizontal deflection circuit using only the same is performed.

Accordingly, the DC voltage generated at the S-shaped correction capacitor C3 is substantially equal to the + B voltage. That is, the switch S2
Is turned on, the DC voltage generated in the S-correction capacitor C3 becomes smaller than when the switch S2 is non-conductive. Thus, the DC voltage generated in the S-shaped correction capacitor C3 can be reduced, so that the value of the deflection current flowing through the deflection yoke DY can be maintained substantially constant even when the scanning period becomes longer.

The function of the switch S2 can be achieved by the transistor Q2. That is, the switch S2 is omitted, the type of the transistor Q2 and the configuration of the drive circuit are appropriately selected, and when the deflection frequency is high, the transistor Q2 is turned on / off at an appropriate timing. It is apparent that the same operation and effect can be obtained as in the case of using the switch S2.

In each of the above embodiments, an example in which the deflection frequency is changed to two types is described. For example, a plurality of capacitors connected in parallel to the capacitor C2 are provided, and conduction of each capacitor is individually controlled by a plurality of switches. Obviously, by controlling, a plurality of types of deflection frequencies can be handled. Further, it is clear that both the series circuit of the capacitor C4 and the switch S1 and the switch S2 may be connected in parallel to the resonance capacitor C2.

[0046]

As described above, according to the present invention, when two horizontal output transistors are connected in series, a horizontal deflection current having a constant amplitude can be obtained irrespective of a change in horizontal frequency. It has the effect of.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a horizontal deflection circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional horizontal deflection circuit.

[Explanation of symbols]

Q1, Q2: Horizontal output transistor, D1, D2: Damper diode, C1, C2: Resonant capacitor, C3: S
Character correction capacitor, C4: capacitor, DY: horizontal deflection yoke, Lp: winding, + B: DC power supply, S1: switch.

Claims (4)

[Claims] A first transistor to which a horizontal period drive pulse is supplied to a base; and a second transistor to which a horizontal period drive pulse is supplied to a base and an emitter is connected to a collector of the first transistor.
A first resonant capacitor connected between the collector and the emitter of the first transistor; a second resonant capacitor connected between the collector and the emitter of the second transistor; A series circuit of a horizontal deflection yoke and an S-shaped correction capacitor connected between a collector of the second transistor and an emitter of the first transistor; and a capacitance of the second resonance capacitor according to a horizontal deflection frequency. A horizontal deflection circuit comprising: a capacitance switching means for equivalently changing the capacitance. 2. The capacitance switching means comprises a series circuit of a switch element and a third capacitor connected between a collector and an emitter of the second transistor, wherein the switch element has a horizontal deflection frequency. 2. The horizontal deflection circuit according to claim 1, wherein the circuit is turned on and off according to the height. 3. The capacitance switching means includes a switch element connected between a collector and an emitter of the second transistor, and the switch element turns off and on according to the level of a horizontal deflection frequency. The horizontal deflection circuit according to claim 1, wherein 4. The horizontal deflection circuit according to claim 1, wherein the capacitance switching means drives or constantly conducts the second transistor according to the level of a horizontal deflection frequency.