JP2001184805A - Clock extracting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock extracting device capable of shortening time by repulling so as not to largely deviate a PLL frequency deviate even when a reproduced signal from a disk is unstable and the undetected signal of the reproduced signal is not outputted. SOLUTION: A monitor circuit 6 always monitors the frequency of an oscillation clock outputted from a VCO 4, and a control circuit 7 performs on/off control of the drive of a charge pump circuit 2 making the frequency of the oscillation clock up and down with the undetected signal of an optical disk reproduced signal and a signal showing whether to be within the range of a prescribed frequency outputted from the circuit 6, higher or lower than the range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock for obtaining the operation timing of a disk information reproducing apparatus for reproducing recorded information from a disk such as an optical disk or a magneto-optical disk as a recording medium. The present invention relates to a clock extracting device that extracts a reproduced signal.

[0002]

2. Description of the Related Art Conventionally, as an information reproducing apparatus, for example, a recording medium such as a compact disk (CD), a digital video disk (DVD), a CD-ROM, a DVD-R.
In order to obtain a clock for operation timing of a disk information reproducing apparatus for reproducing recorded information from a disk such as an optical disk such as an OM, a magneto-optical disk such as a mini disk (MD), and a magnet optical disk (MO). As an information reproducing apparatus, a clock extracting apparatus for extracting a clock from a reproduction signal of the above-mentioned various disks is widely used.

[0003] Such a conventional clock extracting device will be described below. FIG. 3 is a block diagram showing a configuration of a general optical disk information reproducing apparatus which is one of information reproducing apparatuses using a clock extracting apparatus to obtain a clock for operation timing. In FIG. 3, 21 is a CD or D
The optical disk is a VD or the like, and is rotated by a spindle motor 22. 23 is a pickup,
The optical disk 21 is irradiated with a laser beam, and the reflected light from the optical disk 21 is detected, converted into a voltage value corresponding to the intensity, and output. This output is amplified by the head amplifier 24, binarized by the data slicer 25, and the information recorded on the optical disk 21 is restored as an optical disk reproduction signal HS1.

In order to perform signal processing such as demodulation and error correction on the optical disk reproduction signal HS1, an extraction clock CL1 synchronized with the optical disk reproduction signal HS1 is required.
The oscillation clock generated by the LL circuit 26 is used. FIG. 4 is a block diagram showing a configuration of a PLL circuit 26 used as a conventional clock extraction device. In FIG. 4, 1
Is a phase comparison circuit, 2 is a charge pump circuit, 3 is a current-
A filter circuit for performing voltage conversion, 4 is a voltage-controlled oscillator (using VCO as a symbol), and 5 is a charge pump, which generates an oscillation clock having a frequency controlled according to the voltage of the filter circuit 3 as an extraction clock CL1. This is a switch for stopping the circuit 2.

[0005] The operation of the clock extracting device configured as described above will be described below. FIG. 5 is a time chart showing a phase comparison operation in the phase comparison circuit 1 in the above clock extraction device. In this phase comparison circuit 1, as shown in FIG.
The phase of the CO 4 is compared with the oscillation clock CL 1, and the charge pump circuit 2 is driven according to the phase difference to charge and discharge the filter circuit 3. When the filter circuit 3 is charged, the input potential to the VCO 4 increases, and the frequency of the oscillation clock CL1 of the VCO 4 increases.

Conversely, when the filter circuit 3 discharges, the input potential to the VCO 4 decreases, and the frequency of the oscillation clock CL1 of the VCO 4 decreases. Oscillation clock CL
1 and the optical disk reproduction signal HS1, when the phase difference disappears, the charge pump circuit 2
Drives. The switch 5 includes a switch (U) 5a for turning on / off a drive input to an up-side terminal for outputting a current for increasing the frequency of the oscillation clock CL1 of the VCO 4 by the charge pump circuit 2, and a charge pump. A switch (D) 5b for turning on / off a drive input to a down side terminal for outputting a current for lowering the frequency of the oscillation clock CL1 of the VCO 4 by the circuit 2; and a non-detection signal HN1 of the optical disk reproduction signal. Is output from the head amplifier 24, so that the PLL frequency of the PLL circuit 26 does not greatly deviate from the locked state.
Switch (u) 5a and switch (d) 5b are both O
In the FF state, the operation of stopping the operation of the charge pump circuit 2 is performed.

[0007]

However, in the above-mentioned conventional clock extracting device, the optical disk reproduction signal HS1 drops out due to scratches or dirt on the reading surface of the optical disk 21, or vibrations to the optical disk information reproducing device. In this case, the charge pump circuit 2 is stopped by the non-detection signal HN1 of the optical disk reproduction signal so that the PLL frequency does not greatly deviate from the locked state,
Although the L frequency is held, as shown in FIG. 6, although not a dropout, the non-detection signal HN1 is not output immediately after access or when the optical disk reproduction signal HS1 is disturbed by an external vibration, but the optical disk reproduction signal is not output. HS
1 is unstable (the period during which the optical disk reproduction signal is unstable (t61 to t62)), the PLL frequency may deviate significantly from the desired frequency. In such a case, the control time until the pull-in of the PLL is completed ( PLL pull-in period (t
62 to t63)).

The present invention solves the above-mentioned conventional problem. The frequency of a PLL oscillation clock based on a reproduction signal from a disk is not greatly deviated from a normal reproduction state for the disk. Provided is a clock extracting device that can always control the frequency within a set frequency range and can shorten the control time at the time of re-locking.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a clock extracting apparatus according to the present invention always monitors the frequency of an oscillation clock of a PLL and attempts to deviate the frequency from a certain range. In addition, the input voltage of the voltage-controlled oscillator that outputs the oscillation clock is controlled so as to always keep it within the range.

As described above, the frequency of the oscillation clock of the PLL based on the reproduction signal from the disk is not greatly deviated from the normal reproduction state for the disk.
The control can be always performed within the set frequency range, and the control time at the time of re-drawing can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock extracting apparatus according to a first aspect of the present invention includes a PLL circuit that outputs an oscillation clock from a voltage-controlled oscillator based on a reproduction signal from a disk; With respect to the input voltage, when the frequency of the oscillation clock is higher than a predetermined frequency range obtained from a desired frequency, the change in the direction of increasing the frequency of the oscillation clock is stopped, and When the frequency is low, a means for stopping a change in a direction of decreasing the frequency of the oscillation clock is provided.

According to a second aspect of the present invention, there is provided a clock extraction apparatus, wherein a reproduction signal from a disk is input, and an oscillation loop is formed by a phase comparison circuit, a charge pump circuit, a filter circuit, and a voltage controlled oscillator. A PLL circuit for outputting an oscillation clock whose frequency is controlled in accordance with the output voltage of the charge pump circuit from the PLL circuit;
A frequency monitor circuit for monitoring an oscillation clock from the L circuit unit and generating a frequency position signal indicating whether the frequency is within a predetermined frequency range, higher than the range, or lower than the predetermined range; When the frequency of the oscillation clock is higher than a predetermined frequency range based on the detection signal and the frequency position signal from the frequency monitor circuit, the drive of the charge pump circuit for increasing the frequency of the oscillation clock is turned off. When the frequency of the oscillation clock is lower than a predetermined frequency range, the control circuit turns off the drive of the charge pump circuit to reduce the frequency of the oscillation clock.

According to these configurations, the frequency of the oscillation clock of the PLL is constantly monitored, and the output of the oscillation clock is maintained so that the frequency is always kept within the range when the frequency falls outside a certain range. The input voltage of the voltage-controlled oscillator is controlled. Hereinafter, a clock extracting device according to an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a clock extracting device according to the present embodiment in an optical disk information reproducing device which is one of information reproducing devices. In FIG. 1, P
1 is a PL configured similarly to the PLL circuit 26 shown in FIG.
L circuit section, 1 is a phase comparison circuit, 2 is a charge pump circuit, 3 is a filter circuit for performing current-voltage conversion, 4 is an oscillation clock CL1 having a frequency controlled according to the voltage of the filter circuit 3. Is a switch for stopping the current output operation of the charge pump circuit 2. 6 is VC
A frequency monitor circuit 7 for monitoring the frequency of the oscillation clock CL1 from O4, a non-detection signal HN1 of the optical disk reproduction signal, and a frequency of the oscillation clock CL1 output from the frequency monitor circuit 6 from the VCO 4 within a predetermined frequency range or This is a control circuit that controls the drive of the charge pump circuit 2 by the switch 5 based on a frequency position signal FP1 indicating whether the frequency is higher or lower than the range.

The switch 5 includes a switch (U) 5a for turning on / off a drive input to an up-side terminal for outputting a current for increasing the frequency of the oscillation clock CL1 of the VCO 4 by the charge pump circuit 2. And a switch (D) 5b for turning on / off a drive input to a down terminal for outputting a current such that the charge pump circuit 2 lowers the frequency of the oscillation clock CL1 of the VCO 4.

The operation of the clock extracting device in the information reproducing apparatus configured as described above will be described below. First, as a basic operation, the phase comparison circuit 1 generates the optical disk reproduction signal HS1 and the oscillation clock C from the VCO4.
The phase with L1 is compared, and the charge pump circuit 2 is driven according to the phase difference to charge / discharge the filter circuit 3 and determine the input potential of the VCO 4. The frequency monitor circuit 6 constantly monitors the frequency of the oscillation clock CL1 from the VCO 4, and outputs a frequency position signal FP1 indicating whether the frequency of the oscillation clock CL1 is within a predetermined frequency range, higher than the range, or lower than the range. I do.

The control circuit 7 outputs a signal for operating the switch 5 based on the non-detection signal HN1 of the optical disk reproduction signal and the frequency position signal FP1 output from the frequency monitor circuit 6, and using this signal, The switch 5 controls driving of the charge pump circuit 2. Next, a detailed operation will be described.

Non-detection signal HN1 from head amplifier 24
When the frequency of the oscillation clock CL1 from the VCO 4 becomes higher than a predetermined frequency range during a period in which the control circuit 7 is input to the control circuit 7, the control circuit (A) is controlled based on the frequency position signal FP1 from the monitor circuit (A) 6a. A) The switch (U) 5 on the frequency-up side according to the signal output from 7a
a becomes OFF, the frequency-up side of the charge pump circuit 2 stops, and the frequency of the oscillation clock CL1 does not increase.

Conversely, during the period when the non-detection signal HN1 from the head amplifier 24 is input to the control circuit 7, VC
When the frequency of the oscillation clock CL1 from O4 becomes lower than the predetermined frequency range, the control circuit (B) 7 is controlled based on the frequency position signal FP1 from the monitor circuit (B) 6b.
By the signal output from b, the switch (D) 5b on the frequency down side is turned off, the frequency down side of the charge pump circuit 2 stops, and the frequency of the oscillation clock CL1 does not decrease.

In the operation of the above-described clock extracting device, the frequency monitor circuit 6 monitors the frequency of the oscillation clock CL1 from the VCO 4 by counting the number of clocks per a predetermined time (for example, one second). Then, it is determined whether the count value is within a predetermined range, higher than the range, or lower than the range, and the frequency position signal F corresponding to each state is determined.
Output P1.

By operating as described above, as shown in FIG. 2, if the optical disk reproduction signal HS1 is in an unstable period (t1 to t2) and the frequency of the oscillation clock CL1 is out of the predetermined frequency range. The charge pump circuit 2 is controlled so as to be within a predetermined frequency range, and the oscillation clock CL1 is always held within the predetermined frequency range. The operation time from t2 to t3) can be reduced.

The configuration of the present invention is not limited to the configuration example described in the above embodiment.

[0023]

As described above, according to the present invention, the frequency of the oscillation clock of the PLL is constantly monitored, and when the frequency is deviated from a certain range, the frequency is always maintained within the range. In addition, the input voltage of the voltage-controlled oscillator that outputs the oscillation clock can be controlled.

Therefore, the frequency of the oscillation clock of the PLL based on the reproduction signal from the disk can always be controlled within the set frequency range so as not to largely deviate from the normal reproduction state for the disk. The control time at the time of redrawing can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock extraction device according to an embodiment of the present invention.

FIG. 2 is a time chart showing a transition of a VCO oscillation frequency in the embodiment.

FIG. 3 is a block diagram showing a configuration of a general optical disk device.

FIG. 4 is a block diagram showing a configuration of a conventional clock extraction device.

FIG. 5 is a time chart showing a phase comparison operation in the phase comparison circuit in the conventional example.

FIG. 6 is a time chart showing a transition of a VCO oscillation frequency in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparison circuit 2 Charge pump circuit 3 Filter circuit 4 Voltage control type oscillator 5 Switch 5a Switch (U) 5b Switch (D) 6 Frequency monitor circuit 6a Monitor circuit (A) 6b Monitor circuit (B) 7 Control circuit 7a Control circuit (A) 7b control circuit (B)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5D044 BC02 CC04 GM14 5J106 AA04 BB03 BB04 CC01 CC21 DD17 DD32 DD43 DD44 EE08 GG15 HH01 HH08 JJ08 KK03 KK18

Claims (2)

[Claims] 1. A PLL circuit for outputting an oscillation clock from a voltage-controlled oscillator based on a reproduction signal from a disk, wherein the frequency of the oscillation clock is a desired frequency with respect to an input voltage to the voltage-controlled oscillator. If the frequency is higher than a predetermined frequency range obtained from the above, the change in the direction of increasing the frequency of the oscillation clock is stopped, and if the frequency is lower than the predetermined frequency range, the change in the direction of decreasing the frequency of the oscillation clock is stopped. Means for stopping the clock signal. 2. A reproduction signal from a disk is input, and an oscillation loop is formed by a phase comparison circuit, a charge pump circuit, a filter circuit, and a voltage-controlled oscillator, and the voltage-controlled oscillator changes the output voltage of the charge pump circuit. A PLL circuit for outputting an oscillation clock whose frequency is controlled in accordance with the frequency, and a frequency indicating whether the frequency is within a predetermined frequency range or higher or lower than the predetermined frequency range by monitoring the oscillation clock from the PLL circuit unit. A frequency monitor circuit that generates a position signal, and based on a non-detection signal of a reproduction signal from the disk and a frequency position signal from the frequency monitor circuit, when the frequency of the oscillation clock is higher than a predetermined frequency range, The drive of the charge pump circuit for increasing the frequency of the oscillation clock is turned off, and the When the frequency of the oscillation clock is lower than a predetermined frequency range, the drive of the charge pump circuit for reducing the frequency of the oscillation clock is turned off.
A clock extraction device comprising: