JP2001184495A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform image processing based on various kinds of image processing algorithms with the image processing means of an architecture suitable to each of image processing algorithms to perform high-efficiency image processing while sufficiently utilizing resources and to reduce power consumption. SOLUTION: Concerning the image processor having a programmable image processing means for converting a read image signal to a digitally converted image signal or converting digitally generated image information to an image signal, processing the digital converted image signal so as to become an image signal, which can be outputted as an obvious image, and applying image processing to the digitally converted image signal, this device is provided with an SIMD type arithmetic processing means 301, a sequential arithmetic processing means 501 and an internal clock generating part 1203 for controlling the stop of a clock signal to the image processing means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to a digital apparatus applied to an apparatus for reproducing an image on a transfer sheet by a digital image signal, and particularly to an apparatus for reading an image from a scanner and reproducing the image on the transfer sheet. The present invention relates to an image processing device that performs image processing on an image signal.

[0002]

2. Description of the Related Art Conventionally, digital copiers for processing digital image data from analog copiers have appeared, and digital copiers have not only functions as copiers, but also have the functions of copiers. There are digital multifunction peripherals that combine functions such as facsimile functions, printer functions, and scanner functions.

As an image processing apparatus used in the above-described digital multifunction peripheral, a control capable of arbitrarily setting an image processing of a read signal, an image storage in a memory, a parallel operation of a plurality of functions, and an order and number of each image processing. "Image processing apparatus" provided with means (for example, Japanese Patent Application Laid-Open No. 8-2749)
No. 86 has already been proposed, and in this image processing apparatus, various types of image processing can be executed with one image processing configuration.

[0004]

The above-described image processing apparatus can arbitrarily set the order and the number of times of image processing. Therefore, it is possible to perform optimal image processing on input image data, and to execute various image processing. The processing can be executed by one image processing configuration, but only one image processing hardware (arithmetic processing means) of one architecture such as a parallel processing type is provided. It is not possible to select a processing means.

For example, image processing by an image processing algorithm such as an FIR filter (finite impulse response filter) is suitable for arithmetic processing by parallel processing type arithmetic processing means, but is similar to an IIR filter (infinite impulse response filter). Image processing by a simple image processing algorithm is not suitable for arithmetic processing by parallel processing type arithmetic processing means, but is suitable for sequential processing type arithmetic processing means such as performing pipeline processing.

[0006] As described above, a digital multifunction peripheral that can selectively perform image processing using different types of image processing algorithms has only one image processing hardware of one architecture, and thus has a high utilization of resources. There has been a problem that efficient image processing cannot be performed.

Further, the complexity of the image processing causes an increase in the scale of an LSI implemented in the image processing apparatus. Further, a clock signal is always input to the entire image processing unit and the image processing unit is always turned on, so that power consumption is reduced. There were problems such as increase and heat generation. In particular, in recent years, attention has been paid to prevention of global warming and environmental conservation, and although energy saving of electric and electronic devices has become essential, there has been a problem that energy saving has not been achieved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and performs image processing using different types of image processing algorithms by image processing means having an architecture suitable for each image processing algorithm. It is an object of the present invention to provide an image processing apparatus capable of performing high-efficiency image processing using resources sufficiently and reducing power consumption.

[0009]

Means for Solving the Problems To solve the above-mentioned problems,
To achieve the above object, an image processing apparatus according to the present invention converts a read image signal into a digitally converted image signal or converts digitally generated image information into an image signal. In the image processing apparatus having a programmable image processing means for converting and processing the digitally converted image signal into an image signal that can be output as a visualized image, and performing image processing on the digitally converted image signal, The image processing apparatus further includes clock stop control means for controlling stop of a clock signal to the image processing means, wherein the image processing means is constituted by arithmetic processing means having two or more different architectures.

According to the first aspect of the present invention, arithmetic processing means having different architectures can be selectively used according to an image processing algorithm to be executed.
When unnecessary (not used), the clock signal to the image processing means can be stopped.

According to a second aspect of the present invention, there is provided the image processing apparatus according to the first aspect, wherein the clock stop control means stops the clock signal to the arithmetic processing means and the clock processing means other than the arithmetic processing means. And the stop of the clock signal to the portion is separately controlled.

According to the second aspect of the present invention, the stop of the clock signal to the arithmetic processing means and the stop of the clock signal to parts other than the arithmetic processing means can be separately controlled as necessary. .

According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect,
The clock stop control means controls the stop of the clock signal separately for each of the arithmetic processing means.

According to the third aspect of the present invention, the stop of the clock signal can be controlled separately for each arithmetic processing means as needed.

According to a fourth aspect of the present invention, in the image processing apparatus according to the first, second or third aspect, the clock stop control means stops or oscillates a clock signal at a preset timing. It is characterized by the following.

According to the fourth aspect of the present invention, the clock signal can be stopped or oscillated at a preset timing even during processing (such as one-line processing).

According to a fifth aspect of the present invention, in the image processing apparatus according to the first, second or third aspect, the clock stop control means is separately provided for each of the arithmetic processing means at a preset timing. The clock signal is stopped or oscillated.

According to the fifth aspect of the present invention, the clock signal can be stopped or oscillated separately for each arithmetic processing means at a preset timing even during processing (such as one-line processing).

According to a sixth aspect of the present invention, in the image processing apparatus according to any one of the first to fifth aspects, the arithmetic processing means is configured to simultaneously perform processing on a plurality of pixel data. SIMD (Single) that performs the same operation
Instruction Multiple Data
It is characterized by having a stream type arithmetic processing means and a sequential type arithmetic processing means for performing an operation in units of one pixel.

According to the sixth aspect of the present invention, the SIMD type arithmetic processing means and the sequential type arithmetic processing means can be selectively used depending on the image processing algorithm to be executed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an image processing apparatus according to the present invention will be described below in detail with reference to the accompanying drawings.

First, the principle of the image processing apparatus according to the present embodiment will be described. FIG. 1 is a block diagram functionally showing the configuration of the image processing apparatus according to the embodiment of the present invention. In FIG. 1, the image processing apparatus has a configuration including the following five units.

The above five units include an image data control unit 100, an image reading unit 101 for reading image data, and an image memory control unit 102 for controlling an image memory for storing images and writing / reading image data. And an image processing unit 103 that performs image processing such as processing and editing on the image data, and an image writing unit 104 that writes the image data on transfer paper or the like.

Each of the above-mentioned units includes an image data control unit 100, an image reading unit 101, an image memory control unit 102, and an image processing unit 103.
And the image writing unit 104 are connected to the image data control unit 100, respectively.

(Image Data Control Unit 100) The processing performed by the image data control unit 100 is as follows.

For example, (1) data compression processing (primary compression) for improving data bus transfer efficiency, (2)
Transfer processing of primary compressed data to image data, (3) image synthesis processing (image data from a plurality of units can be synthesized, and also includes synthesis on a data bus), (4) image Shift processing (shifting of the image in the main scanning and sub-scanning directions), (5) image area expansion processing (the image area can be enlarged by an arbitrary amount to the periphery), and (6) image scaling processing (for example, 50% Or fixed magnification of 200%), (7) parallel bus interface processing,
(8) Serial bus interface processing (interface with process controller 211 described later), (9) format conversion processing of parallel data and serial data, (10) interface processing with image reading unit 101, (11) image processing Unit 10
3 and the like.

(Image Reading Unit 101) The processing performed by the image reading unit 101 is as follows.

For example, (1) read processing of reflected light of an original by an optical system, (2) CCD (Charge Cou)
(3) digitization processing with an A / D converter, (4) shading correction processing (processing for correcting unevenness in illuminance distribution of a light source), (5) ) Scanner γ correction processing (processing for correcting the density characteristics of the reading system), and the like.

(Image memory control unit 102) The processing performed by the image memory control unit 102 includes the following.

For example, (1) interface control processing with a system controller, (2) parallel bus control processing (interface control processing with a parallel bus), (3) network control processing, (4) serial bus control processing (a plurality of processes) External serial port control processing),
(5) Internal bus interface control processing (command control processing with the operation unit), (6) Local bus control processing (ROM and R for starting the system controller)
AM, font data access control processing), (7) memory module operation control processing (memory module write / read control processing, etc.), and (8) memory module access control processing (from a plurality of units). Arbitration of memory access requests), (9) data compression / expansion processing (processing to reduce the amount of data for effective use of memory), (10)
Image editing processing (clearing data in a memory area, rotating image data, synthesizing an image on a memory, and the like).

(Image processing unit 103) The processing performed by the image processing unit 103 is as follows.

For example, (1) shading correction processing (processing for correcting unevenness in illuminance distribution of a light source), (2) scanner γ correction processing (processing for correcting density characteristics of a reading system), (3) MTF correction processing, 4) smoothing, (5)
Arbitrary magnification processing in the main scanning direction, (6) density conversion (γ conversion processing: corresponding to density notch), (7) simple multi-value processing,
(8) Simple binarization processing, (9) Error diffusion processing, (10)
Dither processing, (11) dot arrangement phase control processing (rightward dot, leftward dot), (12) isolated point removal processing,
(13) Image area separation processing (color determination, attribute determination, adaptive processing), (14) density conversion processing, and the like.

(Image Writing Unit 104) The processing performed by the image writing unit 104 includes the following.

For example, (1) edge smoothing processing (jaggy correction processing), (2) correction processing for dot rearrangement,
(3) image signal pulse control processing, (4) parallel data and serial data format conversion processing, and the like.

(Hardware Configuration of Digital MFP)
Next, a hardware configuration when the image processing apparatus according to the present embodiment forms a digital multifunction peripheral will be described. FIG. 2 is a block diagram illustrating an example of a hardware configuration of the image processing apparatus according to the present embodiment.

In the block diagram of FIG. 2, the image processing apparatus according to the present embodiment includes a reading unit 201, a sensor board unit 202, and an image data control unit 2.
03, an image processor (image processing means) 204
, A video data control unit 205, and an image forming unit (engine) 206. Further, the image processing apparatus according to the present embodiment includes a process controller 211, a RAM 212,
M213.

The image processing apparatus according to the present embodiment includes an image memory access control unit 221 and a facsimile control unit 224 via a parallel bus 220.
And an image memory access control unit 22
1, a memory module 222, a system controller 231, a RAM 232, and a ROM
233 and an operation panel 234.

Here, the relationship between each of the above components and each of the units 100 to 104 shown in FIG. 1 will be described. That is, the reading unit 201 and the sensor board
The function of the image reading unit 101 shown in FIG. 1 is realized by the unit 202. Similarly, the function of the image data control unit 100 is realized by the image data control unit 203. Similarly, the image processor 204
Realizes the function of the image processing unit 103.

Similarly, the video / data control unit 205
The image writing unit 104 is realized by the image forming unit (engine) 206. Similarly, the image memory access control unit 221 and the memory module 2
The image memory control unit 102 is realized by 22.

Next, the contents of each component will be described. The reading unit 201 that optically reads a document includes a lamp, a mirror, and a lens, and condenses the reflected light of the lamp irradiation on the document to a light receiving element by the mirror and the lens.

A light receiving element, for example, a CCD is a sensor
The image data that is mounted on the board unit 202 and converted into an electric signal by the CCD is converted into a digital signal and then output (transmitted) from the sensor board unit 202.

The image data output (transmitted) from the sensor board unit 202 is transmitted to an image data control unit 203.
Is input (received). Functional device (processing unit)
The transmission of image data between the data buses is controlled entirely by the image data control unit 203.

An image data control unit (image data interface control unit) 203 performs image data transfer between the sensor board unit 202, the parallel bus 220, and the image processing processor 204,
Communication is performed between the controller 211 and the system controller 231 that controls the entire image processing apparatus. The RAM 212 stores the process controller 2
The ROM 213 stores a boot program of the process controller 211 and the like.

The image processing processor 204 is a programmable arithmetic processing means for performing image processing. The image data output (transmitted) from the sensor board unit 202 is transferred (transmitted) to the image processor 204 via the image data control unit 203, and the image processor 204 converts the image data into an optical system and a digital signal. The signal deterioration due to the quantization (referred to as signal deterioration of the scanner system) is corrected and output (transmitted) to the image data control unit 203 again.

The image memory access control unit 221 comprises:
It controls writing / reading of image data to / from the memory module 222. The system controller 231 controls the operation of each component connected to the parallel bus 220. The RAM 232 is used as a work area of the system controller 231,
M233 stores a boot program of the system controller 231 and the like.

The operation panel 234 inputs a process to be performed by the image processing apparatus. For example, the type of process (copying, facsimile transmission, image reading, printing, etc.), the number of processes, and the like are input. Thereby, the input of the image data control information can be performed. The details of the facsimile control unit 224 will be described later.

The processing of the image data read by the reading unit 201 includes a job for storing the read image data in the memory module 222 for reuse and a job for not storing the read image data in the memory module 222. explain.

As an example of storing the read image data in the memory module 222, there is a case where a plurality of sheets are copied for one document. In this case, the reading unit 201 is operated only once and the reading unit 201 is operated. Image data read by the memory module 222
And the image data stored in the memory module 222 is read out a plurality of times.

As an example in which the memory module 222 is not used, there is a case where only one original is copied.
In this case, since the read image data may be reproduced as it is, there is no need to access the memory module 222 by the image memory access control unit 221.

When the memory module 222 is not used, the data transferred from the image processor 204 to the image data controller 203 is returned from the image data controller 203 to the image processor 204 again. The image processor 204 performs image quality processing for converting luminance data by the CCD in the sensor board unit 202 into area gradation.

The image data after the image quality processing is transferred from the image processing processor 204 to the video data control unit 205. The video data control unit 205 performs post-processing related to the dot arrangement and pulse control for reproducing the dots on the signal changed to the area gradation. afterwards,
The image data is sent to the image forming unit 206, and the image forming unit 206 forms a reproduced image on transfer paper.

Next, a description will be given of the flow of image data when the image data is stored in the memory module 222 and additional processing such as image direction rotation and image synthesis is performed at the time of image reading. The image data transferred from the image processor 204 to the image data control unit 203 is
The image data is transmitted from the image data control unit 203 to the image memory access control unit 221 via the parallel bus 220.

Here, the system controller 23
1, control of access to image data and the memory module 222, expansion of print data of the external PC (personal computer) 223, and compression / expansion of image data for effective use of the memory module 222. Do it.

The image data sent to the image memory access control unit 221 is stored in the memory module 222 after data compression, and the stored image data is read as needed. The read image data is decompressed, returned to the original image data, and returned from the image memory access control unit 221 to the image data control unit 203 via the parallel bus 220.

After the image data is transferred from the image data control unit 203 to the image processor 204, image quality processing and video / video processing are performed.
The data control unit 205 performs pulse control, and the image forming unit 206 forms a reproduced image on transfer paper.
In the flow of image data, the functions of the digital multi-function peripheral are realized by the bus control by the parallel bus 220 and the image data control unit 203.

The facsimile transmission is performed by subjecting the read image data to image processing by the image processor 204 and transferring it to the facsimile control unit 224 via the image data control unit 203 and the parallel bus 220. Facsimile control unit 224
Performs data conversion to a communication network, and transmits it to a public line (PN) 225 as facsimile data.

Facsimile reception is performed on a public line (PN) 2
Facsimile control unit 22
The image data is converted into image data at 4 and transferred to the image processor 204 via the parallel bus 220 and the image data control unit 203. In this case, no special image quality processing is performed, the dot rearrangement and the pulse control are performed in the video data control unit 205, and the reproduced image is formed on the transfer paper in the image forming unit 206.

In a situation where a plurality of jobs, for example, a copy function, a facsimile transmission / reception function, and a printer output function operate in parallel, the assignment of the right to use the reading unit 201, the imaging unit 206, and the parallel bus 220 to the job is performed by the system Control is performed by the controller 231 and the process controller 211.

The process controller 211 controls the flow of image data, and the system controller 231
Controls the entire system and manages the activation of each resource. The function selection of the digital multi-function peripheral is performed on an operation panel (operation unit) 234, and processing contents such as a copy function and a facsimile function are set by a selection input on the operation panel (operation unit) 234.

The system controller 231 and the process controller 211 communicate with each other via the parallel bus 220, the image data control unit 203, and the serial bus 210. Specifically, communication between the system controller 231 and the process controller 211 is performed by performing data format conversion for the data interface between the parallel bus 220 and the serial bus 210 in the image data control unit 203.

(Image Processor 204)
The arithmetic processing means constituting the image processing processor 204 will be described. The image processing processor 204 shown in FIG.
SIMD type arithmetic processing means (SIM
D-type processor) 301, sequential processing type arithmetic processing means 401 as shown in FIG. 4, and sequential processing type arithmetic processing means 50 having a pipeline configuration as shown in FIG.
One.

FIG. 3 shows the basic structure of the SIMD type arithmetic processing means 301. The SIMD type arithmetic processing means 301 includes n ALUs (arithmetic logical operation units) 302 connected in parallel to the register file 303. Have. The ALU 302 is a unit that inputs two pixel data and performs addition, subtraction, multiplication, division, logical operation, and the like, and n ALUs 302 simultaneously perform the same operation with one instruction. The operation result is written back to the register file 303. The register file 303 is composed of m sets of n registers as one set.

FIG. 4 shows the basic configuration of the sequential processing type arithmetic processing means 401.
Is composed of one ALU 402 and a register file 403 with p registers. As shown in FIG. 5, the sequential processing type arithmetic processing means 501 having a pipeline configuration includes a register file 503 including one ALU 502 and p registers between a data input unit 504 and a data output unit 505. And a plurality of pairs in parallel with each other.

Next, taking a digital filter as an example, S
The IMD type arithmetic processing means 301 will be described. FIG. 6 shows the characteristics of the FIR filter. In the case of an FIR filter with three taps in the main scanning direction and one tap in the sub-scanning direction,
The calculation according to equation (1) is performed.

ODn = K1 · IDn + K2 · IDn−1 + K3 · IDn−2 (1) ODn: calculated density of the nth pixel in the main scanning direction IDn: input image density of the nth pixel in the main scanning direction K1 to K3: coefficients ( K1 + K2 + K3 = 1)

FIG. 7 is a diagram showing the arithmetic expression (1) of the above-mentioned FIR filter. In the FIR filter, input data IDn is multiplied by K1, data IDn−1 delayed by one pixel is multiplied by K2, and data IDn delayed by two pixels
-2 is multiplied by K3, and their sum becomes ODn. Normal,
Since these calculations are performed for each pixel, it takes a calculation time corresponding to the number of pixels. In the case of a hardware configuration, parameters such as K1, K2, and K3 are fixed.

FI by SIMD type arithmetic processing means 301
The calculation procedure of the R filter will be described. Here,
Since the purpose is to show the operation procedure and explain the operation of the SIMD type processor 301, the handling of floating point and the like will not be described in detail. Here, ALU 302
The operation of the SIMD type arithmetic processing means 301 having seven parallel registers and the register file 303 having three sets of seven parallel registers will be described.

(Procedure 1) Di · K1 is calculated, and the calculation result is stored in a register REG1i. That is, in procedure 1, Di · K is used for all the input data D1 to D7.
1 is performed, and each operation result is stored in the register REG1.

(Procedure 2) Di · K2 is calculated, and the calculation result is stored in a register REG2i. That is, Di × K2 is performed for all the input data D1 to D7, and each calculation result is stored in the register REG2.

(Procedure 3) REG1i + REG2 (i +
1) is calculated, and the calculation result is stored in the register RREG3i. That is, REG1 and REG2 are added.
REG2 adds the (i + 1) -th pixel to the i-th pixel of interest.

(Procedure 4) Di · K3 is calculated, and the calculation result is stored in the register REG1i. That is, Di · K3 is performed for all of the input data D1 to D7, and each calculation result is stored in the register REG1.

(Procedure 5) REG3i + REG1 (i +
2) is calculated, and the calculation result is stored in REG2i. That is, REG3 and REG1 are added. REG1 adds the (i + 2) th pixel to the ith pixel of interest. Above,
The calculation result of seven pixels is stored in REG2i.

(Procedure 6) Output data is generated by rounding the calculation result of REG2i below the decimal point.

K1 = 0.25, K2 = 0.50, K3 =
FIG. 8 shows a calculation example of the FIR filter when 0.25 is set.
Is shown in Note that OD6 and OD7 are undefined because O
Normally, it is clamped to 0 because D8 and OD9 do not exist.

As described above, the SIMD type arithmetic processing means 3
When 01 is used, n pixels can be calculated in five steps. Note that the values of K1 to K3 are in register file 3
03 is programmable by loading data, and the coefficient can be freely selected.

As described above, the SIMD type arithmetic processing means 301 can perform extremely high-speed processing, but its performance may not be exhibited depending on the algorithm. I
One example is an IR filter, which will be described.

FIG. 9 shows the characteristics of the IIR filter. The IIR filter performs the operation of Expression (2).

ODn = (1−K) · ODn−1 + K · IDn (2) ODn: density after calculation at the nth pixel in the main scanning direction IDn: input image density at the nth pixel in the main scanning direction K: coefficient (0 < K ≦ 1)

FIG. 10 graphically shows the above-described operation formula (2) of the IIR filter. In the case of the IIR filter, the post-computation density ODn is obtained from the immediately preceding computation result ODn-1 in the main scanning direction and the current data IDn. In the case of such an algorithm, S which performs the operation at once in the main scanning direction is used.
The advantage of the IMD type arithmetic processing means cannot be utilized. This is because the calculation is performed for each pixel and is used for the next calculation. In the past, this part had to be made with hardwire logic.

In the image processing apparatus according to the present invention, the IIR
The operation of the filter is one A as shown in FIG.
This is performed by the sequential operation processing means 401 based on the LU configuration, and the coefficient can be changed. In this case, the calculation can be performed by the following procedure.

Di in register 1 and K in register 2
To load. Di · K is calculated and stored in the register 3. Load register 1 with (1-K). Operate register 0 and register 1 and store the result in register 2. Operate register 2 + register 3 and store the result in register 0. The result of the register 0 is output to Oi. Enter new data Di + 1.

Here, the value of K can be easily changed by changing the value to be loaded into the register file 403, and IIR filters having various characteristics can be realized.

By using the arithmetic processing means of the above two architectures, processing suitable for the image processing algorithm is performed in a programmable manner.

In the example of the above-mentioned IIR filter in the sequential operation processing means 401, five steps are required for the operation, which means that it takes five steps to obtain the operation result of one pixel. In this case, 5 · n steps are required when calculating n pixels.

On the other hand, as shown in FIG.
The sequential arithmetic processing means 501 has a plurality of ALUs 502 and performs pipeline processing, so that the IIR filter operation can be speeded up.

As shown in FIG. 11, the pipeline processing is a means for increasing the processing speed by parallelizing the processing procedure for each fixed pixel. In this example, one processing is performed for every five pixels. I have to. In the example of the operation of the IIR filter, the processing using the arithmetic unit is, therefore, three arithmetic units are required. 1 by adopting pipeline processing
IIR filter processing, which required five steps for pixel processing, is output for each pixel, and high-speed processing can be realized. The basic functions and the basic speed-up means of the programmable arithmetic processing means have been described above.

Next, the configuration and operation of the image processor 204 will be described. Here, it is assumed that an image processing algorithm that can be calculated by the SIMD type processing unit 301 such as an FIR filter is assumed to be SIMD.
An image processing algorithm that can be operated by the sequential operation processing means 401 and 501, such as a direction algorithm (SIMD image processing) and an IIR filter, is called a sequential direction algorithm (sequential type image processing).

For example, image processing is connected in series, and the image processor 204
1 and the sequential processing unit 501 may be provided in series. This configuration is particularly effective when high-speed processing is not required or when image processing is to be performed sequentially. Since only data is passed between each image processing, no special processing is required.

Further, the image processing is performed in parallel in the SIMD operation direction and the sequential operation direction, and the image processing processor 204 has the SIMD operation processing means 301 and the sequential operation operation processing means 501 in parallel with each other. , SIMD
Type arithmetic processing means 301 and sequential processing type arithmetic processing means 501
A selector may be provided on the output side of. This configuration is effective when image processing for sequential calculation is not always necessary.

Further, the image processor 204 is
MD type arithmetic processing means 301 and sequential type arithmetic processing means 5
01 in parallel with each other, and
01 may be used by the SIMD type arithmetic processing means 301. This configuration is effective, for example, when performing image processing such as background removal. Since the IIR filter can perform strong smoothing with a smaller number of operations than the FIR filter, it is suitable for background removal and the like. Therefore, a sequential operation processing means is required.

Further, the image processor 204 is
MD type arithmetic processing means 301 and sequential type arithmetic processing means 5
It is also possible to have a plurality of sets of the 01 parallel configuration before and after.
This configuration is based on IIR such as background removal function and error diffusion processing.
This is effective when a filter is used at two or more locations.

FIG. 12 is a block diagram showing a configuration example of the image processor 204 of the image processing apparatus according to the present embodiment. The image processor 204 includes, for example, a SIMD type arithmetic processing unit 301, a sequential type arithmetic processing unit 501, and a plurality of data input / output buses (DI1,
DI2) a bus switch 1201 for controlling connection of 1207 and 1208, and a memory unit 1 having a memory controller, a memory, and a memory switch
202, an internal clock generator 1203 that receives a clock signal from a reference clock generator 1205 external to the image processor 204 and generates a clock signal used inside the image processor 204, and controls a CPU 1206 external to the image processor 204. Outputs a control signal to each part of the image processing processor 204 according to
U interface 1204.

The memory unit 1202 includes a plurality of memories (RAM) for the SIMD type arithmetic processing unit 301;
A plurality of memory controllers for controlling the memory and a memory switch for controlling connection of the plurality of memories are provided between the memory and the bus switch 1201 and the SIMD type arithmetic processing means 301. .

Data input / output buses 1207, 1208
Can operate separately. Data is bus
Input through the switch 1201 and the
2 is stored in the memory in the memory unit 1202 under the control of the memory controller. The data in this memory is SIMD under the control of the memory controller
The data is transferred to the register file 303 of the type arithmetic processing means 301 and processed by the SIMD type arithmetic processing means 301.

In this example, the sequential arithmetic processing means 501 processes the data processed by the SIMD arithmetic processing means 301 and writes it back to the register file 303 of the SIMD arithmetic processing means 301. The memory controller of the memory unit 1202 retrieves the data written back to the register file 303 by the sequential processing unit 501, stores the data in the memory inside the memory unit 1202, and inputs the data from the memory via the bus switch 1201. Output to the output bus 1207 or 1208. The above processing is performed for image data, usually for one page.
After that, it is in a standby state until the next page.

Here, the image processor 204 operates based on a fixed clock. In this example,
Reference clock generator 1205 for generating a clock signal
Is provided outside the image processing processor 204, and the image processing processor 204 receives the clock signal from the reference clock generation unit 1205 and uses the clock signal as the reference clock 1211.

The internal clock generation unit 1203 uses the reference clock 1211 to
A clock signal 1212 used internally is generated.
Each unit of the image processor 204 operates each function based on the clock signal 1212.

Generally, in an image processing apparatus, a standby time is longer than an operation time. During this waiting time,
When the clock signal 1212 is input, the memory unit 12
02, the SIMD type arithmetic processing means 301, the sequential type arithmetic processing means 501, etc., consume power unnecessarily. In order to prevent this, the clock stop signal 121 from the CPU interface is controlled by the CPU 1206 during the standby time.
3 is output.

The internal clock generation unit 1203 receives the clock stop signal 121 from the CPU interface 1204.
3 and stops the clock signal 1212 to the memory unit 1202, the SIMD type arithmetic processing unit 301, the sequential type arithmetic processing unit 501, and the like.

FIG. 13 is a block diagram showing an example of the configuration of internal clock generation section 1203 shown in FIG. The internal clock generation unit 1203 outputs, for example, the reference clock 1
Frequency dividing circuit 1301 for dividing frequency of 211 and outputting the divided frequency;
Clock stop signal 12 from interface 1204
13 and a stop control circuit 1302 for controlling the stop of the clock signal 1212 in accordance with the input clock stop signal 1213.

The frequency dividing circuit 1301 has a reference clock 1211
Is divided and output to the stop control circuit 1302. The stop control circuit 1302 receives the frequency divider circuit output 1303 from the frequency divider circuit 1301 and the clock stop signal 1213 from the CPU interface 1204, and controls the stop of the clock signal 1212 according to the clock stop signal 1213.

FIG. 14 shows the stop control circuit 1 shown in FIG.
FIG. 3 is a block diagram illustrating an example of a configuration of the image forming apparatus. The stop control circuit 1302 receives, for example, a frequency divider circuit output 1303 and a clock stop signal 1213 and
It is composed of an AND gate 1401 that outputs 2.
The AND gate 1401 receives the input clock stop signal 1
When 213 is “0 (low level)”, “0 (low level)” is output. On the other hand, the input clock stop signal 1
When 213 is “1 (high level)”, the frequency divider 130
1 from the frequency divider circuit output 1303 and the clock signal 1212
Output as

In the above configuration, the operation of the image processor 204 will be described with reference to a timing chart. FIG. 15 is a timing chart illustrating the operation of the frequency dividing circuit 1301 of the image processing apparatus according to the present embodiment. The frequency dividing circuit 1301 receives the reference clock 1211, divides the input reference clock, and outputs the divided frequency. The figure shows an example in which the frequency dividing circuit 1301 performs 1/2 frequency division.

FIG. 16 is a timing chart showing the operation of the image processor 204 of the image processing apparatus according to the present embodiment. The image processing processor 204
When the clock stop signal 1213 is “0” and the clock signal 12
The processing is stopped while 12 is stopped. After the clock stop signal 1213 becomes “1” and the oscillation of the clock signal 1212 is started, one-line processing is started. As described above, the clock signal to each unit of the image processor 204 is stopped during the standby, so that the power consumption during the standby can be reduced.

Next, an example in which the stop control of the clock signal is separately performed for each unit will be described. That is, S
IMD type arithmetic processing means 301, sequential type arithmetic processing means 50
1 and a control unit other than the arithmetic processing means (the memory unit 1202 and the bus switch 1201) is separately controlled to stop the clock signal. For example, when only the data input / output operation is performed, only the clock signal to the arithmetic means (SIMD arithmetic processing means 301 and sequential arithmetic processing means 501) is used, and when there is no IIR filter processing in the image processing, the sequential arithmetic processing means 501 is used. , Only the clock signal corresponding to the clock is stopped.

FIG. 17 is a block diagram showing another configuration example of the image processor 204 of the image processing apparatus according to the present embodiment. The same parts as those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted. This image processor 204 has the configuration shown in FIG.
Clock control signals 1705 and 1706 for the SIMD type arithmetic processing unit 301 and the sequential type arithmetic processing unit 501 are input from the CPU interface 1204, and the SIMD type arithmetic processing unit 301 and the sequential type arithmetic operation are performed in accordance with the input clock control signals 1705 and 1706. A clock stop control unit 1702 that separately controls the stop of the clock signals 1703 and 1704 to the processing unit 501 is provided.

The internal clock generation unit 1701
IMD type arithmetic processing means 301, sequential type arithmetic processing means 50
No stop control of the clock signals 1703 and 1704 to 1 is performed, and the frequency divider circuit output 1303 is output to the clock stop controller 1702 as it is. Internal clock generator 17
01 is, for example, as shown in FIG.
01 from the stop control circuit 1302
The configuration is such that 303 is taken out and output to the clock stop control unit 1702.

The clock signal 1212 from the stop control circuit 1302 is supplied to the bus switch 1201,
02, the SIMD type arithmetic processing means 301,
It is not output to the sequential operation processing means 501. That is, the clock signal 1212 to the bus switch 1201 and the memory unit 1202 can be stopped independently of the clock signals 1703 and 1704 to the arithmetic processing means. The clock signal to the bus switch 1201 and the clock signal to the memory unit 1202 may be separately controlled to stop.

FIG. 19 is a block diagram showing a configuration example of the clock stop control section 1702 shown in FIG. The clock stop control unit 1702 includes, for example, a clock control signal 1705 for the SIMD type arithmetic processing unit 301.
And a frequency divider circuit output 1303, and outputs the SIMD type arithmetic processing means 30 according to the clock control signal 1705.
AND gate 1 that outputs clock signal 1703 for 1
AND gate 1901 that inputs clock control signal 1706 for serial operation processing means 501 and frequency divider circuit output 1303 and outputs clock signal 1704 for sequential operation processing means 501 in response to clock control signal 1706 And

The AND gates 1901 and 1902 output “0” when the clock control signals 1705 and 1706 are “0”, and output 13 when the clock control signals 1705 and 1706 are “1”.
03 is output as clock signals 1703 and 1704. In this way, the stop control of the clock signal is performed separately for each unit.

In the above configuration, the operation of the image processor 204 will be described with reference to a timing chart. FIG. 20 shows the image processor 2
12 is a timing chart showing the operation of the embodiment 04. CPU1
206 controls the clock stop signal 1213 and the clock control signals 1705 and 1706 in accordance with the processing performed by the image processor 204. In the figure, the clock control signal 1705 for the SIMD type arithmetic processing means 301 is "1",
The case where the clock control signal 1706 for 01 is “0” is shown.

In this case, the SIMD type arithmetic processing means 301
Clock signal 1703 is output, but the clock signal 1704 for the clock for the sequential arithmetic processing means 501 is stopped. Thereby, the SIMD type arithmetic processing means 30
In step 1, the image processing is performed, and the operation of the sequential arithmetic processing unit 501 stops. As described above, the stop control of the clock signal is carefully performed for each unit as needed, so that the power consumption can be further reduced.

Next, an example in which the arithmetic processing means is stopped at a predetermined timing set in advance will be described.
Thus, when all the calculation means are used within one page in the image processing, unnecessary calculation processing means can be stopped even during the image processing. FIG.
FIG. 11 is a block diagram illustrating another configuration example of the image processor 204 of the image processing apparatus according to the present embodiment. Note that the same portions as those in FIG. 17 are denoted by the same reference numerals, and description thereof will be omitted.

In the image processor 204, the memory unit 2101 outputs a clock control signal 2105 indicating the head of the line of the image data. Further, the CPU interface 1204 is provided with clock control signals 2103 and 2104 each representing a value preset in accordance with the timing at which the processing in the SIMD type arithmetic processing means 301 and the sequential type arithmetic processing means 501 ends.
Is output.

The clock stop control section 2102 outputs these clock control signals 2103, 2104, 210
5 and the frequency divider circuit output 1303 from the internal clock generator 1701
In accordance with 3, 2104 and 2105, stop control of the clock signals 1703 and 1704 to the SIMD type arithmetic processing means 301 and the sequential type arithmetic processing means 501 is separately performed. The stop and oscillation of the clock signals 1703 and 1704 are also performed during the processing of one line.

FIG. 22 is a block diagram showing an example of the configuration of clock stop control section 2102 shown in FIG. The clock stop control unit 2102 outputs, for example, the frequency divider circuit output 1
A counter 2201 that counts 303 and is reset at the beginning of a line of image data by a clock control signal (pulse) 2105 from the memory unit 2101
It has.

An output signal (counter output) 2211 from the counter 2201 and a clock control signal 2103 for the SIMD type arithmetic processing means 301 from the CPU interface 1204 are input. When these signals match, a clock stop trigger signal is output. (Pulse) 2212 to output a comparator 2202 and a counter 2201 output signal (counter output) 2
And a comparator 2203 that inputs a clock control signal 2104 for the sequential processing unit 501 from the CPU 211 and the CPU interface 1204 and outputs a clock stop trigger signal (pulse) 2213 when these signals match. I have.

A flip-flop (FF) 2204 which is set at the head of the image data line by the clock control signal 2105 from the memory unit 2101 and is reset by the clock stop trigger signal 2212 from the comparator 2202;
1 is set at the head of the image data line by the clock control signal 2105 from
A flip-flop (FF) 2205 reset by a clock stop trigger signal 2213 from the CPU 203;
It has.

An output signal (clock output enable signal) 2214 of the flip-flop 2204 and a frequency divider circuit output 1303 are input. When the clock output enable signal 2214 is "1", the clock signal 1703 for the SIMD type arithmetic processing means is output. An AND gate 2206 is provided to oscillate and stop the SIMD type arithmetic processing means clock signal 1703 when the clock output enable signal 2214 is “0”.

The output signal (clock output enable signal) 2215 of the flip-flop 2205 and the frequency divider circuit output 1303 are input. When the clock output enable signal 2215 is “1”, the clock signal 1704 for the sequential processing means is output. An AND gate 2207 that oscillates and stops the clock signal 1704 for the sequential processing means when the clock output enable signal 2215 is “0”.
It has.

The counter 2201 has a number of bits capable of expressing a number equal to or more than the number of clocks in one-line processing (5 bits in the case of 23 clocks) and counts the number of clocks from the beginning of one-line processing. Clock control signal 21 from CPU interface 1204
03 and 2104 are signals having the same number of bits as the number of bits of the counter 2201 and represent the number of clocks preset in the CPU interface 1204. The comparators 2202 and 2203 output the counter output 2
The value of 211 and the clock control signals 2103, 21
The value is compared with the value of "04", and if they match, the output is set to "1" (pulse is generated).

The flip-flops 2204 and 2205 are
Set at the beginning of one-line processing, comparator outputs 2212 and 2213 rise (to "1")
When reset. AND gate 2206, 2207
Indicates that the flip-flop outputs 2214 and 2215 are "1"
(When set) clock signal 170
3,1704 is oscillated, and the flip-flop output 221 is output.
When 4,2215 is "0" (when reset), the clock signals 1703 and 1704 are stopped. As described above, the clock stop control unit 2102 stops the clock signal to the arithmetic processing unit that has completed the image processing in the middle of one-line processing, and sends the clock signal to these image processing units at the beginning of the next one-line processing. Oscillate.

In the above configuration, the operation of the image processor 204 will be described with reference to a timing chart. FIG. 23 shows the image processor 2
12 is a timing chart showing the operation of the embodiment 04. For example, if the processing time of one line processing is 23 clocks,
MD type arithmetic processing means 301 has 6 clocks (image processing 1)
Assume that the processing for one line is completed at +4 clocks (image processing 2) +9 clocks (image processing 3) = 19 clocks. Further, it is assumed that the sequential arithmetic processing unit 501 finishes processing in 21 clocks. A clock signal is supplied to each arithmetic processing unit only during operation.

In the operation of the image processor 204, first, a clock control signal 2105 rises from the memory unit 2101 at the timing of the head of one line of image data. Clock control signal 2
When 105 rises, the counter 2201 is reset and starts counting from 1. The flip-flops 2204 and 2205 are set, the clock output enable signals 2214 and 2215 become “1”, and the clock signals 1703 and 1704 are output.

Clock control signals 2103, 21
Numeral 04 denotes the timing when the SIMD type arithmetic processing means 301 ends the processing (19th clock from the head of the image data line), and the timing when the sequential type arithmetic processing means 501 ends the processing (two times from the head of the image data line).
(1st clock).

Clock control signals 2103, 21
When the value of “04” matches the value of the counter output 2211, that is, at the timing of the 19th clock and the 21st clock from the head of the image data line, the clock stop triggers 2212 and 2213 rise, and the clock enable signals 2214 and 2214 2215 falls. As a result, the clock signals 1703 and 1704 stop.

Thereafter, the clock control signal 2105 indicating the beginning of the next line rises again, and the above operation is repeated. As described above, unnecessary clock signals to each arithmetic processing unit are stopped even during the one-line processing, so that power consumption can be further reduced.

(Specific Configuration Example of SIMD Type Operation Processing Unit 301) FIG. 24 shows a specific configuration of the SIMD type operation processing unit 301. SIMD (Single Ins
fraction Multiple Datast
The “ream” executes a single instruction in parallel on a plurality of data, and is composed of a plurality of PEs (processor elements).

Each PE has a register (Reg) 2401 for storing data, a multiplexer (MUX) 2402 for accessing a register of another PE,
Barrel Shifter (Shift Expand) 240
3. A logical operation unit (ALU) 2404, an accumulator (A) 2405 for storing a logical result, and a temporary register (F) 2406 for temporarily saving the contents of the accumulator 2405.

Each register 2401 is connected to an address bus and a data bus (lead line and word line), and stores an instruction code defining a process and data to be processed. The contents of the register 2401 are input to the logical operation unit 2404, and the operation processing result is stored in the accumulator 2405. In order to retrieve the result outside the PE, the result is temporarily saved in the temporary register 2406. By extracting the contents of the temporary register 2406, a processing result for the target data is obtained.

The instruction code is given to each PE with the same contents.
The data to be processed is given in a different state for each PE, and the contents of the register 2401 of the adjacent PE are stored in the multiplexer 2.
By referring to 402, the calculation result is processed in parallel and output to each accumulator 2405.

For example, if the contents of one line of image data are arranged in the PE for each pixel and arithmetic processing is performed with the same instruction code, the processing result for one line can be processed in a shorter time than in the case of sequentially processing one pixel at a time. can get. In particular, the spatial filter processing and the shading correction processing can be performed in common for all PEs, with the instruction code for each PE being the operation expression itself.

As described above, according to the present embodiment, the arithmetic processing means having different architectures can be used for the SIMD arithmetic processing means 301 and the sequential arithmetic processing means 401 depending on the image processing algorithm to be executed.

Further, by using the sequential processing means 501 for performing the pipeline processing, the sequential processing can be performed at a high speed. Further, since the SIMD arithmetic processing means 301 and the sequential arithmetic processing means 401 and 501 operate in parallel, the optimal architecture can be selected according to the image processing algorithm to perform the arithmetic operation at high speed.

In the case of image processing by the SIMD type arithmetic processing means 301, processing results are exchanged between the SIMD type arithmetic processing means 301 and the sequential type arithmetic processing means 401 and 501, and complex image processing Can be performed at high speed. As described above, it is possible to perform high-efficiency image processing that makes full use of resources regardless of the image processing algorithm.

In addition, when unnecessary, such as during standby, the clock signal to each unit of the image processor 204 is stopped, so that power consumption can be reduced. Further, by controlling the stop of the clock signal independently of each part of the image processor 204, the power consumption can be further reduced. Further, even during the one-line processing, the power consumption can be further reduced by stopping the clock signal to the arithmetic processing unit that has completed the processing.

[0137]

As will be understood from the above description, according to the first aspect of the present invention, it is possible to selectively use arithmetic processing means having different architectures according to the image processing algorithm to be executed, and it is unnecessary. When (not used), the clock signal to the image processing means can be stopped, thereby performing high-efficiency image processing using resources irrespective of the image processing algorithm and power consumption. And an image processing apparatus that can reduce the image quality is obtained.

According to the second aspect of the present invention, the stop of the clock signal to the arithmetic processing means and the stop of the clock signal to parts other than the arithmetic processing means can be separately controlled as necessary. Thus, an effect is obtained that an image processing apparatus that can operate only necessary functions at the time of data input / output and can further reduce power consumption can be obtained.

Further, according to the third aspect of the present invention, the stop of the clock signal can be separately controlled for each arithmetic processing means as needed, whereby the processing processing means which are not used by the processing can be controlled. Stop only the clock signal,
Further, there is an effect that an image processing apparatus capable of reducing power consumption can be obtained.

According to the fourth aspect of the present invention, the clock signal can be stopped or oscillated at a preset timing even during the processing (eg, one-line processing), whereby the clock signal can be generated during the image processing. An effect is obtained that an image processing apparatus capable of performing stop control of a signal and further reducing power consumption can be obtained.

According to the fifth aspect of the present invention, the clock signal can be stopped or oscillated separately for each arithmetic processing means at a preset timing even during processing (such as one-line processing). Thereby, the stop control of the clock signal can be performed even during the image processing,
Further, there is an effect that an image processing apparatus capable of reducing power consumption can be obtained.

Further, according to the present invention, the SIMD type arithmetic processing means and the sequential type arithmetic processing means can be selectively used according to the image processing algorithm to be executed, and the resources can be used regardless of the image processing algorithm. There is an effect that an image processing apparatus capable of performing high-efficiency image processing that is fully utilized and high-speed operation is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram functionally showing a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a hardware configuration of the image processing apparatus according to the embodiment;

FIG. 3 is a block diagram illustrating an example of a SIMD type arithmetic processing unit used in the image processing apparatus according to the embodiment;

FIG. 4 is a block diagram illustrating an example of a sequential processing unit used in the image processing apparatus according to the embodiment;

FIG. 5 is a block diagram illustrating an example of a sequential processing type arithmetic processing unit having a pipeline configuration used in the image processing apparatus according to the exemplary embodiment;

FIG. 6 is a graph showing characteristics of an FIR filter.

FIG. 7 is a block diagram showing a configuration of an FIR filter.

FIG. 8 is an explanatory diagram showing a calculation example of an FIR filter.

FIG. 9 is a graph showing characteristics of an IIR filter.

FIG. 10 is a block diagram illustrating a configuration of an IIR filter.

FIG. 11 is an explanatory diagram illustrating a state of pipeline processing by a sequential processing type arithmetic processing unit having a pipeline configuration used in the image processing apparatus according to the present embodiment;

FIG. 12 is a block diagram illustrating a configuration example of an image processor of the image processing apparatus according to the present embodiment.

13 is a block diagram illustrating a configuration example of an internal clock generation unit illustrated in FIG.

FIG. 14 is a block diagram illustrating a configuration example of a stop control circuit illustrated in FIG. 13;

FIG. 15 is a timing chart showing the operation of the frequency dividing circuit of the image processing apparatus according to the present embodiment.

FIG. 16 is a timing chart showing the operation of the image processor of the image processing apparatus according to the present embodiment.

FIG. 17 is a block diagram illustrating another configuration example of the image processor of the image processing apparatus according to the present embodiment;

18 is a block diagram illustrating a configuration example of an internal clock generation unit illustrated in FIG.

FIG. 19 is a block diagram illustrating a configuration example of a clock stop control unit illustrated in FIG. 17;

FIG. 20 is a timing chart showing an operation of another image processing processor of the image processing apparatus according to the present embodiment.

FIG. 21 is a block diagram illustrating another configuration example of the image processor of the image processing apparatus according to the present embodiment;

FIG. 22 is a block diagram illustrating a configuration example of a clock stop control unit illustrated in FIG. 21;

FIG. 23 is a timing chart showing the operation of another image processor of the image processing apparatus according to the present embodiment.

FIG. 24 is an explanatory diagram illustrating a schematic configuration of a SIMD type processor used in the image processing apparatus according to the present embodiment;

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Image data control unit 101 Image reading unit 102 Image memory control unit 103 Image processing unit 104 Image writing unit 201 Reading unit 202 Sensor board unit 203 Image data control unit 204 Image processing processor 205 Video data control unit 206 Image formation Unit (engine) 210 Serial bus 211 Process controller 212,232 RAM 213,233 ROM 220 Parallel bus 221 Image memory access control unit 222 Memory module 223 Personal computer (PC) 224 Facsimile control unit 225 Public line 231 System Controller 234 Operation panel 301 SIMD type arithmetic processing means 302, 402, 502 ALU 3 3,403,503 Register file 401,501 Sequential processing unit 1201 Bus switch 1202,2101 Memory unit 1203,1701 Internal clock generation unit 1204 CPU interface 1205 Reference clock generation unit 1206 CPU 1702,2102 Clock stop control unit 2401 Register (Reg) 2402 Multiplexer (MUX) 2403 Barrel shifter (Shift Expand)
d) 2404 Logical operation unit (ALU) 2405 Accumulator (A) 2406 Temporary register (F)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shinya Miyazaki 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd. (72) Inventor Hideto Miyazaki 1-3-6 Nakamagome, Ota-ku, Tokyo Ricoh Co., Ltd. (72) Inventor: Sugitaka Shikogi 1-3-6 Nakamagome, Ota-ku, Tokyo Stock Company Ricoh (72) Yasuyuki Nomizu 1-3-6, Nakamagome, Ota-ku, Tokyo Co., Ltd. Inside Ricoh (72) Inventor Rie Ishii 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72) Inventor Yoshiyuki Hatzuka 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72 ) Inventor Goji Tone 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72) Inventor Fumio Yoshizawa 1-3-6 Nakamagome, Ota-ku, Tokyo Stock Association Ricoh Co., Ltd. (72) Inventor Takusho Fukuda 1-3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Co., Ltd. 5B057 CH02 CH05 CH09 CH18 5C062 AA05 AB41 AB43 AB47 AE15 BA00 BA04

Claims (6)

[Claims] An image capable of converting a read image signal into a digitally converted image signal, or converting digitally generated image information into an image signal, and outputting the digitally converted image signal as a visualized image. An image processing apparatus having programmable image processing means for processing the image signal into a signal and performing image processing on the digitally converted image signal; clock stop control means for controlling stop of a clock signal to the image processing means The image processing apparatus according to claim 1, wherein the image processing means is configured by arithmetic processing means having two or more different architectures. 2. The method according to claim 1, wherein the clock stop control means controls the stop of the clock signal to the arithmetic processing means and the stop of the clock signal to parts other than the arithmetic processing means separately. Image processing device. 3. The image processing apparatus according to claim 1, wherein the clock stop control unit controls the stop of the clock signal separately for each of the arithmetic processing units. 4. The image processing apparatus according to claim 1, wherein said clock stop control means stops or oscillates a clock signal at a preset timing. 5. The image processing apparatus according to claim 1, wherein the clock stop control unit stops or oscillates a clock signal separately for each of the arithmetic processing units at a preset timing. 6. The SIMD (Single) which performs the same operation on a plurality of pixel data at the same time.
e Instruction Multiple Da
The image processing apparatus according to any one of claims 1 to 5, further comprising: a (stream) arithmetic processing unit; and a sequential arithmetic processing unit that performs arithmetic on a pixel-by-pixel basis.