JP2003281516A - Image processor and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To resolve a problem in carrying out a pseudorandom number process by using an SIMD type element processor wherein it is difficult to supply favorable pseudorandom numbers at high speed. <P>SOLUTION: The SIMD type processor has twenty five F/Fs 501-525 composing a linear feedback shift register, eight sets of calculating means for calculating exclusive ORs regarding four F/F outputs of the F/Fs 501-525, a feedback means for concurrently feeding back each output data from the eight sets of calculating means to eight registers, a shifting means for shifting the data held in the eight registers to registers positioned in each subsequent stage, and a random number generating means for generating a pseudorandom number of eight bits from the feedback data by the feedback means and the data shifted by the shifting means. The SIMD type processor carries out the pseudorandom number process by using the generated pseudorandom number. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method for generating pseudo random numbers.

[0002]

2. Description of the Related Art At present, a so-called MFP (MFP) configured as a multifunction machine of image processing apparatuses having different functions such as a copying machine, a facsimile machine, a printer, and a scanner.
An image processing device called an ulti function printer is known. In such an MFP, SIMD (Single Instruction stream Multiple Data
A technique for processing an image in a high-speed and programmable manner by using a stream type processor is described in, for example, Japanese Patent Laid-Open No. 8-315126.

In such an MFP, image processing using pseudo random numbers is performed. For example, when a halftone is expressed in a pseudo manner such as a pseudo halftone process, it has a frequency component that is unpleasant to the human eye, and further has a more irregular and higher frequency component in order to reduce regular texture. A process of disturbing the unpleasant texture using a pseudo random number is known. Processing using such pseudo-random numbers has been realized by simple hardware such as the random number generator shown in FIG. 5A.

[0004]

However, in the conventional MFP described above, when a large number of pixels are processed in parallel by software using a SIMD type processor, the pseudo random number is generated by the following method. A method can be considered.

A) Random number generators as shown in FIG. 5A are prepared in parallel as external hardware, and the generated pseudo random numbers are input in a raster form like an image signal.

B) A pseudo random number is generated by another CPU.

C) Each PE (processor element) forming the SIMD type processor independently generates a pseudo random number.

In a normal SIMD type processor, when inputting data from the outside, serial input using shift registers for the number of PEs is performed. In addition, high-speed processing is required because it is necessary to simultaneously generate pseudo-random numbers for the number of PEs that the SIMD type processor processes in parallel. Therefore, in the above methods a) and b), high-speed input to the SIMD processor cannot be expected.

Further, in the above method c), all PEs in the SIMD type processor operate by the same program, and therefore different random numbers cannot be generated for each PE. Therefore, in this method, since the same random number is generated when the adjacent processors process the adjacent image signals, the normal random number processing cannot be performed.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an image processing apparatus and a method therefor capable of high-speed pseudo-random number processing using a SIMD type processor.

[0011]

As one means for achieving the above object, the present invention has the following configuration.

That is, in a processor in which a plurality of processor elements operate in parallel and simultaneously according to a single program, an image processing device for performing image processing using pseudo random numbers, and a plurality of registers forming a linear feedback shift register , N sets of calculation means for calculating an exclusive OR of outputs from a predetermined number of registers, feedback means for returning each output data from the N sets of calculation means to N registers at the same time, and the N sets. Shift means for shifting the data held in the register of each to a register located at a subsequent stage, feedback data by the feedback means, and random number generating means for generating a pseudo random number from the data shifted by the shift means, And the processor performs image processing using the pseudo-random number generated by the random number generation means. And wherein the Ukoto.

For example, the random number generating means is characterized in that it simultaneously generates N-bit pseudo random numbers.

For example, the N sets of arithmetic means are characterized by performing respective arithmetic processes in parallel.

For example, the N is 8 or 16.

For example, each of the N sets of computing means is constituted by a lookup table.

For example, the register, the feedback unit, the shift unit, and the random number generation unit are implemented on a processor different from the processor.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

Basic Functional Configuration of Image Processing Apparatus First, the basic functional configuration of the image processing apparatus according to the present embodiment will be described with reference to the block diagram of FIG. According to the figure, the image processing apparatus is an image data control unit that performs main control.
Image data input unit 1 for inputting 100 and image data
01, an image memory control unit 102 that controls an image memory that stores images and writes / reads image data, an image processing unit 103 that performs image processing such as processing and editing on the image data, and image data An image writing unit 104 for writing on a transfer sheet or the like is composed of five units.

The above-mentioned units are mainly composed of the image data control unit 100. That is, the image data input unit 101, the image memory control unit 102, the image processing unit 103, and the image writing unit 104 are all connected to the image data control unit 100. Each unit will be described below.

First, the processing by the image data control unit 100 will be described below.

Control data bus interface processing, overall system control, local bus control processing (ROM, RAM for accessing system controller, access control processing), interface processing with image data input unit 101, image memory control unit 102 Interface processing with the image processing unit 103, interface processing with the image writing unit 104, network control processing, and the like.

In the image data input unit 101,
Interface control processing with the system controller,
CCD (Charge)
Coupled Device: Charged device) conversion processing to electrical signals, A / D converter digitization processing, shading correction processing (processing to correct the unevenness of the illuminance distribution of the light source), density characteristics of the reading system Correction processing, rasterization processing of PDL image data input via a network, and the like are performed.

In the image memory control unit 102,
Interface control processing with the system controller,
Write / read processing to the memory unit, access control processing to the memory module (arbitration processing of memory access requests from a plurality of units), and the like are performed.

In the image processing unit 103, color conversion processing, color correction processing, MTF correction processing, smoothing processing, arbitrary scaling processing in the main scanning direction, density conversion (γ conversion processing: corresponding to density adjustment key), simple Binarization processing, various pseudo-halftone processing, dot arrangement phase control processing (jaggy correction), image area separation processing (color determination, attribute determination, adaptive processing), density conversion processing, etc. are performed.

In the image writing unit 104, pulse control processing of image signals, format conversion processing of parallel data and serial data, etc. are performed.

Hardware Configuration of Digital Multifunction Peripheral The above-described image processing apparatus according to this embodiment constitutes a digital multifunctional peripheral. Hereinafter, an example of the hardware configuration of this digital multi-function peripheral will be described with reference to the block diagram of FIG.
According to the figure, this digital multi-function peripheral has a reading unit 20
1, PDL processing unit 202, image data control unit 203, image processing processor 204, image forming unit 205, memory control unit 20
6, a memory module 207, a network control unit 214, a working memory 216. Further, via the control data bus 208, the system controller 209, ROM 210, RA
An M211 and an operation panel 212 are provided. Also, the network 213
Via a personal computer 215.

Of the configuration shown in FIG. 2, the image processor 204 processes image data, which is a digital signal created based on an image, so that it can be output as a visible image, thereby realizing a plurality of image forming operations. It is a programmable image processing means. Further, the image data control unit 203,
Data bus and image processor for transmitting image data
An image data transmission management unit that collectively manages image data transmission between processing units used for image processing by 204, and includes a reading unit 201, a PDL processing unit 202, an image processing processor 204, a memory control unit 206, and an image forming unit. 20
5. Manages data transmission between network control units 214. The present embodiment is characterized by the processing in the image processing processor 204.
The detailed configuration of 4 will be described in detail with reference to the drawings starting from FIG.

The digital multi-function peripheral further comprises a memory module 207 connected to the image memory control unit 206 as image data storage management means.

Here, the relationship between each configuration shown in FIG. 2 and each of the units 100 to 104 shown in FIG. 1 will be described. That is, the function of the image data input unit 101 shown in FIG. 1 is realized by the reading unit 201 and the PDL processing unit 202. Similarly, the image data control unit 203, the system controller 209, the ROM 210, the RAM 211, the operation panel 212, the network control unit 214, the image data control unit 1
Realize the function of 00. Similarly, an image processor
204, image processing unit 103 by working memory 216
Realize the function of.

Similarly, the image forming unit 205 realizes the image writing unit 104, and the memory control unit 206 and the memory module 207 realize the image memory control unit 102.

The system controller 209 shown in FIG.
Operates based on the control program stored in the ROM 210 connected via the control data bus 208, and uses the RAM 211 as a work memory. Also, the reading unit 20
1, PDL processing unit 202, image data control unit 203, image processing processor unit 204, image forming unit 205, memory control unit 20
6, the operation of the network control unit 214 and the operation panel 212 are controlled by the system controller 209 via the control data bus 208.

The operation of each component shown in FIG. 2 will be described in detail below. Scanning unit 20 that optically scans documents
Reference numeral 1 is composed of a lamp, a mirror, a lens, and a light receiving element, and collects the reflected light of the illumination of the document on the light receiving element by the mirror and the lens. The image data converted into an electric signal in a light receiving element such as a CCD is converted into a digital signal and then output (transmitted) from the reading unit 201.

The PDL processing unit 202 includes a network 213.
Is a unit for rasterizing the PDL image data input from the personal computer 215 connected to the to a bitmap image. PDL image data input via the network 213 is transmitted to the PD via the network control unit 214.
When input to the L processing unit 202, the PDL processing unit 202
Performs rasterization based on the input PDL image data and outputs (transmits) bitmap image data. As described above, the reading unit 201 and the PDL processing unit
The image data output (transmitted) from 202 is input (received) to the image data control unit 203.

The image data received by the image data control unit 203 from the reading unit 201 and the PDL processing unit 202 is the image data processing processor unit 204 or the memory control unit 206.
Is output to.

First, the operation when output to the image processing processor unit 204 will be described.

The image data input to the image processing processor unit 204 is processed by the image processing processor unit 204 while using the working memory 216, and then output to the image data control unit 203 again and passed through the memory control unit 206. Stored in the memory module 207.

After the processing of the image data for one screen by the image processing processor unit 204 is completed and the processed data for one screen is stored in the memory module 207, the memory control unit 206 causes the image for the memory module 207 to be processed. Data is read and the read image data is output to the image forming unit 205 via the image data control unit 203 to obtain a print output. Alternatively, the image data read from the memory module 207 is output to the network control unit 214 via the image data control unit 203, and the network 213
It operates so as to output to the personal computer 215 via.

Next, the reading unit 201 and the PDL processing unit
Image data received by the image data control unit 203 from 202,
The operation when outputting to the memory control unit 206 will be described.

From the image data control unit 203 to the memory control unit 206
The image data input to is stored in the memory module 207. Next, the memory control unit 206 detects the memory module 207.
Then, the stored image data is read out and output to the image processing processor unit 204 via the image data control unit 203.
The image processing processor unit 204 processes the input image data and outputs the processed image data to the memory module 20 via the image data control unit 203 and the memory control unit 206 again.
Remember in 7. Then, by the image processing processor unit 204
After the processing of the image data for one screen is completed and the processed data for one screen is stored in the memory module 207, the memory control unit 206 reads the image data from the memory module 207 and reads the image data. Image data is output to the image forming unit 205 via the image data control unit 203 to obtain a print output. Alternatively, the image data read from the memory module 207 is output to the network control unit 214 via the image data control unit 203 and further output to the personal computer 215 via the network 213.

In the above, the reading units 201, P
The image processing processor unit 204 performs processing on the image data output from the DL processing unit 202, and after the processed image data for one screen is stored in the memory module 207, the processed image data is read out and created. An example of outputting to the image unit 205 or the network control unit 214 has been shown. However, the present embodiment is not limited to this example, and the memory module 2 is processed before the storage of the processed image data in the memory module 207 is completed for one screen.
It may be controlled to start reading the processed image data from 07.

It is also possible to control so that the image data is not stored in the memory module 207. Hereinafter, an operation example in this case will be described.

The image data received by the image data control unit 203 from the reading unit 201 and the PDL processing unit 202 is output to the image processing processor unit 204. The image processing processor unit 204 performs a predetermined process on the input image data and outputs it to the image data control unit 203. The image data input from the image processor 204 to the image data controller 203 is then output to the image forming unit 205 and the network controller 214.

As an example of the operation for storing one screen of processed image data in the memory module 207, there is a case where a plurality of sheets of one original is copied. in this case,
Operate the reading unit 201 only once,
Image data read by the memory module 207
The stored image data is read a plurality of times.

Further, as an operation example in which the image data is not stored in the memory module 207, there is a case where only one original is copied. In this case, the processed data corresponding to the read image data may be directly output to the image forming unit 205, and thus it is not necessary to access the memory module 207.

The overall operation of the digital multi-function peripheral is controlled by the system controller 209 based on the processing command input from the operation panel 212. From the operation panel 212, type of processing (copy, transmission, image reading,
It is possible to input the number of sheets to be processed and the like.

Image Processing Processor Configuration FIG. 3 is a block diagram showing the detailed configuration of the image processing processor 204 shown in FIG. According to the figure, the image processor 204 includes the FIFO memories 301 and 307 and the arithmetic processing unit 3
Composed of 00. Further, the arithmetic processing unit 300 has an input register 302, an output register 304, a SIMD processor 308 including a SIMD type data arithmetic processing unit 303, a control processor unit 305, and an external memory interface 306.

Here, SIMD indicates that a single instruction is executed in parallel with respect to a plurality of data, and in this embodiment, the data operation processing unit 303 is composed of 128 PEs.

The FIFO memory 301 is a first-in / first-out memory having a capacity of one line of image data (7168 pixels) input from the reading unit 201 or the PDL processing unit 202, and writing and reading are independent. Controlled by. The image data input from the data bus A of the image data control unit 203 is input to the FIFO memory 301,
128 pieces of image data are divided into 56 and input to the input register 302 configured by the number of registers equal to the number of PEs included in the data calculation processing unit 303.

The image data input to the input register 302 is output to the data calculation processing unit 303 and the external memory interface 306. The image data input to the data calculation processing unit 303 is subjected to predetermined processing there, and then output to the output register 304 and the external memory interface 306. It is also possible to output the intermediate data processed by the data calculation processing unit 303 to the external memory interface 306.

Like the input register 302, the output register 304 has the same number of registers as the number of PEs included in the data operation processing unit 303. The output image data of the output register 304 is input to the FIFO memory 307 having a capacity of one line of image data. The FIFO memory 307 is a first-in / first-out memory whose writing and reading are controlled independently. The image data signal output from the FIFO memory 307 is output to the image data control unit 203 via the data bus B.

Further, the SIMD processor 308 and the external memory interface 306 are the control data buses shown in FIG.
It is connected to the control processor unit 305 connected to 208. The control processor unit 305 is a PE of the data calculation processing unit 303.
To control the status of each PE, control the memory connected to each PE, input / output of data to and from the register, and control the external memory interface unit 306.
It controls data between the internal memory or register of the D processor 308 and the working memory 216. The control processor 3
05 and the SIMD processor 308 can independently perform different processes.

Arithmetic Processing Unit Configuration FIG. 4 is a block diagram showing a schematic configuration of the arithmetic processing unit 300 including the SIMD type processor 308 shown in FIG.

According to FIG. 4, the control processor unit 305 comprises a control processor 401, a program memory 402 storing a program for controlling the operations of the control processor and the SIMD type processor, and a data memory 403.

Reference numeral 404 denotes one PE that constitutes the SIMD type processor 308, and as described above, the SI in this embodiment is SI.
The MD processor 308 is composed of 128 PEs (PE0 to PE127).

As shown in FIG. 4, each PE has an 8-bit arithmetic unit (ALU) 405 and an 8-bit register 16
A general-purpose register 406 composed of a book, a mask register 407 for controlling whether or not the arithmetic operation of the ALU 405 is performed, a PE register 408 for storing data in the middle of arithmetic operation, an output register 4
09, input register 408, memory 4 with a capacity of 2K bytes
It is composed of 11. The ALU 405 and the PE register 408 are connected to the same constituent element between adjacent PEs, and have a configuration capable of inputting / outputting data. Also,
The output register 409 and the input register 410 are also connected to the same constituent elements between adjacent PEs, and operate as a 128-stage shift register. Note that, in FIG. 4, blocks corresponding to the input register 302 and the output register 304 shown in FIG.

The memory 411 in each PE is connected to the working memory 216 via the external memory interface 306 and the data bus C.

The ALU 405, the general-purpose register 406, the mask register 407, the PE register 408, the output register 409, the input register 410, and the memory 413 which compose the same PE have a structure capable of inputting / outputting data between arbitrary blocks. For example, data input / output from the memory 411 to the PE register 408, and external memory interface 306 from the PE register 408.
It enables data input / output to / from.

The instruction for each PE is the control processor 401.
Is supplied with the same contents via the instruction supply bus 413,
All PEs are controlled to operate according to the same instruction, but by differentiating the processing target data given to each PE, each PE performs arithmetic processing on different processing target data in parallel. Controlled. For example, if the contents of 128 pixels in one line of image data are arranged in the PE register for each pixel and the same instruction code is used to perform arithmetic processing on each PE register, it will take less time than sequentially processing pixel by pixel. , 128 pixel processing results are obtained.

Calculation result in ALU405 of each PE, and
Since the contents of the PE register 408 can be input / output between adjacent PEs, the PE register 40 of the adjacent PE is
8 and the calculation processing referring to the calculation result of ALU405 for each P
It is also possible to do it with E. In addition, each PE's memory 411
The input register 410, the output register 409, the PE register 408, the mask register 407, and the general-purpose register 406 are controlled by the control processor 4 via the memory / register access bus 414.
The control processor 401 controls the input / output of the memory and each register data.

The control processor 401 also receives the system controller 209 in FIG. 2 via the control data bus 208.
Control data can be input and output to and from. Further, the program memory 402 for controlling the operation of the control processor 401 and the data memory 403 are configured to be accessible from the system controller 209 via the control data bus 208. The program memory 402 for controlling the operation of the control processor 401 can be rewritten according to the contents of processing performed in 300.

[Principle of Random Number Generation] In order to facilitate understanding of the principle of pseudo random number generation in this embodiment, the conventional hardware configuration shown in FIG. 5A will be described as an example.

As the random number generation method, for example, as shown in the document "Modern Signal Theory" (Ikeno, Koyama, published in 1986, Institute of Electronics, Information and Communication Engineers), a maximum long-period sequence (M sequence) is generated. Linear feedback shift register (LF
SR) is known.

FIG. 5A shows a conventional random number generator based on the LFSR method.
As shown in, a 1-bit n-stage D flip-flop (hereinafter,
(Only described as F / F) 501, 502, ..., 525, and exclusive logical sum calculators 526, 527, 528 for calculating output signals from specific F / Fs
Consists of. In the example shown in FIG. 5A, a 1-bit 25-stage shift register is configured, and the 22nd-stage F / F522, the 23rd-stage F / F523, the 24th-stage F / F524, and the 25th-stage The output values from the F / F 525 are calculated using the exclusive OR calculators 526, 527, and 528, respectively, and the result is input to the F / F 501 at the first stage. Therefore, if the clock 534 is given to all the F / Fs and the data is shifted one stage at a time, one random number is generated each time the clock enters, and as a result, 2 ²⁵ -1 M-sequences with one cycle are generated. A 1-bit pseudo random number sequence is obtained as the output 529 of the F / F 525. It should be noted that the output of each F / F in this LFSR system can generate a pseudo random number from 2 ²⁵ -1 initial states except when all the states are 0.

By the way, when processing with 600DPI image A4 size, the longitudinal direction 7168 pixels, if the lateral direction is 4960 pixels, since the total number of pixels is about 1.06 × 2 ^25, 5
According to the LFSR system shown in (1), it is possible to generate a number of random numbers substantially equal to the total number of A4 size 600 DPI image signals.

Next, the principle of high-speed pseudo random number generation in this embodiment will be described with reference to FIG. 5B. The figure
5B, the same components as those in FIG. 5A are denoted by the same reference numerals.

Of the 25 stages of F / Fs shown in FIG. 5B, the output signals of the four F / Fs 522 to 525 from the latter stage are converted into three exclusive OR calculators 52.
The signal 550 calculated using 6,527,528 and returned to the F / F 501 in the first stage is as described in FIG. 5A.

Here, 2 to the first stage F / F 501 in FIG. 5A
The second feedback signal was obtained after the data of each F / F was shifted to the right by 1 bit by the input of the shift clock 534. On the other hand, in the present embodiment shown in FIG. 5B,
The second feedback signal to the first stage F / F 501 is obtained at the same time as the first feedback signal 550. That is, in FIG.
F / F521 ~ which is one step before the four F / F522 ~ 525 described in A
The output signal from the 524 is converted into three exclusive OR calculators 540, 541,
The result 551 calculated using 542 corresponds to the second feedback signal.

Similarly, the output signals of the F / Fs 520 to 523 are calculated by using the three exclusive OR calculators 543, 544 and 545, and the signal 552 to be fed back to the third is generated.

As described above, in the present embodiment, according to the configuration of FIG. 5A, a plurality of feedback signals, which are obtained for each bit by shifting the F / F data for each clock, are parallelized. Return at the same time by processing. By this, F / F
It is possible to reduce the number of transfer times and the time for calculating the feedback signal, and speed up is achieved.

According to the configuration shown in FIG. 5B, by providing eight sets of exclusive ethics and arithmetic units, eight feedback signals 5
50 to 557 are generated by parallel processing. Therefore, according to the configuration shown in FIG. 5B, it is possible to generate random numbers about eight times faster than the configuration shown in FIG. 5A.

<First Embodiment> An example in which the principle of generating pseudo-random numbers in the present embodiment described above is applied to hardware will be described below.

FIG. 6 is a block diagram showing an example of the hardware configuration of the first embodiment.

In FIG. 6, blocks 1 to 25 are respectively
It is the same 1-bit DF / F as the F / F 501 to 525 shown in FIG. 5B, but is connected to each other 8 F / Fs apart. That is,
The F / F1 is connected to the F / F9, the F / F9 is connected to the F / F17, the F / F17 is connected to the F / F25, and when the transfer clock 601 is input, eight shift operations are performed respectively. The output signals 603 of the F / Fs 18 to 25 can be used as continuous 1-bit random numbers or 8-bit random numbers.

The 11-bit output signal from the F / Fs 15 to 25 is input to the exclusive OR calculation unit 602. As described in FIG.5B, the exclusive OR operation unit 602 has eight sets of units each internally operating four consecutive F / F outputs with three exclusive OR calculators, and at the same time, 8 return signals 550
Outputs ~ 557.

Of these eight feedback signals, the most preceding signal 550 is connected to the input of F / F8 and the next feedback signal 551 is connected to the input of F / F7. Sequential F / F8
Type in ~ 1.

As described above, according to the first embodiment, the hardware configuration shown in FIG. 6 makes it possible to generate random numbers about eight times faster than the conventional random number generator shown in FIG. 5A. .

Therefore, since the pseudo random number generated by the random number generator having the configuration shown in FIG. 6 can be supplied to the SIMD processor 308, the SIMD processor 308 performs high-speed pseudo random number processing. Is possible.

The exclusive OR operation unit 602 may be implemented by the logic circuit shown in FIG. 5B, but a so-called lookup is performed using a ROM that connects the output signals of the F / Fs 15 to 25 to each address terminal. If a table is realized, eight feedback signals can be generated even faster.

<Second Embodiment> An example in which the pseudo-random number generation principle of this embodiment is realized by a different hardware configuration will be described below with reference to FIG.

In FIG. 6 described above, 25 shown in FIG. 5B is used.
Although an example in which eight 1-bit random numbers are simultaneously generated by the LFSR of a stage has been shown, the hardware configuration shown in FIG. 7 can generate 16 1-bit random numbers at the same time.

In FIG. 7, F / F1 to 25 are F / F50s shown in FIG. 5B.
It is the same 1-bit DF / F as 1-525, but each is connected to 16 F / Fs apart. That is, in FIG. 7, F / F1
To F / F17, F / F2 to F / F18, F / F3 to F / F19,
Clock 16 in Figure 5A depending on the input of transfer clock 701.
The operation corresponding to the shift for each piece is performed at one time. F / F10
The output signals 703 to 25 can be used as 16 consecutive 1-bit random numbers or as 16-bit random numbers.

The 19-bit output signals of the F / Fs 7 to 25 are input to the exclusive OR operation unit 702. As described with reference to FIG. 5B, the exclusive-OR operation unit 702 has four consecutive ORs.
It has 16 sets of units that operate the F / F output with three exclusive OR calculators, and outputs 16 feedback signals 550 to 565 at the same time.

Of these 16 feedback signals, the most preceding signal 550 is connected to the F / F16 input, the next feedback signal 551 is connected to the F / F15, and the next feedback signal 552 is connected to the F / F14 input. , And so on, 16 feedback signals are sequentially input to the F / Fs 16 to 1.

As described above, according to the second embodiment, the hardware configuration shown in FIG. 7 can generate a random number about 16 times faster than the conventional random number generator shown in FIG. 5A. .

Therefore, since the pseudo random number generated from the random number generator having the configuration shown in FIG. 7 can be supplied to the SIMD processor 308, the random number generator shown in FIG. Further, the pseudo random number processing by the SIMD processor 308 is speeded up more than in the first embodiment including.

The exclusive OR operation unit 702 may be implemented by the logic circuit shown in FIG. 5B, but a so-called lookup is performed using a ROM that connects the output signals of the F / Fs 7 to 25 to each address terminal. If a table is realized, 16 feedback signals can be generated even faster.

<Third Embodiment> Hereinafter, the principle of generating pseudo-random numbers in this embodiment will be described with reference to FIG.
An example realized by software processing using will be described with reference to the flowcharts of FIGS. 8A and 8B.

Initialization Routine FIG. 8A shows the initialization routine of the random number register, that is, the initialization routine of the register in the control processor 401.
Set the number of bits as the random number register Q, the first bit
Initializes 25-bit data from Q (1) to the 25th bit Q (25).

If this initialization routine is performed once when the system is started up, the cycle is always 2 ²⁵ -1 (33554431).
The 25-bit random number that is part of the random number sequence of
Will be held in Q. As described above, the initial value is an arbitrary value in which all bits are not 0.

Random Number Generation Routine FIG. 8B shows a control processor 401 for supplying a random number of 1 bit to 128 PEs that constitute the SIMD processor 308.
5 is a flow chart showing a random number generation routine executed by.

According to the hardware configuration shown in FIG. 6 in the above-described first embodiment, since eight random numbers are generated at one time, in order to generate 128 random numbers for 128 PEs, a generation routine is required. Need to be repeated 16 times. Therefore, first, the counter M for counting 16 times is set to the initial value 0 (S802), and the eight random numbers are set to the random number registers Q (25) to Q (18).
As the output from the control processor 401 to the memory / register of the SIMD processor 308 via the memory / register access bus 414 (S803).

In the SIMD processor 308, each PE is in charge of 2
One byte of the KB memory 411 is allocated as a random number register P *, and eight random numbers are output to the 0th bit P * (0). Where * indicates the PE number, and the counter M
It becomes 0-127 sequentially according to the value of. That is, in step S803, since the counter M is 0, first register PE0 register P0 (0).
1-bit random numbers of Q (25), Q (24) to register P1 (0) of PE1, and Q (18) to register P7 (0) of PE7 are transferred.

Next, the above eight sets of exclusive OR operations are performed (S804). That is, among the 25-bit registers Q (1) to Q (25) corresponding to the output signals of the 25 F / Fs shown in FIG. 5B, Q (18) to Q (25 ) Is stored in the working register WR1. The 8-bit data stored in WR1 is the eight exclusive OR calculators 528, 542, 5 shown in FIG. 5B.
Corresponds to one input signal of 45, ..., 548.

Similarly, Q (17) to Q are sent to the working register WR2.
Stores (24). The 8-bit data stored in WR2 is shown in Figure 5B.
8 exclusive OR calculators 528,542,545, ..., 548 shown in
Corresponds to the other input signal of.

Similarly, Q (16) to Q (23) are input to the working register WR3 as input signals to the exclusive OR calculators 527, 541, 544, ..., 547, and an exclusive OR operation is input to the working register WR4. Q as an input signal to the devices 526,540,543, ..., 546
(15) to Q (22) are stored respectively.

Then, the exclusive OR operation result of WR1 and WR2 is sent to the working register WR5, the exclusive OR operation result of WR5 and WR3 is sent to the working register WR6, and the exclusive OR operation result of WR6 and WR4 is sent to the working register. Store in WR7 respectively.

Therefore, the data of WR5 which is the exclusive OR operation result of WR1 and WR2 corresponds to the outputs of the eight exclusive OR calculators 528, 542, 545, ..., 548 shown in FIG. 5B. With WR5
The data of WR6, which is the exclusive OR operation result with WR3, corresponds to the output of the exclusive OR calculators 527, 541, 544, ..., 547, and similarly the exclusive OR operation result of WR6 and WR4. The data of a certain WR7 is the exclusive OR calculator 526,540,54
3, ..., 546 outputs, i.e. 8 feedback signals 550,551,552, ...,
Equivalent to 557.

As described above, in step S804, as shown in FIG.
The eight sets of exclusive OR operations shown in are executed as three exclusive OR operations using an 8-bit register.

Next, processing corresponding to the F / F shift operation shown in FIG. 6 is performed (S805). That is, the values of Q (10) to Q (17) are transferred to the registers Q (18) to Q (25) whose output has ended as random numbers,
The values of Q (2) to Q (9) are transferred to Q (10) to Q (17) after the transfer is completed.

Similarly, after transferring the data of Q (1) to Q (9), the eight feedback signals obtained in step S804, that is, the values of the working register WR7 are set to Q (8) to Q (1). Give feedback to. That is, WR7 (0) that returns at the beginning is set to Q (8), and WR7 (1) is set to
It is sequentially fed back to Q (7), the value of WR7 (7) is input to Q (1), and the transfer process is completed.

After the value of M is updated by 1 (S806), the processes of steps S803 to S806 are repeated 16 times (S807) to obtain 128 1-bit random numbers for 128 sets of PEs in the SIMD processor. Can be entered.

Here, the control processor 401 of the present embodiment.
Is the so-called SISD (Single Instruction stream Single
Since it is a data stream type processor, it is suitable for so-called sequential image processing such as the LFSR method. Therefore,
If the control processor 401 is capable of sufficiently high-speed processing as compared with the SIMD type processor 308, it is needless to say that it generates a 1-bit random number for each clock transfer described in FIG. 5B, and is stored in the program memory 402. Instructions are 1 word with 41 bits for control processor and 31 bits for SIMD 7
In the VLIW (Very Long Instructin Word) method, which is 2 bits, this type of sequential processing is performed using the SISD method control processor when the simultaneous operation is performed by the same clock.
Further speed-up can be expected by executing the speed-up algorithm according to the present invention.

The control processor 401 and the SIMD type processor 308 are monolithic processor chips, respectively.

Image Processing Using Random Numbers Image processing performed by the SIMD processor 308 using the random numbers generated by the control processor 401 as described above will be described below with reference to the flowchart of FIG.

In this embodiment, one raster 7168 whose shading has been corrected by the reading unit 201 shown in FIG.
The image signal of the pixel is equal to the number of PEs of SIMD processor 308 1
It is divided into 28 pixels for processing.

The image signal read by the CCD by the reading unit 201 is input as an 8-bit image signal to the FIFO memory 301 in the image processing processor unit 204 via the image data control unit 203, and the input register 302, It is stored in the working memory 216 via the external memory interface 306.

Of the image signals of one raster read from the working memory 216, first, the image data of the first 128 pixels is input to the registers of the PEs in charge thereof (S901), and the image data is processed to the luminance. Since it is a signal, it is logarithmically converted into a density signal (S902). At this time, the random number generation routine by the control processor 401 described with reference to FIG. 8B is executed (S903).

In this embodiment, the SIMD processor 30
The instruction of 8 and the instruction of the control processor 401 are composed of 72 bits in one word, and the 41-bit instruction code for the control processor 401 and the 31-bit for the SIMD processor 308 execute each at the same time. Control processor 401 shown
Random number generation process (S903) by logarithmic conversion process (S902)
It will be started at the same time.

The density data obtained as a result of the logarithmic conversion is subjected to density conversion processing for density adjustment according to the input from the operation panel 212 (S904). Similarly, the spatial filtering process is performed on the image signal according to the designation of the image mode set by the input of the operation panel 212 or the like (S905).
After that, a pseudo halftone process (S906) is performed, which is a typical image processing routine using the pseudo random number generated in this embodiment. As the pseudo intermediate length process, an error diffusion process, a tissue dither process, or the like is selectively performed. In the present embodiment, an example of performing a random number dither process for binarizing an image by directly using a random number will be described later.

After performing other processing, the binarized image signal as a recording signal is transferred to the external working memory 216 (S908), and the processing of the first 128 pixels of one raster is completed. The processing for one raster (7168 pixels) is completed by repeating the processing of steps S901 to S908 56 times (S909).

Therefore, in the random number generation routine of step S903, all the processes shown in FIG. 8B must be completed before the processes of steps S901 to S908 are completed. It is assumed that the initialization routine of the random number register shown in FIG. 8A has already been completed when the power is turned on, for example.

By repeating the raster processing of steps S901 to S909 described above for 4960 lines, A4 size 1
The processing of the page ends (S910).

Details of the pseudo halftone process in step S906 will be described below with reference to the flowchart in FIG.

FIG. 10 is a flowchart showing the random number dither processing in this embodiment. First, the last step
An 8-bit image signal is transferred to the 8-bit register B in the general-purpose register 406 of each PE from the internal memory 411 that stores the result of the spatial filter processing performed in S905 (S1001). S
Since 128 PEs simultaneously operate in the IMD processor 308, in this step S1001, the 128 image signals stored in the memory 411 are simultaneously transferred to the general-purpose register B in charge of each PE of the SIMD processor 308. Will be there.

As described above, the internal memory 41 of each PE is
8-bit random number registers P (0) to P (7) are set to 1 respectively, and the 0th bit P (0) of the random number register is set immediately before by the execution of the random number generation routine shown in FIG. 8B. The generated 1-bit random number is written. In the present embodiment, the random number written from the control processor 401 for each pixel is stored as the past 8 pixels, that is, 8 bits as P (0) to P (7), and the 8-bit random number is 2 It is used as a threshold for binarization.

That is, the binary data of the random number registers P (0) to P (7) is stored in the register PER in the PE register 408 as an 8-bit random number (S1002), and the random number for processing the next pixel is stored. P (6) → P (7), P (5) → P (6), P (4) →
1-bit shift is performed as in P (5), ..., P (0) → P (1) (S1003).

After that, 0 is stored as the initial value of the binarization result in the binarization register C in the general-purpose register 406 (S1004), and the image signal B is binarized using the random number PER as a threshold (S1005). That is, if the image signal B is larger than the random number PER, the binarization register C is rewritten to 1 (S1006), and then the value of the binary register C is output to the internal memory 411 (S1007). At this time, the binarization result for 128 pixels is obtained as in the case of image input, and the image transfer to the internal memory 411 is simultaneously performed for 128 bits.

By the processing in the above steps S1001 to S1007, 1/56 of one raster, that is, binarization of 128 pixels is completed.

As described above, according to the third embodiment, the pseudo random number generation process realized by the hardware configuration shown in FIG. 6 in the first embodiment described above is realized by the software process by the control processor 401. be able to.

Therefore, since the pseudo random number generated at high speed by the control processor 401 can be supplied to the SIMD processor 308, high speed pseudo random number processing by the SIMD processor becomes possible.

<Fourth Embodiment> The control processor 40 will be described below.
Another processing example of the pseudo random number generation processing by the software processing in 1 will be described with reference to the flowchart in FIG. 8C. 8C, similar to FIG. 8B, the random number generation process by the hardware shown in FIG. 6 in the first embodiment is performed by the control processor.
9 is a flowchart showing a random number generation routine executed by 401, in which the same step numbers are assigned to the same processes as the steps shown in FIG. 8B. The pseudo-random number generation process shown in FIG. 8C is characterized in that the exclusive OR operation is performed by LUT conversion, thereby further speeding up the process shown in FIG. 8B.

According to the hardware configuration shown in FIG. 6 in the above-described first embodiment, eight random numbers are generated at one time, and therefore 128 random numbers for 128 PEs are generated in this embodiment. Requires the generation routine to be repeated 16 times. Therefore, also in the flowchart shown in FIG. 8C, first, the counter M for counting 16 times is set to the initial value 0 (S802), and eight random numbers are set to the random number registers Q (25) to Q (18).
As the output from the control processor 401 to the memory / register of the SIMD processor 308 via the memory / register access bus 414 (S803).

In the SIMD processor 308, each PE is in charge of 2
One byte of the KB memory 411 is allocated as a random number register P *, and eight random numbers are output to the 0th bit P * (0). Where * indicates the PE number, and the counter M
It becomes 0-127 sequentially according to the value of. That is, in step S803, since the counter M is 0, first register PE0 register P0 (0).
1-bit random numbers of Q (25), Q (24) to register P1 (0) of PE1, and Q (18) to register P7 (0) of PE7 are transferred.

Then, similar to the processing in step S804 of FIG. 8B, eight sets of exclusive OR operations are performed using the LUT (S809). That is, in step S809, as shown in FIG. 5B.
25-bit register Q corresponding to 25 F / F output signals
Of the (1) to Q (25), the 2 bits of the data memory 403, which uses the 11-bit signal of the register Q (15) to Q (25) in the subsequent stage as an address, is used as a look-up table. Directly obtain signals 550-557. Therefore, first, 11-bit data is input to the working register WR1, and the value of the LUT (WR1) is input to the working register WR7 as a feedback signal. In the present embodiment, as described above, the 8 sets of exclusive OR operations shown in FIG. 6 are performed by using the 2 KB LUT in the data memory 403 in which the operation result is written in advance to obtain the feedback signal at high speed. be able to.

After that, a process corresponding to the F / F shift operation shown in FIG. 6 is performed (S805). That is, the values of Q (10) to Q (17) are transferred to the registers Q (18) to Q (25) whose output is finished as random numbers, and Q (10) to Q (17) are transferred to the registers Q (18) to Q (17). Transfer the values from (2) to Q (9).

Similarly, after transferring the data of Q (1) to Q (9), the eight feedback signals obtained in step S804, that is, the values of the working register WR7 are set to Q (1) to Q (8). Give feedback to. That is, WR7 (0) that returns at the beginning is set to Q (8), and WR7 (1) is set to
It is sequentially fed back to Q (7), the value of WR7 (7) is input to Q (1), and the transfer process is completed.

After the value of M is updated by 1 (S806), the processes of steps S803 to S806 are repeated 16 times (S807), so that 128 1-bit random numbers are set for 128 sets of PEs in the SIMD processor. Can be entered.

As described above, according to the fourth embodiment, as compared with the processing shown in FIG. 8B in the third embodiment, L
By using UT, higher speed processing is possible.

<Fifth Embodiment> Hereinafter, the control processor 40 will be described.
Pseudo-random number generation processing by software processing in 1 will be described with reference to a flowchart of FIG. 8D as another processing example. FIG. 8D is a flowchart showing a random number generation routine in which the control processor 401 executes a random number generation process for simultaneously generating 16 random number sequences by the hardware shown in FIG. 7 in the second embodiment.

According to the hardware configuration shown in FIG. 7 in the second embodiment described above, 16 random numbers are generated at one time, so in the present embodiment, 128 random numbers for 128 PEs are generated. Requires the generation routine to be repeated eight times. Therefore, in the flowchart shown in FIG. 8D, first, a counter M for counting 8 times is set to an initial value 0 (S812), and 16 random numbers are stored in the random number registers Q (25) to Q (10).
As the output from the control processor 401 to the memory / register of the SIMD processor 308 via the memory / register access bus 414 (S813).

In the SIMD processor 308, each PE is in charge of 2
One byte of the KB memory 411 is assigned as a random number register P *, and 16 random numbers are output to the 0th bit P * (0). Where * indicates the PE number, and the counter M
It becomes 0-127 sequentially according to the value of. That is, in step S813, since the counter M is 0, first register PE0 register P0 (0).
1-bit random numbers of Q (25), Q (24) to the register P1 (0) of PE1, and Q (10) to the register P15 (0) of PE15 are transferred.

Next, the above 16 sets of exclusive OR operations are performed (S814). That is, among the 25-bit registers Q (1) to Q (25) corresponding to the output signals of the 25 F / Fs shown in FIG. 5B, Q (10) to Q (25 ) Is stored in the 16-bit working register WR1. 16 stored in WR1
The bit data serves as one input signal of the 16 arithmetic units corresponding to the 8 exclusive OR arithmetic units 528, 542, 545, ..., 548 shown in FIG. 5B.

Similarly, Q (9) to Q (2
Store 4). The 16-bit data stored in WR2 is 1 above.
It becomes the other input signal of the six arithmetic units.

Similarly, to the working register WR3, the data shown in FIG.
8 exclusive OR operators 527,541,544, ..., 547
Q (8) to Q (2
3) to the working register WR4 and the exclusive OR calculator 5
Q (7) to Q (22) are respectively stored as input signals to 16 arithmetic units corresponding to 26,540,543, ..., 546.

Then, the exclusive OR operation result of WR1 and WR2 is sent to the working register WR5, the exclusive OR operation result of WR5 and WR3 is sent to the working register WR6, and the exclusive OR operation result of WR6 and WR4 is sent to the working register. Store in WR7 respectively.

Therefore, the data of WR5 which is the exclusive OR operation result of WR1 and WR2 indicates the output of 16 arithmetic units corresponding to the exclusive OR arithmetic unit 528 and the like. The data of WR6, which is the exclusive OR operation result, indicates the outputs of 16 arithmetic units corresponding to the exclusive OR operation unit 527 and the like, and similarly is the exclusive OR operation result of WR6 and WR4. The data of a certain WR7 indicates the outputs of 16 arithmetic units corresponding to the exclusive OR arithmetic unit 526, that is, 16 feedback signals 550,
Equivalent to 551,552, ..., 567.

As described above, in step S814, as shown in FIG.
The 16 sets of exclusive OR operations shown in are performed as three exclusive OR operations using a 16-bit register.

Next, a process corresponding to the F / F shift operation shown in FIG. 7 is performed (S815). That is, the values of Q (1) to Q (9) are transferred to the registers Q (17) to Q (25) whose output has ended as random numbers, and the 16 feedback signals obtained in step S814, that is, the working register WR7. The value of is fed back to Q (16) to Q (1).
That is, WR7 (0) that returns at the beginning is set to Q (16) and WR7 (1) is set to Q (15).
Then, the value of WR7 (15) is input to Q (1), and the transfer process is completed.

After updating the value of M by 1 (S816), the processes of steps S813 to S816 are repeated 8 times (S817) to obtain 128 1-bit random numbers for 128 sets of PEs in the SIMD processor. Can be entered.

As described above, according to the fifth embodiment, the pseudo-random number generation processing realized by the hardware configuration shown in FIG. 7 in the second embodiment described above is realized by software processing by the control processor 401. be able to. Since the configuration of FIG. 7 realizes twice the processing speed as compared with the configuration of FIG. 6, according to the fifth embodiment, that is, in the third embodiment showing the software processing corresponding to the configuration of FIG. As compared to the processing shown in FIG. 8B, it is possible to perform high-speed processing that is about twice as fast.

The fourth embodiment described above also for the fifth embodiment.
It is possible to apply the exclusive logical wheel operation by the LUT shown in the embodiment, and further speedup can be expected by this.

<Modification> The above-described embodiment is only one form of the present invention, and the present invention can be modified as follows.

Applicable Random Number Processing Random numbers obtained by the random number generation method of the present invention are not limited to the random number dither shown in the above-described embodiment, and for example, when 1-bit random number output is performed by the error diffusion method. The present invention can be applied to all general random number processes such as switching the distribution ratio of an error and adding a multi-bit random number to an image signal.

Use of Random Numbers at Plural Places In the above-described embodiment, the example in which the random number dither method is continuously performed for one page has been shown. However, for example, different image processing is continuously performed for each raster and When a random number is used at a location, the application position of the random number register may be changed instead of executing the random number generation routine each time. For example, by using a 1-bit random number by the random number register P (7) in the first process, a 4-bit random number by the random number register P (0) to P (3) in the second process, etc. It is possible to prevent a decrease in processing speed due to the random number generation routine being executed a plurality of times.

Similarly, for example, when one pixel is color-separated into RGB and the RGB data of one pixel is continuously processed, the random number register P (7) is for R data and P (6) is for G data. Therefore, if P (5) is used for B data, the processing speed can be increased.

LFSR Further, in the above-mentioned embodiment, the 25-stage LFSR is shown as an example, but it is needless to say that the same effect can be obtained by applying the pseudo random number generating method having other periodicity.

<Other Embodiments> Incidentally, even when the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus consisting of one device ( For example, it may be applied to a copying machine, a facsimile machine, etc.). Also,
An object of the present invention is to provide a storage medium in which a program code of software for realizing the functions of the above-described embodiment is recorded,
It is needless to say that it is also achieved by supplying to the system or device, and the computer (or CPU or MPU) of the system or device reads and executes the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

A storage medium for supplying the program code is, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD.
-ROM, CD-R, magnetic tape, non-volatile memory card, RO
M etc. can be used.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the OS (operating system) operating on the computer based on the instruction of the program code. ) Etc. do some of the actual processing,
It goes without saying that the processing includes the case where the functions of the above-described embodiments are realized.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code, The CPU provided in the function expansion board or function expansion unit performs some or all of the actual processing,
It goes without saying that the processing includes the case where the functions of the above-described embodiments are realized.

[0153]

As described above, according to the present invention, SI
High-speed pseudo-random number processing by the MD processor is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic functional configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a hardware configuration of an image processing apparatus according to this embodiment.

FIG. 3 is a block diagram showing a detailed configuration of an image processor.

FIG. 4 is an arithmetic processing unit 30 including a SIMD type processor.
FIG. 3 is a block diagram showing a schematic configuration of 0.

FIG. 5A is a diagram showing a hardware configuration of a conventional random number generator based on the LFSR method.

FIG. 5B is a diagram showing a hardware configuration of a pseudo random number generation device according to the present embodiment.

FIG. 6 is a diagram showing a hardware configuration of a pseudo random number generation device in the first embodiment.

FIG. 7 is a diagram illustrating a hardware configuration of a pseudo random number generation device according to a second exemplary embodiment.

FIG. 8A is a flowchart showing an initialization routine of a pseudo random number generation process in the third embodiment.

FIG. 8B is a flowchart showing a pseudo random number generation routine in the third embodiment.

FIG. 8C is a flowchart showing a pseudo random number generation routine in the fourth embodiment.

FIG. 8D is a flowchart showing a pseudo random number generation routine in the fifth embodiment.

FIG. 9 is a flowchart showing image processing using a pseudo random number generated in the third embodiment.

FIG. 10 is a flowchart showing random number dither processing in the third embodiment.

[Explanation of symbols]

204 Image processor 300 arithmetic processing unit 301, 307 FIFO memory 302 Input register 303 Data processing unit 304 output register 305 Control processor 306 External memory interface

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Manabu Takebayashi             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation F term (reference) 5B057 CA12 CA16 CB07 CB12 CB16                       CE13 CH02 CH04 CH07 CH08                 5C077 LL03 MP01 NN08 PQ12 PQ20

Claims (16)

[Claims] 1. An image processing apparatus for performing image processing using pseudo-random numbers in a processor in which a plurality of processor elements operate in parallel and simultaneously according to a single program, and a plurality of registers forming a linear feedback shift register. , N sets of calculation means for calculating an exclusive OR of outputs from a predetermined number of registers, feedback means for returning each output data from the N sets of calculation means to N registers at the same time, Shift means for shifting the data held in the register of each to a register located at a subsequent stage, feedback data by the feedback means, and random number generation means for generating a pseudo-random number from the data shifted by the shift means, And the processor is configured to perform image processing using the pseudo-random number generated by the random number generating means. An image processing device characterized by: 2. The image processing apparatus according to claim 1, wherein the random number generating means simultaneously generates an N-bit pseudo random number. 3. The image processing apparatus according to claim 1, wherein the N sets of calculation means perform respective calculation processes in parallel. 4. The image processing apparatus according to claim 1, wherein the N is 8. 5. The image processing apparatus according to claim 1, wherein the N is 16. 6. The N sets of computing means are each configured by a lookup table.
The image processing device described. 7. The image processing apparatus according to claim 1, wherein the register, the feedback unit, the shift unit, and the random number generation unit are realized on a processor different from the processor. 8. An image processing method for causing a processor in which a plurality of processor elements operate in parallel and simultaneously in accordance with a single program, to perform image processing using pseudo-random numbers, the plurality of registers constituting a linear feedback shift register. Of the N sets of a predetermined number of registers, an operation step of performing respective exclusive OR operations, a feedback step of returning N output data of the operation step to N registers at the same time, A shift step of shifting the data held in the register to a register located at a subsequent stage, respectively, a random number generation step of generating pseudo random numbers from the feedback data by the feedback step and the data shifted by the shift step, The image processing unit using the pseudo-random number generated in the random number generation step. Image processing method, characterized in that to perform. 9. A first processor that generates a pseudo random number, a second processor that performs image processing using the pseudo random number, and a pseudo random number that is generated by the first processor to the second processor. An image processing apparatus comprising: 10. The image processing apparatus according to claim 9, wherein the second processor is a SIMD type processor in which a plurality of processor elements simultaneously operate in parallel according to a single program. 11. The image processing apparatus according to claim 9, wherein the first and second processors are VLIW type processors that execute instructions with the same clock. 12. The image processing apparatus according to claim 9, wherein the first and second processors are monolithic processor chips. 13. An image processing method in an image processing apparatus having first and second processors, comprising: a random number generation step of generating a pseudo random number in the first processor; An image processing method, comprising: a supply step of supplying the processor to the processor of 1); and an image processing step of performing image processing by the second processor using the supplied pseudo-random number. 14. The image processing method according to claim 13, wherein the second processor is a SIMD type processor in which a large number of processor elements simultaneously operate in parallel according to a single program. 15. A program that, when executed by a computer, causes the computer to operate as the image processing apparatus according to claim 1. 16. A recording medium on which the program according to claim 15 is recorded.