JP2001184377A - Operation delay computer and operation delay computing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely calculate the delay of a continuous operation and to accurately conduct scheduling. SOLUTION: A continuous operation analysis part analyzes the type of the operation of a continuous operation formula and bit width, which are inputted from a continuous operation input part. A calculation type selection part selects a calculation type by referring to a calculation type library in accordance with the type of the operation of the inputted continuous operation formula. A calculation method selection part selects a calculation method in accordance with the type of the inputted continuous operation formula by referring to a calculation method library. A delay calculation part calculates the additional delay of the inputted continuous operation formula by using the calculation method selected in accordance with the type, adds the additional delay to the delay of the first operation and calculates the delay of the continuous operation. Thus, the delay of the continuous operation can more precisely be calculated and scheduling can more accurately be conducted compared to a conventional method where the delays of the first and second operations are simply added.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-level synthesis technique for synthesizing a logic circuit from an operation description, and more particularly to an arithmetic delay calculating apparatus and method used for a scheduling process for synthesizing a logic circuit by the high-level synthesis technique. .

[0002]

2. Description of the Related Art In recent years, product cycles have been shortened, and there has been a demand for a reduction in time from design to introduction to the market. In order to shorten the design period, a design technique has emerged in which the logic design level is raised to an operation level having a higher abstraction level than the conventional register transfer level (hereinafter, referred to as an RT level). In particular,
Attention has been paid to a high-level synthesis technique for synthesizing a logic circuit from a description of an operation level (hereinafter referred to as an operation description).

In order to synthesize a high-performance circuit using this high-level synthesis technique, a high-performance scheduling process is required. Scheduling is a process of dividing an operation in an operation description into grooves that are executed every clock cycle. The operation sequence that can be executed within one clock cycle can be put into one group.

[0004]

In the above-described scheduling, since the grouping is performed based on the operation delay, the accuracy of the delay calculation greatly affects the scheduling result. In particular, since the delay of a continuous operation is conventionally calculated as the sum of the delays of the individual operations, there is a large error from the actual delay value, and although a continuous operation can be normally performed in one clock cycle, However, an erroneous determination that execution cannot be performed in one clock cycle has occurred, and a situation has occurred in which a continuous operation is divided into separate groups. For this reason, there has been a problem that the number of clock cycles until the end of the operation is large, that is, a logic circuit having a low processing speed is synthesized.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to accurately calculate a delay of a continuous operation, and to accurately perform scheduling. An operation delay calculating apparatus and method are provided.

[0006]

In order to achieve the above object, a feature of the present invention is to calculate a delay when a continuous operation including a first operation and a second operation is performed by a logic circuit. In the operation delay calculation method, the pair of the type of the first operation and the type of the second operation and the pair of the bit width of the first operation and the bit width of the second operation are uniquely determined. Calculating the delay, adding the calculated additional delay to a delay of the first operation, which is determined in advance by the type and bit width of the first operation, and calculating the delay from the first and second operations. And calculating the delay of the continuous operation. A feature of the invention according to claim 2 is that the type of the first operation and the second operation
And a calculation type determined by a pair of the operation types described above, and calculating an additional delay uniquely determined by a pair of the calculation type, the bit width of the first operation, and the bit width of the second operation. .

According to a third aspect of the present invention, there is provided an operation delay calculator for calculating a delay when a continuous operation including a first operation and a second operation is performed by a logic circuit. Analysis means for obtaining the type and bit width of each operation of a continuous operation comprising a second operation; type selection means for obtaining a calculation type corresponding to a pair of the first operation and the second operation type; A calculation method selecting means for selecting a calculation method of an additional delay corresponding to the obtained calculation type; and calculating the additional delay by using the selected calculation method and using the obtained bit width of each operation as a parameter. Delay calculation means for adding the additional delay to the delay of the first calculation to calculate the delay of the continuous calculation.

According to a fourth aspect of the present invention, the type selecting means includes:
A first holding unit that holds a calculation type corresponding to a pair of the first operation and the second operation obtained by changing the bit width of the first operation and the second operation. The calculation type corresponding to the pair of the type of the first operation and the type of the second operation is determined with reference to the holding unit, and the calculation method selection unit determines the first type determined in advance for each type.
And a second holding means for holding a calculation method of the additional delay expressed by a function of the bit width of the second operation, and referring to the holding means, the additional delay of the additional delay corresponding to the calculation type is referred to. Find the calculation method.

According to a fifth aspect of the present invention, the bit width of the first and second operations is changed for each calculation type of the continuous operation, and the continuous operation is performed by a logic circuit obtained by logic synthesis. There is provided a constant generation means for collecting delay data obtained by the execution and obtaining a constant used in the method of calculating the additional delay based on the collected delay data.

In scheduling, which is one of the high-level synthesis processes for synthesizing a logic circuit from an operation description, it is necessary to estimate an operation delay. The difference between the estimated value and the actual value greatly affects the scheduling result. In particular,
If the delay of successive calculations is estimated as the sum of the delays of the individual calculations, the difference from the actual value is large. This difference adversely affects the scheduling result. Therefore, by providing an accurate calculation method of the delay value of the continuous operation, it is possible to perform a scheduling process with high performance.

According to the above invention, when calculating the delay of the continuous operation consisting of the first operation and the second operation, a pair of the type of the first operation and the type of the second operation and the first The additional delay uniquely determined by the pair of the bit width of the operation and the bit width of the second operation is calculated, and the additional delay is added to the delay of the first operation to obtain the delay of the continuous operation. I have.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration according to an embodiment of the operation delay calculation device of the present invention. The operation delay calculation device includes a continuous operation input unit 1 for inputting a continuous operation expression 100, a continuous operation analysis unit 2 for analyzing the type of operation and the bit width of the input continuous operation expression 100, A calculation type selection unit 3 for selecting a calculation type according to the type of operation, a calculation type library 4 for holding a calculation type according to the type of operation, and a calculation for selecting a calculation method according to the input calculation type of the continuous operation expression 100 A method selection unit 5, a calculation method library 6 for holding a calculation method of an additional delay according to a calculation type,
A delay calculator 7 calculates a delay of the input continuous operation expression 100 and outputs a delay 200 of the continuous operation.

Next, the operation of this embodiment will be described. The continuous operation expression 100 is an operation expression to be subjected to delay calculation. The continuous operation input unit 1 inputs the continuous operation expression 100 to the continuous operation analysis unit 2. The continuous operation analysis unit 2 analyzes the type and bit width of each operation of the continuous operation expression 100. For example, when the continuous arithmetic expression 100 is “(x + y) × z”, the bit width of the addition is 16 and the bit width of the multiplication is 32, the analysis result is as shown in FIG.

The calculation type selection unit 3 selects a calculation type registered in the calculation type library 4 according to the type of each operation analyzed by the continuous operation analysis unit 2. The correspondence between the type of operation registered in the calculation type library 4 and the calculation type is, for example, as shown in FIG.

The calculation method selection unit 5 selects a calculation method registered in the calculation method library 6 according to the calculation type selected by the calculation type selection unit 3. Delay calculator 7
Calculates the delay of the continuous operation expression 100 using the calculation method selected by the calculation method selection unit 5 and using the bit width of each operation analyzed by the continuous operation analysis unit 2 as a parameter. The delay 200 of the continuous operation is the result calculated as described above.

Next, the processing method of the continuous operation analysis unit 2, calculation type selection unit 3, calculation method selection unit 5, and delay calculation unit 7 will be described in detail with reference to the flowchart of FIG.

FIG. 4 is a flowchart showing the flow of processing from the continuous operation analysis unit 2 to the delay calculation unit 7. In this flowchart, the continuous operation expression 100 is 2
It is assumed that there is a continuous configuration of one operation.

First, the continuous operation analysis unit 2 executes step 401
The type of the first operation of the continuous operation is op1 and the bit width is w.
1. Analyze the type of the second operation as op2 and the bit width as w2. In step 402, the calculation type selection unit 3 selects a calculation type from the calculation type library 4 based on the types of continuous operations op1 and op2.

For example, as shown in FIG. 3, there are three types of calculation from type 1 to type 3. These calculation types are registered in the calculation type library 4 in advance. The calculation method of the additional delay differs depending on these calculation types. In step 403, the calculation type selection unit 3 selects a calculation method from the calculation method library 6 according to the calculation type. In this embodiment, the delay of two consecutive calculations is calculated in the form of “delay of first calculation + additional delay Δ”.

FIG. 5 is a table showing an example of a method of calculating an additional delay for each calculation type. However, in the figure, d, d1, d
2 is a function and c is a constant. In the case of Type 1, the additional delay Δ is calculated by the constant c and the sum of functions of the difference (w2−w1) between the bit width w2 of the second operation and the bit width w1 of the first operation. As a function of the difference (w2-w1), w
A different function d1 or d2 is used depending on the magnitude relationship between 1 and w2.

The constant c takes different values depending on the type of the first operation op1 and the type of the second operation op2. Functions d1, d2
Is a function of the difference (w2-w1) between the bit width w2 of the second operation and the bit width w1 of the first operation as shown in FIG. The constants a and b appearing in the functions d1 and d2 are the types of the first operation op1
And a different value depending on the type op2 of the second operation.

In the case of type 2, the additional delay Δ is a function d of the bit width w1 of the first operation and a bit width w of the second operation.
2 and a function of the difference (w2-w1) between the bit widths w1 of the first operation. The function d is a function of w1 as shown in FIG. The constants c1 and c2 appearing in the function d take different values depending on the type of the first operation op1 and the type of the second operation op2. As a function of the difference (w2-w1), w1
A different function d1 or d2 is used depending on the magnitude relation between w1 and w2. The functions d1 and d2 are the functions shown in FIG.

In the case of type 3, the additional delay Δ is calculated by the constant c and the sum of the functions of the difference (w2−W1) between the bit width w2 of the second operation and the bit width w1 of the first operation. However, if w2 is greater than w1, the additional delay Δ
Is calculated as a constant c. The function d1 is shown in FIG.

In step 404, the additional delay Δ is calculated using the bit width w1 of the first operation and the bit width w2 of the second operation as parameters according to the calculation method selected as described above. Finally, the delay calculator 7 calculates the delay of the continuous calculation by taking the sum of the delay of the first calculation (stored in the calculation method library 6 or the like) and the additional delay Δ calculated at step 404 in step 405.

The functions Δ (w1, w2) and d1 (w2-w)
FIG. 8 shows examples of values of the constants c, a, and b appearing in 1) and d2 (w2-w1). These values are calculated based on the delay values actually logically synthesized. As an example, FIG. 9 shows a delay calculation result of the continuous operation (x + y + z). FIG.
In the example shown in the above, the bit width of the first operation is 16 and the bit width of the second operation is 32. FIG. 9 also shows the result of the conventional delay calculation. For example, the clock
Assuming that the cycle is 10 NS seconds, when performing scheduling, using a conventional delay calculation method,
Calculated as 15.17 NS seconds and cannot schedule successive additions to be performed in the same clock cycle.

However, when the calculation method of the present invention is used,
It is calculated to be 9.37 NS seconds and can be scheduled so that successive additions can be performed in the same clock cycle. Actually, the delay after logic synthesis under the same conditions as when collecting the actual delay values used for calculating the constants appearing in the functions Δ (w1, w2) and the like is 9.26 NS seconds, which limits the logic circuit after synthesis. Can be operated in the clock cycle given by. As described above, the use of the delay calculation device of the present invention enables better scheduling.

Next, the generation of constants used in the calculation methods registered in the calculation method library 6 described above will be described with reference to FIG.
0 will be described.

FIG. 10 is a flowchart showing a procedure for generating constants used in the above calculation method. Step 101
Specifies the continuous operation that generates the calculation method. Then, the type of the first operation is op1 and the type of the second operation is op2. In step 102, specify the calculation type of the continuous operation,
Let it be type. FIG. 3 shows an example of the correspondence between the type of operation and the calculation type. In step 103, the calculation type typ is changed by changing the bit width of the first operation and the bit width of the second operation.
Collect data for e. FIG. 11 shows a list of collected data for each calculation type.

For example, in the case of Type 1, delay values obtained by changing the values of the bit width of the first operation and the values of the bit width of the second operation for the operation in the operation (column) column are collected. These delays are collected, for example, by executing logic synthesis. In step 104, a constant appearing in the additional delay Δ is calculated based on the data collected in step 103. FIG. 12 shows an example of a method of calculating these constants. Step 10
In step 5, the additional delay Δ having the constant calculated in step 104 is registered in the calculation method library 6.

As an example, data necessary for calculating a constant appearing in the additional delay Δ in the continuous operation (x + y + z) is shown in FIG.
FIG. 14 shows a calculation result of a constant using the data. A continuous operation in which the type of the first operation is “addition” and the type of the second operation is “addition” is “type 1”. In this case, the result shown in FIG. 14 matches the value shown in FIG.

In general, the constant appearing in the additional delay Δ differs for each logic library used in logic synthesis. If the library 6 is constructed by a method of calculating manually for each logical library, it takes a long time, and there is a possibility that errors may be mixed. Therefore, by automatically generating the additional delay function by the method described in the present embodiment, the calculation method library 6 can be constructed without error and without taking much time.

According to the present embodiment, the delay of the continuous first operation and the second operation is calculated by adding the additional delay Δ obtained by separately calculating the delay of the first operation to the delay of the first operation. The delay of the continuous operation can be calculated more accurately than before, and scheduling can be performed more accurately. For this reason, when the conventional calculation method produces a delay value that cannot be executed in the same clock cycle, when calculated by the method of this example, a delay value that can be executed in the same clock cycle may be obtained. By performing high-level synthesis, a high-performance logic circuit with a short processing time can be obtained.

The operation delay calculation method of the present invention can be typically realized by programming each step shown in the flowchart of FIG. 4 and causing a computer to execute the steps. Similarly, the delay of the continuous operation is accurately calculated. be able to. At that time, the computer program can be supplied to the computer through a disk-type recording medium such as a floppy disk or a hard disk, various memories such as a semiconductor memory or a card-type memory, or various program recording media such as a communication network.

[0034]

As described above in detail, according to the operation delay calculating apparatus and method of the present invention, the delay of the continuous operation can be calculated with high accuracy, and thus the scheduling can be performed accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration according to an embodiment of an operation delay calculation device of the present invention.

FIG. 2 is a table illustrating an example of an analysis result of a continuous operation analysis unit illustrated in FIG. 1;

FIG. 3 is a table showing an example of correspondence between types of calculations and calculation types registered in a calculation type library shown in FIG. 1;

FIG. 4 is a flowchart illustrating a flow of processing from a continuous operation analysis unit to a delay calculation unit illustrated in FIG. 1;

FIG. 5 is a table showing an example of a calculation method for each calculation type registered in the calculation method library of FIG. 1;

FIG. 6 is a table showing specific examples of functions d1 and d2 shown in FIG. 5;

FIG. 7 is a table showing a specific example of a function d shown in FIG. 5;

FIG. 8 is a function Δ used in the delay calculator shown in FIG. 1;
(W1, w2), d1 (w2-w1), d2 (w2-w)
FIG. 3 is a table showing values of constants c, a, and b appearing in 1).

9 is a table showing a result of delay calculation of continuous operation (x + y + z) performed by the apparatus shown in FIG. 1 and a result example obtained by a conventional calculation method.

FIG. 10 is a flowchart showing a procedure for generating constants used in the calculation method registered in the calculation method library shown in FIG.

11 is a table showing a list of examples of collected data for each calculation type collected in step 103 of FIG.

FIG. 12 is a table showing a method of calculating a constant appearing in an additional delay Δ handled in step 104 of FIG. 10;

FIG. 13 is a table showing an example of data necessary for calculating a constant appearing in an additional delay Δ handled in step 104 of FIG. 10;

FIG. 14 is a table showing an example of a result of a constant calculation generated by the method shown in FIG. 10;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Continuous calculation input part 2 Continuous calculation analysis part 3 Calculation type selection part 4 Calculation type library 5 Calculation method selection part 6 Calculation method library 7 Delay calculation part 100 Continuous calculation formula 200 Continuous calculation delay

Claims (5)

[Claims] 1. An operation delay calculating method for calculating a delay when a continuous operation including a first operation and a second operation is performed by a logic circuit, wherein the type of the first operation and the second operation A step of calculating an additional delay uniquely determined by a pair of a type and a bit width of the first operation and a bit width of the second operation; and a priori knowledge determined by the type and the bit width of the first operation. Calculating the delay of the continuous operation including the first and second operations by adding the calculated additional delay to the delay of the first operation. Method of calculation. 2. A calculation type determined by a pair of a type of the first operation and a type of the second operation is set, and the calculation type, a bit width of the first operation, and a bit of the second operation are set. 2. The method according to claim 1, wherein an additional delay uniquely determined by the pair of widths is calculated. 3. An operation delay calculation device for calculating a delay when a continuous operation including a first operation and a second operation is performed by a logic circuit, wherein the continuous operation includes the first operation and the second operation. Analysis means for obtaining the type and bit width of each operation of the operation; type selection means for obtaining the calculation type corresponding to the pair of the first operation and the second operation; and corresponding to the obtained calculation type Calculating method selecting means for selecting a calculating method of the additional delay, calculating an additional delay using the selected calculation method and using the bit width of each of the calculated operations as a parameter,
A delay calculating means for adding the obtained additional delay to the delay of the first calculation to calculate the delay of the continuous calculation. 4. A calculation type corresponding to a pair of a type of the first operation and the type of the second operation obtained by changing a bit width of the first operation and the second operation. A first holding unit for holding a calculation type, and by referring to the holding unit, a calculation type corresponding to a pair of the type of the first operation and the type of the second operation is obtained. A second holding unit for holding a calculation method of an additional delay expressed as a function of a bit width of the first operation and the second operation determined in advance for each calculation type; 4. The operation delay calculation device according to claim 3, wherein a calculation method of an additional delay corresponding to the calculation type is obtained by calculation. 5. A delay obtained by changing each bit width of the first and second operations for each calculation type of the continuous operation and executing the continuous operation by a logic circuit obtained by logic synthesis. 5. The arithmetic delay calculating apparatus according to claim 3, further comprising a constant generation unit that collects data and obtains a constant used in the method of calculating the additional delay based on the collected delay data.