JP2001184253A - Processor system and storage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor system capable of speeding up the memory access. SOLUTION: Plural memory blocks 141 respectively provided with a storage region in which plural first memory cells connected to bit lines selected by a column decoder 21a and a plural second memory cells connected to bit lines selected by a column decoder 21b are allowed to coexist in the column direction and a low decoder for driving word lines to which the fist memory cells and the second memory cells are connected are arranged in the column direction in the processor system, and plural processors are arranged so as to be faced to the plural memory blocks respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a processor system and a storage circuit, and more particularly to a processor system and a storage circuit capable of speeding up memory access.

[0002]

2. Description of the Related Art In a general processor, the following processes (1) to (4) are sequentially performed in response to a Read Modify Write command. (1) Data in a memory such as a DRAM (Dynamic Random Access Memory) is read into a register of an ALU (Arithmetic Logic Unit). (2) The ALU performs an arithmetic process using a constant prepared in advance or data of a predetermined register in the ALU and data read to the register in (1). (3) The data obtained in the operation processing of (2) is written to a register in the ALU. (4) The data written in the register in the ALU in (3) is written back to the memory again.

One or more clock cycles are assigned to each of the above operations (1) to (4). In a general processor, the above (2),
In many cases, one clock cycle is assigned to each operation in the ALU shown in (3), and two or more clock cycles are assigned to memory access. Alternatively, the above (2) and (3) may be collectively allocated to one clock cycle. This is because, if the memory access speed is set as a reference, the processing in the ALU becomes redundant from the viewpoint of the operation time, and the time during which no processing is performed in the ALU becomes longer. This is also because the access method of a DRAM or the like differs depending on the order in which addresses in the memory cells are designated, and the like, and the logical access sequence differs. On the other hand, the memory access speed varies with the device characteristics itself, and the memory access time cannot be uniquely determined. Even when the memory is integrated on the same semiconductor substrate as the ALU, the access speed varies greatly depending on the size of the memory and the memory configuration (the method of dividing rows and columns). Therefore, the reference is made to the internal operation speed of the ALU, and a plurality of clock cycles are allocated to other operations such as a memory access operation. In this case, when a control circuit such as a memory controller starts a memory access operation, A
A wait signal for stopping the processing is output to the LU, and a wait release signal for releasing the stop of the processing is output to the ALU when the memory access operation is completed.

[0004] The execution speed of an instruction involving memory access as described above largely depends on the memory access speed. There are various factors that delay the memory access speed. For example, in the case of a DRAM, a transistor forming a memory cell drives a bit line (data line), the capacity and resistance of the bit line itself, and a sense. The performance of the amplifier, the performance of the column select circuit after the memory cell output stage, and the like can be considered. However, in order to improve the memory access speed, it is not sufficient to simply change the memory cell itself, the sense amplifier, and the like in terms of circuit. Therefore, conventionally, the wiring length between the ALU and the DRAM has been shortened as much as possible to increase the speed of memory access.

[0005] The wiring length between the ALU and the DRAM will be described below. One 1-port DRAM and ALU
When the ALU is connected, the connection length of the data line between the DRAM and the ALU can be minimized by designing the ALU according to the wiring pitch of the data line of the DRAM. Specifically, the data IO terminal side of the DRAM and the AL
The data IO terminal side of U is laid out (placed) on a semiconductor substrate.

Next, two DRAs each of one port type are used.
When M (DRAM having a two-bank configuration) is connected to the ALU, A is set in accordance with the arrangement pitch of the data lines of the DRAM.
Even if the LU is designed, the wiring length of the data line is longer than in the case where one DRAM and the ALU are connected as described above.

For example, as shown in FIG. 13, two 16 Mbit DRAMs 101 ₁ and 101 ₂ and an ALU 102
When connecting the door is arranged to direct a DRAM 101 _1, 101 ₂ data IO103 _1, 103 ₂ to the selector 104. The other side of the selector 104 includes the DRAM 1
01 ₁ the distance between the positions the ALU102 so that the shortest.

[0008]

SUMMARY OF THE INVENTION However, ALU
If the distance between 102 to DRAM 101 ₁ is arranged such that the shortest distance between ALU102 the DRAM 101 ₂ is not a minimum. Therefore, there is a problem that the access speed of the relative DRAM101 ₂ is slow, becomes a bottleneck in achieving improved performance of the overall system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a processor system and a storage circuit capable of speeding up memory access.

[0010]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a processor system according to a first aspect of the present invention comprises a plurality of processors arranged in a matrix. A processor system in which a memory module having a memory cell and a processor module performing predetermined processing and accessing the memory module are provided on the same semiconductor substrate, wherein the memory module includes a first column decoder and a first column decoder. , A second column decoder, a plurality of first memory cells connected to a bit line selected by the first column decoder, and a plurality of first memory cells connected to a bit line selected by the second column decoder The memory in which the second memory cells are mixed in the column direction is connected to the first memory cell and the second memory cell. And a plurality of memory blocks arranged in the column direction and a row decoder for driving the word line, wherein the processor module comprises a plurality of processors arranged to face each of the plurality of memory blocks.

In the processor system of the present invention, when performing an operation in each processor, the processor accesses a memory block corresponding to the processor as necessary. At this time, access to the first memory cell is performed by selection of a bit line by a first column decoder, and access to the second memory cell is performed by selection of a bit line by a second column decoder. Done. That is, the access to the first memory cell and the access to the second memory cell
It is performed by the same operation as the conventional access to a different bank. Here, in the present invention, since the first memory cell and the second memory cell are mixed in the column direction, the wiring distance between the first memory cell and the corresponding processor and the second memory cell The wiring distance between the processor and the corresponding processor can be reduced as compared with the related art. As a result, memory access can be speeded up.

Further, in the processor system according to the first aspect of the present invention, preferably, the memory block of the memory module includes the first memory cells and the second memory cells alternately arranged in a column direction. Has been established.

In the processor system according to the first aspect of the present invention, the first memory cell and the second memory cell share a word line.

Further, a processor system according to a first aspect of the present invention is provided between the memory block and a processor corresponding to the memory block, and the processor accesses the first memory cell by the processor. And a second wiring used for data transfer when the processor accesses the second memory cell.

Further, in the processor system according to the first aspect of the present invention, the plurality of processors input and output data between adjacent processors.

Further, the storage circuit according to the first aspect of the present invention comprises:
A storage circuit having a plurality of memory cells arranged in a matrix, comprising: a first column decoder, a second column decoder, and a plurality of memory cells connected to a bit line selected by the first column decoder. A storage area in which a first memory cell and a plurality of second memory cells connected to a bit line selected by the second column decoder are mixed in a column direction; And a row decoder for driving a word line to which the second memory cell is connected.

Further, a processor system according to a second aspect of the present invention includes a memory module having a plurality of memory cells arranged in a matrix, a processor module performing predetermined processing and accessing the memory module. Wherein the memory module includes a plurality of column decoders and a plurality of memory cells connected to bit lines selected by the plurality of column decoders, respectively, in a column direction. A plurality of memory blocks each having a mixed memory and a row decoder for driving a word line to which the memory cells are connected are arranged in a column direction, and the processor module is provided in each of the plurality of memory blocks. A plurality of processors are provided to face each other.

Further, the storage circuit of the present invention is a storage circuit having a plurality of memory cells arranged in a matrix, wherein a plurality of column decoders and a bit line respectively selected by the plurality of column decoders are provided. The memory includes a memory in which a plurality of connected memory cells are mixed in the column direction, and a row decoder that drives a word line to which the memory cells are connected.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a processor according to an embodiment of the present invention will be described. FIG. 1 is a configuration diagram of a processor 1 of the present embodiment. As shown in FIG. 1, the processor 1 has, for example, a memory module 2, a processor module 3, a memory control circuit 4, and a control circuit 5 on a single semiconductor substrate. Here, the processor module 3 has the same wiring pitch (1b) as that of the memory module 2.
The layout width per it is the same).

Hereinafter, each component shown in FIG. 1 will be described. [Memory Module 2] FIG. 2 is a configuration diagram of the memory module 2. As shown in FIG.
Is an address generation circuit 11, a row decoder 1
2, the control circuit 13, m number of memory blocks 14 ₁ to 14
_{has m} . Address generating circuit 11, address signals ADRa from the control circuit 5 shown in FIG. 1, based on adrb, precharge signal Pra, Prb and column address signals CADRa, generates CADRb, these memory blocks 14 ₁ to 14 _m Output to In addition, the address generation circuit 11 generates a row decoder control signal RDCNT based on the address signals ADRa and ADRb from the control circuit 5 shown in FIG. Further, the address generation circuit 11 generates a control signal CNT ₁ based on the address signals ADRa and ADRb from the control circuit 5 shown in FIG.
Output to 3.

The row decoder 12 includes an address generation circuit 1
1 based on the row decoder control signal RDCNT from
Selectively activating word lines WL ₁ to WL _n to (drive).

The control circuit 13 controls the memory block 14 based on a control signal CNT ₁ from the address generation circuit 11.
Generates a control signal IOCNT for controlling ₁ to 14 _m of I (Input) / O (Output ), which memory block 14 ₁
Output to 14 _m .

[0023] FIG. 3 is a configuration diagram of the memory block 14 _1. Memory block 14 ₂ to 14 _m has the same configuration as the memory block 14 _1. As shown in FIG. 3, the memory block 14 _1, leaf 20a ₁ through 20a _8, 2
0b ₁ ~20b _8, having a column decoder 21a, 21b and an input output circuit 22. Leaf 20a ₁ ~20a
_8, 20b _{1 ~20b 8} is a horizontal direction in the drawing (the column direction), toward the right from the left in the drawing, the leaf 20a _1, 2
_{0b 1, 20a 2, 20b 2} , 20a 3, 20b 3, 2
_{0a 4, 20b 4, 20a 5} , 20b 5, 20a 6, 2
0b ₆ , 20a ₇ , 20b ₇ , 20a ₈ , 20b ₈ . That is, the leaf 20a ₁ through 20a ₈ which is controlled by the column decoder 21a, the leaf 20b ₁ to 2, which is controlled by the column decoder 21b
0b ₈ are alternately arranged in the column direction. Also,
As shown in FIG. 3, the leaf 20a ₁ through 20a _8, 20b
Across the _{1 ~20b 8,} downward from 3 Nakagami, the word lines WL ₁ to WL _n are disposed in this order.

[0024] For the leaf 20a ₁ will be explained. The leaf 20a _1, bit lines BL1a, BL1a / are arranged. For example, the cell Q1 is connected to the bit line BL1a.
1a, Q13a, Q15a, ..., Q1 (n-1) a
Are connected to one of the source and the drain of the N-type transistor. The other of the source and the drain of the N-type transistor is grounded via a capacitor. The bit lines BL1a / are connected to the cells Q12a, Q14a, Q16a,.
One of a source and a drain of an N-type transistor constituting each of na is connected. The other of the source and the drain of the N-type transistor is grounded via a capacitor. Cells Q11a, Q12a, Q
13a, Q14a, Q15a, ..., Q1 (n-1)
The gates of the N-type transistors constituting the transistors a and Q1na are connected to the word lines WL1 to WLn, respectively.

[0025] The leaf 20a _1, which is provided further sense amplifier SA1a. Sense amplifier SA1a
Is a precharge signal Pr from the address generation circuit 11.
Based on a, the bit lines BL1a, BL1a / are precharged and the cells Q11a to Q1na are refreshed.

[0026] The leaf 20a _1, further transistor Tr1a, Tr1a / is provided. One of the source and the drain of the transistor Tr1a is connected to the bit line B
L1a, and the other is connected to the column decoder 21a. The gate of the transistor Tr1a is
It is connected to the column decoder 21a via the wiring Y1a. One of a source and a drain of the transistor Tr1a / is connected to the bit line BL1a /, and the other is connected to the column decoder 21a. Further, the gate of the transistor Tr1a / is connected to the column decoder 21a via the wiring Y1a.

The leaves 20a _{2 to} 20a ₈ are the leaves 20
It has the same configuration as a _1.

[0028] Next, a description will be given of leaf 20b _1.
The leaf 20b _1, bit line BL1b, BL1b /
Are arranged. For example, cells Q11b, Q13b, Q15b,..., Q1 (n−
1) One of a source and a drain of an N-type transistor constituting each of b is connected. The other of the source and the drain of the N-type transistor is grounded via a capacitor. Bit line BL1b /
For example, cells Q12b, Q14b, Q16b,.
One of a source and a drain of an N-type transistor constituting each of Q1nb is connected. The other of the source and the drain of the N-type transistor is grounded via a capacitor. Cells Q11b, Q12
b, Q13b, Q14b, Q15b,..., Q1 (n
-1) The gates of the N-type transistors constituting b and Q1nb are connected to word lines WL1 to WLn, respectively.

[0029] The leaf 20b _1, which is provided further sense amplifier SA1b. Sense amplifier SA1b
Is a precharge signal Pr from the address generation circuit 11.
Based on b, the precharge operation of the bit lines BL1b, BL1b / is performed, and the refresh operation of the cells Q11b to Q1nb is performed.

[0030] The leaf 20b _1, further transistor Tr1b, Tr1b / is provided. One of the source and the drain of the transistor Tr1b is connected to the bit line B
L1b, and the other is connected to the column decoder 21b. The gate of the transistor Tr1b is
It is connected to the column decoder 21b via the wiring Y1b. One of a source and a drain of the transistor Tr1b / is connected to the bit line BL1b /, and the other is connected to the column decoder 21b. Further, the gate of the transistor Tr1b / is connected to the column decoder 21b via the wiring Y1b.

The leaves 20b _{2 to} 20b ₈ are the leaves 20
It has the same configuration as the b _1.

The column decoder 21a receives the column address signal CADRa from the address generation circuit 11 shown in FIG.
2 on which the cell to be accessed is arranged based on
And wiring Y1a~Y8a of 0a ₁ through 20a ₈ to a high level, leaf 20a that cell is arranged ₁ through 20a ₈
Transistors Tr1a to Tr8a, Tr1a / to Tr
8a / is turned on. Thus, the bit lines of the leaf 20a ₁ through 20a ₈ to which the cells are arranged BL1a
ＢＬBL8a, BL1a / 〜BL8a / and the column decoder 21a become conductive, and the cell can be accessed.

The column decoder 21b receives the column address signal CADRb from the address generation circuit 11 shown in FIG.
2 on which the cell to be accessed is arranged based on
And wiring Y1b~Y8b of 0b _{1 ~20b 8} to a high level, leaf 20b the cell is arranged _{1 ~20b 8}
Transistors Tr1b to Tr8b, Tr1b / to Tr
8b / is turned on. Thus, the bit lines of the leaf 20b ₁ ~20b ₈ to which the cells are arranged BL1b
ＢＬBL8b, BL1b / 〜BL8b / and the column decoder 21b become conductive, and the cell can be accessed.

The input output circuit 22, based on IOCNT from the control circuit 13 shown in FIG. 2, the leaf 20a ₁ to 2
During the read operation of the cell in 0a _8, the column decoder 2
1a amplifies the voltage level of the bit line BL1a~BL8a corresponding to data read from the cell and reflected on the wiring IO1a by the write operation of the cells of the leaves 20a ₁ through 20a in _8, the voltage level of the wiring IO1a Is reflected on the bit lines BL1a to BL8a. Also, the input / output circuit 22 controls the control signal I from the control circuit 13 shown in FIG.
Based on OCNT, during a read operation of the cell in the leaf 20b ₁ ~20b _8, bit lines BL corresponding to the data read from the cell by the column decoder 21b
Amplifies the voltage level of 1b~BL8b reflected in the wiring IO1a, during the write operation of the cell of the leaf 20b ₁ ~20b in _8, the bit line voltage level of the wiring IO1B BL1
b to BL8b.

[Processor Module 3] FIG. 4 is a configuration diagram of the processor module 3. As shown in FIG. 4, the processor module 3, the control circuit 30 includes a selection circuit 31, 32 and the processor 33 ₁ ~ 33 _m. The control circuit 30 selects the selection signal SE based on the operation control signal OCTL from the control circuit 5 shown in FIG.
It generates L _1, SEL _2, and outputs a selection signal SEL ₁ to the selection circuit 31 outputs the selection signal SEL ₂ to the selection circuit 32. The control circuit 30 based on the operation control signal OCTL from the control circuit 5, the control signal S30 ₁ to S
30 _m , and these are respectively processed by the processors 33 ₁ to 33 ₁ .
Output to 33 _m .

The selection circuit 31, based on the selection signal SEL _1, the processor 33 ₁ terminal IOaL and terminal IO
bL is connected to the terminal GIOa shown in FIG. Selection circuit 32, based on the selection signal SEL _2, the processor 33 _m terminals IOaR and terminal IO of
One of bR is connected to the terminal GIOb shown in FIG.

[0037] The processor 33 ₁ ~ 33 _m, respectively run in parallel a predetermined program and inputs and outputs data between processors mutually adjacent as necessary. For example,
In the case of using the processor system 1 for scientific calculations, the processor 33 ₁ ~ 33 _m performs an operation corresponding to each digit, and outputs to the processor adjacent the data of the carry. In the case of using a processor system 1 to the image processing performs processing of the pixel data corresponding respectively in the processor 33 ₁ ~ 33 _m. The following describes the processor 33 _1. Processor 33 _{2 to} 33 _m
Has the same configuration as the processor 33 _1. However, processor 33 ₂ ~ 33 _m performs access to the memory block 14 ₂ to 14 _m as shown in Figure 2, respectively.

[0038] FIG. 5 is a configuration diagram of a processor 33 _1. Processor 33 ₂ ~ 33 _m is in the same structure as the processor 33 _1. As shown in FIG.
3 ₁ includes a selection circuit 40, CPU 41 and the FIFO circuit 42. The processor 33 ₁ performs the memory block 14 ₁ leaf number in operation to example 8 bits corresponding shown in FIG.

The selection circuit 40 includes a control circuit 30 shown in FIG.
Perform the following processing based on the control signal S30 ₁ from. Selection circuit 40, when the CPU41 performs access to the leaf 20a ₁ through 20a ₈ of the memory block 14 ₁ of the memory module 2 shown in FIGS. 2 and 3, CPU 4
1 and the wiring IO1a connected to the input / output circuit 22 shown in FIG. The selection circuit 40 of the memory module 2 CPU41 is shown in FIGS. 2 and 3 memory block 14 ₁ leaf 20b
When accessing the _{1 ~20b 8,} to the wiring IOb between CPU 41, and a wiring IO1b connected to the input output circuit 22 shown in FIG. 3 in the connected state.

When the CPU 41 inputs / outputs data from / to the outside of the processor system 1 via the external terminal GIOa, the selection circuit 40 connects the wiring IOa to / from the CPU 41 and the selection shown in FIG. The terminal IOaL connected to the circuit 31 is connected. Also, the selection circuit 40
When the CPU 41 performs input / output of data with the outside of the processor system 1 via the external terminal GIOb, the wiring IOb to the CPU 41 and the terminal IObL connected to the selection circuit 31 shown in FIG. And are connected.

The selection circuit 40 is provided by the CPU 41 as shown in FIG.
When performing input and output of data between the processor 33 ₂ shown in a wiring IOa between the CPU 41, terminal IOa
R is connected. Further, the selection circuit 40 includes a CPU
41 when performing input and output of data between the processor 33 ₂ shown in FIG. 4, the wiring IOb between CPU 41,
The terminal IObR is connected.

The CPU41, based on the control signal S30 ₁ from the control circuit 30 shown in FIG. 4 executes the processing according to a predetermined program, if necessary, through the selection circuit 40, a memory shown in FIG. 2 block 14 ₁ inputs and outputs data between the external and the processor 33 ₂ of the processor system 1. In addition, the CPU 41 executes the FIF shown in FIG.
The main memory 6 outside the processor system 1 is accessed via the O circuit 42 and the memory control circuit 4 shown in FIG.

The FIFO circuit 42 based on the control signal S30 ₁ from the control circuit 30 shown in FIG. 4, the input order data from the CPU 41, terminal Da shown in FIGS. 1 and 5
The signal is output to the memory control circuit 4 via the line ta and the wiring d1. Further, the FIFO circuit 42 includes the control circuit 3 shown in FIG.
Based on the control signal S30 ₁ from 0, 1 and 5
The data input from the memory control circuit 4 via the terminal Data shown in FIG.

[Memory control circuit 4] Memory control circuit 4
Based on the control signal CNT ₅ from the control circuit 5, the main memory 6 by the processor module 3 shown in FIG. 1
, Access via the wirings d1 to dm is controlled.

The control circuit 5 generates address signals ADRa and ADRb based on a control signal chipopr input from outside the processor system 1 and outputs them to the memory module 2. Further, the control circuit 5 generates a control signal OCTL based on the control signal chipopr, and outputs this to the processor module 3. Also,
Control circuit 5 based on the control signal Chipopr, generates a control signal CNT _5, and outputs it to the memory control circuit 4.

Hereinafter, an operation example of the processor system 1 will be described. First Operation Example FIG. 6 is a diagram for describing a first operation example of the processor system 1. In the first operation example shown in FIG. 6, the leaf 20 of the memory block 14 ₁ of the memory module 2
reading data from the memory cell Q11a of a _1, performs a calculation by the processor 33 ₁ by using the read data, the leaf 20b ₁ data obtained by the calculation
Is written to the memory cell Q11b. In this case, the word lines WL ₁ shown in FIG. 2 is activated, the memory cells connected to the word line WL _1, i.e. it is possible to simultaneously access a memory cell having the same row address. FIG.
FIG. 7 is a timing chart of the first operation example shown in FIG. 6 at the time of single access. Figure 7 (A) of the reference clock signal waveform, FIG. 7 (B) the memory blocks 14 ₁ to 14 _m of the leaves 20a from the address generating circuit 11 shown in FIG. 2
Waveforms of the precharge signal Pra output to ₁ through 20a _8, FIG. 7 (C) is the control signal R of the word line output from the address generating circuit 11 shown in FIG. 2 to the row decoder 12
Illustrates the timing of DCNT, FIG 7 (D) is a memory block 14 ₁ to 1 from the address generating circuit 11 shown in FIG. 2
FIG. 7E is a timing chart of the column address signal CADRa output to the 4 _m column decoder 21a, FIG. 7E is a timing chart of data transmitted on the wiring IO1a shown in FIGS. 1 and 3, and FIG. The control signal S shown in FIG.
30 ₁ of the timing diagram, FIG. 7 (G) is a timing diagram of a data transmitting line IO1b shown in FIGS. 1 and 3, FIG. 7 (H) is a memory block 14 ₁ to 14 from the address generation circuit 11 shown in FIG. 2 waveforms of the precharge signal Prb output to the leaf 20b ₁ ~20b ₈ of _m, 7
(I) is a timing diagram of a column address signal CADRb output from the address generating circuit 11 shown in FIG. 2 to the column decoder 21b of the memory blocks 14 ₁ to 14 _m.

Hereinafter, the first operation of the processor system 1 will be described with reference to FIG. Clock cycle "1": the address signal ADRa from the control circuit 5 shown in FIG. 1, based on adrb, the memory block 14 ₁ to 1 from the address generating circuit 11 shown in FIG. 2
4 _m of leaf _{20a 1 ~20a 8, 20b 1 ~20b} 8
The precharge signals Pra and Prb output to
It rises to a high level as shown in (B) and (H).
As a result, the leaf 20a ₁ ~20a _8, 20b ₁ ~
Bit line BL1a~BL8a of 20b in _8, BL1a /
~ BL8a /, BL1b ~ BL8b, BL1b / ~ BL
A precharge operation of 8b / is performed. In addition, leaf 2
Access to 0a ₁ through 20a ₈ is the read mode, access to the leaf 20b ₁ ~20b ₈ is controlled to a write mode.

Clock cycle "4": A control signal RDCNT is output from the address generation circuit 11 shown in FIG. 2 to the row decoder 12 based on the address signals ADRa and ADRb from the control circuit 5 shown in FIG. ₁
Is activated.

The clock cycle "10": the address generating circuit 11 shown in FIG. 2, the column decoder 21a of the memory block 14 ₁ shown in FIGS. 2 and 3, the leaf 20
a column address signal C indicating the column address of a ₁
ADRa is output.

Clock cycle "12": In response to a read operation on memory cell Q11a shown in FIG. 3, the potential of wiring IO1a in FIGS. 2 and 3 changes according to the read data. Then, via the wiring IO1a,
Read data is output to the processor 33 ₁ of the processor module 3 shown in FIG.

Clock cycle "13": Processor 3
In 3 _1, based on the control signal S30 _1, lines IO
An operation is performed using the data input via 1a.

[0052] from the address generating circuit 11 shown in FIG. 2, a column decoder 21b of the memory block 14 ₁ shown in FIGS. 2 and 3, the column address signal CADRb indicating a column address of the leaf 20b ₁ is output. Clock cycle "14": from the processor 33 _1, through the wiring IO1B, the memory cell Q11b leaf 20b ₁ shown in FIG. 3, data corresponding to the calculation result is written.

[0053] As can be seen from Figure 7, the data of the operation result of the processor 33 ₁ obtained in clock cycle "13" is written into the memory cell Q11b in the immediately following clock cycle "14". This is because the leaves 20a ₁ and 20b ₁ shown in FIG.
a _1, 20b ₁ processor 33 ₁ shown in FIG. 4 so as to face by disposing the memory cell Q11a, Q11
and b, can be the shortest both the distance between the processor 33 _1, due to the fact that could a time associated with the data transfer to the shortest. In addition,
As shown in FIG. 7, after the column address is designated by the column address signal CADRa, the memory cell Q11
It takes two clock cycles to read data from line a to line IO1a, but as in this embodiment,
When the memory module 2 and the processor module 3 are constructed on the same semiconductor substrate, it can be performed in one clock cycle. Further, in the present embodiment, when performing the read-modify-write, the memory cell Q11a for reading and the memory cell Q11
b and can be because it is connected to the same word line WL _1, once the activation operation of the word line. as a result,
It is possible to reduce power consumption and speed up access.

[0054] In the example described above, the processor 33 _1, is exemplified a so-called 1-term operation for performing an operation using one of the data read from the memory module 2, using two or more data read out from the memory module 2 When the calculation is performed by using the other data,
The register in ₁ is read from the memory module 2 or
Or stored in advance in the processor 33 _1.

The above operation is executed by one series of operations. A series of operations is an operation unit for activating a word line of the memory block 14. Due to the characteristics of the DRAM, different row addresses cannot be accessed simultaneously. Here, in the above-described operation example, an example is shown in which the first row address is accessed, but the present invention is not limited to accessing the first row address. Further, in the above-described operation example, the case where the first column address is accessed is illustrated, but this is not limited as well. Although the read-modify-write is one unit of work, a method of continuously switching column addresses is also conceivable. This is the so-called SDRAM
Burst transfer. Further, in the example described above, data is read from the leaf 20a ₁ also leaf 20
b ₁ to writing the data of the operation results is also possible vice versa. Also, as shown in FIG.
Performs a calculation by the processor 33 ₁ using the read data from the memory cell Q11a in 0a _1, may be written into the memory cell Q21b leaf 20b ₂ not adjacent to the leaf 20a ₁ of the operation result.

[0056] The second operation example FIG. 9 is a timing chart of the burst access of the processor system 1. Clock cycle "10": From the address generation circuit 11 shown in FIG. 2, the memory block 14 shown in FIGS.
₁ of the column decoder 21a, a column address signal CADRa pointing to the column address of the leaf 20a ₁ is output. Clock cycle "11": column address signal CADRa pointing to the column address of the leaf 20a ₂ from the address generating circuit 11 to the column decoder 21a is output.

Clock cycle "12": The potential of the wiring IO1a in FIGS. 2 and 3 changes according to the read data in response to the read operation for the memory cell Q11a shown in FIG. Then, via the wiring IO1a,
Read data is output to the processor 33 ₁ of the processor module 3 shown in FIG. Also, the leaf 20a is sent from the address generation circuit 11 to the column decoder 21a.
Column address signal CA indicating the column address of ₃
DRa is output.

Clock cycle "13": Processor 3
In 3 _1, based on the control signal S30 _1, lines IO
An operation is performed using the data of the memory cell Q11a input via the memory cell 1a. The column address signal CADRa pointing to the column address of the leaf 20a ₄ from the address generating circuit 11 to the column decoder 21a is output. Further, in response to a read operation on memory cell Q12a shown in FIG. 3, the potential of wiring IO1a in FIGS. 2 and 3 changes according to the read data. And
Via the wiring IO1a, read data is output to the processor 33 ₁ of the processor module 3 shown in FIG.

[0059] clock cycle "14": from the address generating circuit 11 shown in FIG. 2, a column decoder 21b of the memory block 14 ₁ shown in FIGS. 2 and 3, the leaf 20
column address signal C indicates the column address of b ₁
ADRb is output. From the processor 33 _1, wiring I
Via O1b, the memory cell Q11b leaf 20b ₁ shown in FIG. 3, data corresponding to the calculation result using the data of the memory cell Q11a is written. Processor 33
In _1, based on the control signal S30 _1, lines IO1
The operation is performed using the data of the memory cell Q12a input through the input terminal a. Further, the memory cell Q13 shown in FIG.
The potential of the wiring IO1a in FIG. 2 and FIG. 3 changes according to the read data in response to the read operation for “a”. Then, via the wiring IO1a, read data is output to the processor 33 ₁ of the processor module 3 shown in FIG.

[0060] clock cycle "15": the address generating circuit 11 shown in FIG. 2, a column decoder 21b of the memory block 14 ₁ shown in FIGS. 2 and 3, the leaf 20
column address signal C indicates the column address of b ₂
ADRb is output. From the processor 33 _1, wiring I
Via O1b, the memory cell Q12b leaf 20b ₂ shown in FIG. 3, data corresponding to the calculation result using the data of the memory cell Q12a is written. Processor 33
In _1, based on the control signal S30 _1, lines IO1
An operation is performed using the data of the memory cell Q13a input through the input terminal a. Further, the memory cell Q14 shown in FIG.
The potential of the wiring IO1a in FIG. 2 and FIG. 3 changes according to the read data in response to the read operation for “a”. Then, via the wiring IO1a, read data is output to the processor 33 ₁ of the processor module 3 shown in FIG.

[0061] clock cycle "16": the address generating circuit 11 shown in FIG. 2, a column decoder 21b of the memory block 14 ₁ shown in FIGS. 2 and 3, the leaf 20
column address signal C indicates the column address of b ₃
ADRb is output. From the processor 33 _1, wiring I
Via O1b, the memory cell Q13b leaf 20b ₁ shown in FIG. 3, data corresponding to the calculation result using the data of the memory cell Q13a is written. Processor 33
In _1, based on the control signal S30 _1, lines IO1
An operation is performed using the data of the memory cell Q14a input through the input terminal a.

[0062] clock cycle "17": the address generating circuit 11 shown in FIG. 2, a column decoder 21b of the memory block 14 ₁ shown in FIGS. 2 and 3, the leaf 20
column address signal C indicates the column address of b ₄
ADRb is output. From the processor 33 _1, wiring I
Via O1b, the memory cell Q14b leaf 20b ₁ shown in FIG. 3, data corresponding to the calculation result using the data of the memory cell Q14a is written.

As described above, according to the processor system 1, the data read operation and the write operation from the processor module 3 can be continuously performed a plurality of times by performing the burst access.

In the above-described read operation, since data has been read up to the bit line in the memory block, the selection of the bit line in the column decoder 21a may be switched.

The processor module 3 shown in FIG.
In inner, a processor 33 ₁ ~ 33 _m of the result of the data terminal IOaL, IObL, IOaR, after shifting between processors via IObR, may be written into the memory module 2.

[0066] In the above embodiment, as shown in FIG. 3, two column decoders 21a to operate independently of each memory block 14 ₁ in to 14 _m, and 21b provided, leaf 20a ₁ through 20a ₈ and leaf 20b ₁ ~20b ₈ and the a case has been exemplified where independently perform access, provided three or more column decoder may be able to independently access the leaf three or more groups. FIG.
FIG. 10 is a diagram for describing a case where three column decoders are provided and three groups of leaves are independently accessed.
As shown in FIG. 10, in the memory block 14 ₁ in to 14 _m, the memory cell Q11a~Q1na controlled by the first column decoder, Q21a～Q2na, ·
.., Q81a to Q8na and memory cells Q11b to Q1nb, Q2 controlled by the second column decoder
1b to Q2nb,..., Q81b to Q8nb, and the third
Cell Q11 controlled by the column decoder of FIG.
c to Q1nc, Q21c to Q2nc,..., Q81c
To Q8nc are sequentially arranged in the column direction.

[0067] Memory block 14 _1-14 shown in FIG. 10
In the configuration of _m, for example, it outputs the data read from the memory cell Q11a and Q11b by controlling the first and second column decoders, the wiring IO1a, the processor 33 ₁ through respectively the IO1B, processor 33
₁ to perform an operation using the data, output the operation result data to the memory module 2 through the wiring IO1c, and control the memory cell Q under the control of the third column decoder.
The so-called three-term operation, which is written in 11c, can be performed at high speed. This is used for the operation in the processor 33 ₁ 2
This is because individual data can be read by one read operation. The data to be read includes leaf data controlled by the first and second column decoders, leaf data controlled by the first and third column decoders, or second and third data.
May be leaf data controlled by the column decoder. Further, the leaves on which writing is performed may be leaves controlled by the first and second column decoders.

[0068] As another example of the operation of the processor system 1 described above, for example, as shown in FIG. 11, the processor 33 ₁ of the operation result of the data leaves 20a ₁ ~
Memory cells Q connected to the word line WL ₁ in 20a in ₈
11a, Q21a, Q31a, Q41a, Q51a, Q
A so-called broadcast operation, that is, writing to 61a, Q71a, and Q81a may be performed. At this time,
The memory cells Q11a, Q21a, Q31a, Q41a,
Q51a, Q61a, Q71a, Q81a, because they are connected to the same word line WL _1, the activation of the word line associated with the write operation may be performed once. Further, the memory cells Q11a, Q21a, Q31a, Q41a, Q51
a, Q61a, Q71a, the writing of data to Q81a, achieved by performing from the processor module 3 via the wiring IO1a the data input to the memory block 14 _1, the switching of the selection of the bit line in order in the column decoder 21a it can.

In the example shown in FIG. 11, the leaf 20a
_{Although the} case where the writing to the memory cells _{1 to} 20a ₈ is performed by broadcast is illustrated, the leaves 20b _{1 to} 20b
To write to the ₈ memory cell of it may be carried out in the broadcast, leaf 20a ₁ ~20a _8, 20b ₁ ~2
Writing to the memory cells of the 0b ₈ may be performed by one broadcast operation.

Hereinafter, effects of the processor system 1 will be described. As shown in FIGS. 1 to 4, the processor system 1
So, by building the memory blocks 14 ₁ to 14 _m in the memory module 2 shown in FIG. 2, so as to face on the same semiconductor substrate to the corresponding processor 33 _to 333 shown in FIG. 4 to be _m, the processor 33 ₁ and ~ 33 _m, the wiring length between the memory cell in which the processor 33 ₁ ~ 33 _m performs access (e.g. wiring IO1a, distance IO1B)
Can be shortened as compared with the related art, and the memory access speed can be increased as compared with the related art. The effect of improving the access speed becomes more remarkable as the capacity of the memory module 2 increases.
FIG. 12 is a diagram for explaining the layout of the processor system 1 of the present embodiment in comparison with the above-described conventional processor system shown in FIG. As shown in FIG. 12, in the processor system 1, the processor 3
3 and ₁ ~ 33 _m, can the layout pattern for the processor 33 ₁ ~ 33 _m is disposed opposite a memory cell to be accessed uniformly in the column direction,
A common layout pattern can be applied irrespective of the capacity of the memory module 2, which facilitates design.

[0071] Further, according to the processor system 1, by enabling the input and output of data between the processor 33 ₁ ~ 33 _m mutually adjacent 4, the memory module 2 with respect to the shift operation of the data No access required. Therefore, the shift operation can be performed at high speed.

Further, according to the processor system 1, as shown in FIG. 12, a memory and a processor can be configured in a bit unit and can be expanded in a scalable manner. In particular, assuming that bits for the horizontal pixels of the monitor display (the number of data lines, which is a repetition amount for each memory block) are assigned to all of one row, 1024 bits in the horizontal direction in the XGA standard, S
It is very convenient for calculation if repetition is performed for 1280 bits in the XGA standard and 720 bits in the NTSC. In this case, it is possible to perform the calculation for the horizontal direction (horizontal pixels) collectively. The calculation is typically performed by the SIMD method, but is not limited to the SIMD method.

[0073]

As described above, according to the present invention,
It is possible to provide a processor system and a storage circuit which can speed up memory access.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a processor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory module shown in FIG. 1;

FIG. 3 is a configuration diagram of a memory block shown in FIG. 2;

FIG. 4 is a configuration diagram of a processor module shown in FIG. 1;

FIG. 5 is a configuration diagram of a processor shown in FIG. 4;

FIG. 6 is a diagram for explaining a first operation example of the processor system according to the embodiment of the present invention;

FIG. 7 is a timing chart of the first operation example shown in FIG. 6 at the time of single access.

FIG. 8 is a diagram for explaining an operation example of the processor system according to the embodiment of the present invention;

FIG. 9 is a timing chart at the time of burst access of the processor system of the present invention.

FIG. 10 shows three column decoders provided.
FIG. 7 is a diagram for describing a processor system according to an embodiment of the present invention when independently accessing one group of leaves.

FIG. 11 is a diagram for explaining a broadcast operation of the processor system according to the embodiment of the present invention;

FIG. 12 is a diagram for explaining a layout of the processor system according to the embodiment of the present invention;

FIG. 13 is a configuration diagram of a conventional processor system.

[Explanation of symbols]

1. Processor system 2. Memory module 3.
Processor module, 4 ... memory control circuit, 11 ... address generator, 12 ... row decoder, 13 ... control circuit, 14 ₁ to 14 _m ... memory blocks, 20a ₁ to 20
a _8, 20b ₁ ~20b ₈ ... leaf, 21a, 21b ...
Column decoder, 22 ... input output circuit, 30 ... control circuit, 31, 32 ... selection circuit, 33 ₁ ~ 33 _m ... Processor

Claims (11)

[Claims] 1. A processor system in which a memory module having a plurality of memory cells arranged in a matrix and a processor module performing predetermined processing and accessing the memory module are provided on one semiconductor substrate. A first column decoder; a second column decoder; a plurality of first memory cells connected to a bit line selected by the first column decoder; and a second column. A memory in which a plurality of second memory cells connected to a bit line selected by a decoder are mixed in a column direction; and a word line to which the first memory cell and the second memory cell are connected. A plurality of memory blocks having a row decoder to be driven are arranged in a column direction, and the processor module , Processor system having a plurality of processors arranged to face each of the plurality of memory blocks. 2. The processor system according to claim 1, wherein said memory block of said memory module has said first memory cells and said second memory cells alternately arranged in a column direction. 3. The processor system according to claim 1, wherein said first memory cell and said second memory cell share a word line. 4. A first wiring disposed between the memory block and a processor corresponding to the memory block, the first wiring being used for data transfer when the processor accesses the first memory cell. 2. The processor system according to claim 1, further comprising: a second wiring used for data transfer when the processor accesses the second memory cell. 5. The processor system according to claim 1, wherein said plurality of processors input and output data between adjacent processors. 6. The processor according to claim 1, wherein said processor performs a predetermined operation using data read from said first memory cell of a corresponding memory block, and writes data obtained by said operation to said second memory cell. 2. The processor system according to claim 1. 7. The processor system according to claim 6, wherein said processor reads data from said first memory cell and writes data to said second memory cell in a burst manner. 8. A storage circuit having a plurality of memory cells arranged in a matrix, comprising: a first column decoder; a second column decoder; and a bit line selected by the first column decoder. A storage area in which a plurality of first memory cells connected to the bit line and a plurality of second memory cells connected to the bit line selected by the second column decoder are mixed in the column direction; A storage circuit having a row decoder that drives a word line to which a first memory cell and the second memory cell are connected. 9. The storage circuit according to claim 8, wherein said first memory cells and said second memory cells are alternately arranged in a column direction. 10. A memory module having a plurality of memory cells arranged in a matrix, performing a predetermined process,
In a processor system in which a processor module for accessing the memory module is provided on one semiconductor substrate, the memory module is connected to a plurality of column decoders and bit lines selected by the plurality of column decoders, respectively. A plurality of memory blocks each having a memory in which a plurality of memory cells are mixed in a column direction and a row decoder driving a word line to which the memory cells are connected are arranged in a column direction. And a processor system having a plurality of processors provided to face the plurality of memory blocks, respectively. 11. A storage circuit having a plurality of memory cells arranged in a matrix, comprising: a plurality of column decoders; and a plurality of memory cells connected to bit lines respectively selected by the plurality of column decoders. A memory circuit having a memory mixed in different directions and a row decoder for driving a word line to which the memory cell is connected.