JP2001180042A - Optical writing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically execute the operation of restraining a noise electric wave radiation synchronous with a system clock only when it is intense. SOLUTION: This device comprises a clock oscillator 14 and a frequency divider 30 for dividing the clock thereof and providing the same to a driver 9 for driving a motor 10 of a rotary polarizer; an output buffer 5 for temporarily storing image data to be provided to a driver 7 for driving a light source 8 for outputting a laser beam to the rotary polarizer; an input buffer 2 for temporarily storing the image data provided from the host; gate processors 3, 4, 12, 13 for limiting the image data to be provided from the buffer 2 to the output buffer 5; and signal generating means 40, 50 for generating a frequency fluctuation clock Sc and providing the same to the output buffer 5, the input buffer 2, and the gate processors as a data transfer synchronous signal; wherein the signal generating means 40, 50 include mode switches 51, 55 for generating the frequency fluctuation clock Sc at the time of setting the fluctuation mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical writing apparatus for electrophotography, and more particularly to an optical writing control apparatus for controlling the operation of the optical writing apparatus. This device is, for example, a copying machine,
Used for printer or facsimile.

[0002]

2. Description of the Related Art FIG. 3 shows an outline of a mechanism of an optical writing apparatus according to one embodiment. The optical writing device includes an LD (laser diode) unit 8, a first cylinder lens 15, a first mirror 16, an imaging lens 17, a disk type motor 10,
Accordingly, the polygon mirror 18 is rotated in the direction of arrow A.
And an exposure system comprising a second mirror 20 and a second cylinder lens 21.
There is a line synchronization signal generation system including a mirror 24, a condenser lens 61 including a cylinder lens, and a synchronization sensor 62 including a light receiving element. The LD unit 8 has a laser diode (hereinafter, referred to as “LD”) and a collimator lens that converts a divergent beam emitted from the LD into a parallel light beam. The first cylinder lens 15 shapes the parallel light beam emitted from the LD unit 8 in the sub-scanning direction on the photosensitive drum 22, and the imaging lens 17 converts the parallel light reflected by the first mirror 16 into a convergent beam. And the light is incident on the mirror surface 19 of the polygon mirror 18. The polygon mirror 18 is an R-polygon mirror formed by curving each mirror surface 19, and is a post-object type that does not use an fθ lens conventionally disposed between the second mirror 20 (after converting the light beam to convergent light). (A type in which a deflector is arranged). The second mirror 20 reflects the beam (scanning beam) reflected and deflected by the rotating polarizer toward the photosensitive drum 22. The scanning beam reflected by the second mirror 20 passes through the second cylinder lens 21 and forms an image as a sharp spot on the main scanning line 23 on the photosensitive drum 22.

A third mirror 24 is arranged outside the scanning area on the photosensitive drum 22 by the light beam reflected by the rotating polarizer, and reflects the incident light beam toward the synchronous sensor 11 side. The light beam reflected by the third mirror 24 and condensed by the condensing lens 25 is received by a light receiving element such as a photodiode constituting the synchronous sensor 11, for example.
It is converted into a synchronization signal for keeping the scanning start position constant.

The image data written on the photoconductor 22 is
After being once stored in the input buffer 2 shown in FIG. The gate signal is a write unit (6 to 11)
Is generated by the gate signal generator 4 on the basis of the values of the main scanning counter 13 and the sub-scanning counter 12 operated by the signal from the synchronous sensor 11 and preset values such as the paper size set in advance. This gate signal is sent to gate processing 3,
The portion of the image data that is actually written on the photoconductor 22 is extracted by the gate signal and sent to the output buffer 5. These series of data processing are performed by OSC (oscillator) 1
4 is performed in synchronization with a system clock generated based on the clock pulse generated in step 4. Writing to the output buffer 5 is also performed in synchronization with this clock. This clock is also divided and used as a clock for driving the polygon motor 10.

On the other hand, the writing section (6 to 11) generates a clock corresponding to the writing speed (scanning speed) of the rotating polarizer by its internal writing clock generator 6, and synchronizes with this clock to output clock 5 Image data from the laser driver 7
And light the LD8.

The photosensitive member 23 shown in FIG. 1 uniformly charges the photosensitive member, irradiates the charged surface with light corresponding to an image to form an electrostatic latent image, and develops the electrostatic latent image with a developer. The photosensitive member of the electrophotographic image forming unit that forms a toner image and transfers and fixes the toner image to a sheet, and the scanning beam of the above-described rotating polarizer forms an electrostatic latent image. In FIG. 1, elements used in a process before forming an electrostatic latent image and a process after forming an electrostatic latent image are omitted.

[0007]

The rotation of the polygon mirror 18 is fast, so that the time (one line) of the repetitive beam scanning 23 of the photosensitive member 22 is extremely short. The image data for the line length is read from the output buffer 5 and supplied to the laser driver 7, and the image data of the next line is read from the input buffer 2 through the gate processing 3 and written to the output buffer 5. One line is generally treated as a pixel column of 2000 or a multiple thereof, and a pixel separation signal, that is, a pixel synchronization signal is generated by a write clock generator 6 and supplied to the output buffer 5 as a read clock, and is synchronized with this clock. Then, image data is read from the output buffer 5 and supplied to the laser driver 7. Therefore, the frequency of the clock is extremely high. The time of one beam scan 23 is constant, and the read clock generated by the write clock generator 6 has a constant frequency. It is necessary to write the image data for one line next to the line currently being output to the output buffer 5 within the time of one beam scan 23, so that the system clock Sc supplied to the output buffer 5 as a write clock Is
This frequency is as high as the frequency of the read clock generated by clock generation 6.

High frequency clocks cause radio emissions (noise). Although the radio wave emission level by the read clock and the write clock itself is low, the image data is switched by the input buffer 2, the gate processing 3, and the output buffer 5 in synchronization with, for example, the write clock (system clock Sc). , An image processing circuit (IP) (not shown) for supplying image data to the input buffer 2.
Also in U), since image processing is performed in synchronization with the system clock Sc, radio wave radiation (noise) due to these is performed.
As a whole, radio wave radiation (noise) synchronized with the system clock Sc increases.

A first object of the present invention is to suppress this kind of radio wave radiation (noise), and a second object is to enable this only when necessary. The third purpose is to do.

[0010]

Means for Solving the Problems (1) A first set of clock generating means (6/14) for generating a clock having a constant frequency for controlling portions (7, 9) requiring a constant processing speed. , 30)
And a second clock (Sc) for controlling the other parts
And a second set of clock generating means (30, 40, 50) that generates one of a fluctuation mode in which the oscillation frequency fluctuates within a preset range and a constant mode in which the oscillation frequency is constant, and a specific condition or timing. And a means (1) for setting the second set of clock generating means to the fluctuation mode.

For easy understanding 2, the reference numerals of the corresponding elements or corresponding elements in the embodiment shown in the drawings and described later are added for reference in the parentheses. The same applies to the following.

According to this, the second set of clock generating means is provided.
When (30,40,50) is set to the fluctuation mode, the second clock
The frequency of (Sc) fluctuates within a preset range. Radio wave radiation (noise) synchronized with the second clock (Sc)
Is similarly varied, the electric field strength of the radio wave radiation is apparently low, averaged within the variation range. That is, for example, the radio wave emission peak when the frequency indicated by the dotted line in FIG. 2B is constant spreads over the frequency fluctuation range as indicated by the solid line, and the level of radio wave emission (noise) decreases.

Even if the second clock (Sc) is generated, in the case of electrical processing synchronized with the second clock (Sc), for example, in a standby state where image data transfer is not performed, radio wave radiation synchronized with the second clock (Sc) is performed. (Noise) is low, and it is necessary to generate the second clock (Sc) without transferring image data in the warm-up, adjustment, and inspection of the device. When the clock (Sc) is oscillating
Difficult to do (if the frequency fluctuates). Therefore, at this time, the second set of clock generating means (30, 40, 50) is set to the constant mode to keep the frequency of the second clock (Sc) constant. In this way, unnecessary radiation countermeasures can be taken finely when necessary.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (2) The setting means (1) sets a fluctuation mode when the output of a DC power supply (26) of an optical writing device exceeds a specific value. When electric processing synchronized with the second clock (Sc) is actively performed and radio wave emission (noise) synchronized with the second clock (Sc) is large, for example, image data transfer and image formation are performed. The power consumption of the device is large. In this embodiment, this state is automatically detected based on the output of the DC power supply (26). As a result, the second set of clock generation means (3
Switching between the constant mode and the fluctuation mode (0, 40, 50) can be realized by simple control.

(3) The setting means (1) sets the fluctuation mode during a period from the start to the end of the operation of the device for optical writing. When electric processing synchronized with the second clock (Sc) is actively performed and radio wave radiation (noise) synchronized with the second clock (Sc) is large, for example, image data transfer and image formation are performed. . In this embodiment, this state is automatically detected based on the start and end of the operation of the device for optical writing. Thus, switching between the constant mode and the fluctuation mode of the second set of clock generation means (30, 40, 50) can be realized by simple control.

(4) A clock pulse oscillator (14) and a motor driver (9) for dividing the clock pulse generated by the clock pulse oscillator and for rotating and driving the electric motor (10) of the rotary deflector.
Frequency divider (30) to be supplied to a laser deflector; output buffer (5) for temporarily holding image data to be supplied to a laser driver (7) for driving a light source (8) for emitting a laser beam to a rotary deflector; Input buffer for temporarily storing image data
(2); a gate processing means (3, 4, 12, 1) for limiting image data supplied from the input buffer (2) to the output buffer (5).
3); and a clock whose frequency fluctuates within the set range (S
c) to generate the output buffer (5) and the input buffer (2).
An optical writing control device comprising: synchronizing signal generating means (40, 50) for providing the data to the gate processing means (3, 4, 12, 13) as a synchronizing signal for data transfer.

(5) The synchronizing signal generating means (40, 50)
A swing signal generator (40) that generates a signal whose level fluctuates at a lower frequency than the clock (Sc), and a frequency modulator (50) that generates the clock (Sc) having a frequency corresponding to the level of the fluctuating signal )including.

(6) The swing signal generator (40) is an integration circuit (40) for integrating the frequency-divided pulse generated by the frequency divider (30).
And the frequency modulator (50) includes a voltage-controlled frequency variable oscillator (54) that generates the clock (Sc) having a frequency corresponding to the integration voltage of the integration circuit (40).

(7) The frequency modulator (50) is an integrating circuit.
Means for synthesizing DC voltage (V2) with integrated voltage (V1) of (40) (52)
And the voltage-controlled frequency variable oscillator (54) generates the clock (Sc) having a frequency corresponding to the synthesized voltage (V2-V1).

(8) The synchronizing signal generating means (40, 50)
A clock (Sc) that includes mode switching means (51, 55) and that fluctuates in frequency within the setting range when it is set to the fluctuation mode
The optical writing control device according to the above (4), which generates a clock (Sc) having a set constant frequency when the constant mode is set.

(9) The optical writing device further comprises the mode switching means (51, 51) while the output of the power supply of the device exceeds a set value.
55. The optical writing control device according to (8), further comprising control means (1) for setting 55) to the variable mode.

(10) The optical writing apparatus further includes a control means (1) for setting the mode switching means (51, 55) to the variable mode from the time the image forming instruction is given to the apparatus until the end. The optical writing control device according to (8), further comprising:

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The clock pulse from the clock pulse oscillator (OSC) 14 is frequency-divided by the frequency divider 30 and used as the clock pulse for driving the polygon motor 10 as in the conventional case. However, in order to use the frequency divider 30 also for controlling the frequency modulation, in this embodiment, the frequency divider 30 uses the first counter 31 and the second counter 32 to change the clock pulse of the OSC 14 in two stages. The frequency is divided. When the first counter 31 counts clock pulses of the OSC 14 up to the first set value of the preset register 33, it generates a first carry signal. That is, the first counter 3
1 repeatedly generates a first carry signal with the product of the OSC 14 clock pulse cycle and the first set value as one cycle. The second counter 32 counts up the first carry signal, and generates a second carry signal every time the second carry value counts up to the second set value of the preset register 33. The second carry signal is provided to the motor driver 9 as a motor drive synchronization signal.

On the other hand, since the first carry signal triggers the flip-flop 34 to invert, the output of the flip-flop 34 has a duty cycle of twice the product of the clock pulse cycle of the OSC 14 and the first set value. % Pulse and applied to the integration circuit 40. By doing so, there is no need to separately provide a pulse oscillator for modulation, and it is possible to suppress an increase in cost.

As shown in FIG. 2A, the integration circuit 40
(V1) rises in the high level H section of the output pulse of the flip-flop 34 and drops in the next low level L section, and becomes a triangular wave, that is, a swing voltage that repeats this. The level of the integrated voltage is adjusted to V1 by the variable resistor 44 and applied to the analog switch 51 of the frequency modulator 50.

When the switch driver 55 turns on the analog switch 51 in the frequency modulator 50, the swing voltage V1 is applied to one input terminal of the operational amplifier 52. The operational amplifier 52 synthesizes the swing voltage V1 with the set voltage V2 applied to the other input terminal, generates a synthesized voltage having a level of (V2-V1), and controls the voltage-controlled frequency variable oscillator 54 to control the voltage. Applied as a voltage. Analog switch 5
1 is off, the operational amplifier 52 outputs the set voltage V2
A voltage that is substantially equal to
Is applied as a control voltage.

The voltage controlled frequency variable oscillator 54 generates a pulse having a frequency proportional to the voltage applied by the operational amplifier 52. This pulse is supplied as a system clock Sc to the input buffer 2, the gate processing 3, the output buffer 5, and the main scanning counter 13, and to an upstream device (image processing unit IPU (not shown)) that supplies image data to the present embodiment. It is output as a system clock (image data reading synchronization signal) on the device side.

The output of the integration circuit 40 is adjusted to V1 by the variable resistor 44 to determine the frequency variation F1. On the other hand, the variable resistor 53 of the frequency modulator 50 is for adjusting the offset, and in this embodiment, determines the upper limit F2 of the variable frequency. The ratio of F1 to F2 depends on how much operating margin the system has. In some cases, up to about 50% is possible, but generally about 20% or less. If this setting is too large, a timing error will occur and the system will not operate.

By modulating (F1) the system clock Sc with the low frequency voltage V1 as described above, (b) of FIG.
As shown in (2), the electric field intensity caused by the clock generated at the specific frequency (F2) is spread (spectrum spread) to the surrounding frequency, and the conventional peak portion intensity is reduced. However, since this function does not reduce (rather increases) the entire radiated power, it is preferable to perform this function only when diffusion is necessary, for example, when the peak of the electric field strength synchronized with the system clock Sc is high while the machine is operating.

Therefore, in this embodiment, as described above, the analog switch 51 is inserted into the transmission line of the swing voltage V1, and the system clock Sc is set in the set frequency range F1 (V1
(Corresponding value) and a constant mode in which the system clock Sc is fixed at the set frequency F2 (corresponding to V2).

In the embodiment shown in FIG. 1, various parts of the image forming unit incorporating the optical writing device of the embodiment are provided with various DCs.
Load detection circuit 2 provided in power supply circuit 26 for supplying voltage
The system controller 1 of the optical writing device checks whether the detected load of No. 7 is higher than the load corresponding to the operation state of executing the image data transfer using the threshold Th,
If so, a switch-on instruction signal is given to the switch driver 55, and a switch-off signal is given when the load is low.
This relationship is shown in FIG.

In another embodiment, the system controller 1 of the optical writing device operates the switch in response to an image forming start command (print start) given to an image forming unit in which the optical writing device is incorporated. A switch-on instruction signal is given to the driver 55, and at the end of the image forming cycle (end of optical writing), the switch driver 55 is instructed to switch off. This relationship is shown in FIG.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention.

2A is a time chart showing input / output signals of an integration circuit 40 shown in FIG. 1, and FIG. 2B is an electric field intensity (noise level) generated in synchronization with a system clock Sc.
FIG. 1C is a time chart showing the timing at which the controller 1 shown in FIG. 1 turns on the analog switch 51, and FIG. 1D is a time chart showing the controller 1 of another embodiment. 5 is a time chart showing a timing at which a switch 51 is turned on.

FIG. 3 is a perspective view showing an outline of a mechanism in which optical writing is controlled by the embodiment shown in FIG. 1;

[Explanation of symbols]

8: LD unit 14: Clock pulse oscillator 15: First cylinder lens 16: First lens 17: Imaging lens 18: Polygon mirror 19: Mirror surface 20: Second mirror 21: Second cylinder lens 22: Photoconductor drum 23 : Main scanning line 24: Third mirror 25: Condensing lens 34: Flip-flop 41: Amplifier 51: Analog switch 52: Operational amplifier 54: Voltage controlled variable frequency oscillator 55: Switch driver

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) 9A001 F-term (Reference) 2C362 BA33 BA34 DA41 EA11 EA25 2H027 DA03 DA18 DA32 ED04 ED06 EE01 EE02 EF06 EF09 EF15 JA20 JB30 JC05 JC16 JC18 2H045 AA01 BA02 CA88 DA41 5C072 AA03 BA11 HA02 HA13 HB16 UA11 UA14 XA01 XA05 5C074 AA01 BB03 CC22 DD13 9A001 BB04 HH34 KK42

Claims (3)

[Claims] 1. A first set of clock generating means for generating a clock having a constant frequency for controlling a portion requiring a constant processing speed, and a second clock for controlling other portions. A second set of clock generating means for generating one of a fluctuation mode in which the oscillation frequency fluctuates within a preset range and a constant mode in which the oscillation frequency is constant; and a second set of clock generating means under a specific condition or timing. An optical writing control device comprising: 2. The optical writing control device according to claim 1, wherein said setting means sets a fluctuation mode when an output of a DC power supply of the optical writing device exceeds a specific value. 3. The optical writing control device according to claim 1, wherein said setting means sets the fluctuation mode during a period from the start to the end of the device operation for optical writing.