JP2001177408A - Pipeline a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a pipeline A/D(analog/digital) converter that can be realized with a reduced circuit scale. SOLUTION: The pipeline A/D converter is provided with a pipeline A/D conversion means consisting of a plurality of pipeline stages connected in series and an error collection means that applies pipeline processing to digital data while correcting an error of the digital data from each pipeline stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a pipeline A /
The present invention relates to a D converter, and more particularly, to a pipeline A / D converter capable of reducing a circuit scale.

[0002]

2. Description of the Related Art A conventional pipeline A / D converter quantizes an input signal by an A / D converter having a low resolution of 1 bit or the like, and subtracts a quantized analog value from the input signal to obtain an appropriate value. The A / D converter is constituted by connecting a plurality of pipeline stages for amplifying and outputting the amplified stage to the subsequent stage.

FIG. 4 is a block diagram showing an example of such a conventional 8-bit pipeline A / D converter. In FIG. 4, 1 is a 1.5-bit A / D converter, 2 is a 1.5-bit D / A converter, 3 is a subtractor, and 4 is a gain of 2.
Double amplifiers, 5, 6, 7, 8, 9, 10 and 11 are storage circuits for storing 2-bit data for 7 to 1 cycle, 100 is an analog input signal, and 101 is a digital output signal.

[0004] Also, 1 to 4 are pipeline stages 50.
a, 50b, 50c, 50d, 50e, 50f
And 50g are pipeline stages having the same circuit configuration as the pipeline stage 50a, and 50a to 50g constitute pipeline A / D means 51. In addition, 5
Reference numeral 2 denotes an operation means, and 5 to 11 and 52 constitute an error correction means 53.

The analog input signal 100 is connected to the input terminal of the A / D converter 1 and the addition input terminal of the subtractor 3 constituting the pipeline stage 50a, and the 2-bit output of the A / D converter 1 is stored in a storage circuit. 5 and connected to the digital input terminal of the D / A converter 2. D
The output of the / A converter 2 is connected to the subtraction input terminal of the subtractor 3, and the output of the subtractor 3 is connected to the amplifier 4.

Similarly, the output of pipeline stage 50a is connected to pipeline stage 50b, and the output of pipeline stage 50b is connected to pipeline stage 50c.
And the output of the pipeline stage 50c is connected to the pipeline stage 50d.

The output of the pipeline stage 50d is connected to the pipeline stage 50e, and the output of the pipeline stage 50e is connected to the pipeline stage 50e.
f, and the output of the pipeline stage 50f is connected to the pipeline stage 50g.

The pipeline stages 50b, 50
The 2-bit output of each of c, 50d, 50e, 50f and 50g is stored in a storage circuit 6, 7, 8, 9, 10, and 1, respectively.
1 and the outputs of the storage circuits 5 to 11
Is connected to the digital output signal 101.
Is output.

Here, the operation of the conventional example shown in FIG.
This will be described with reference to FIGS. 6, 7, 8, 9, 10, and 11. FIG. FIG. 5 is a block diagram showing an example of pipeline A / D means constituted by three pipeline stages for simplicity of description, and FIG. 6 is a table showing input / output of a 1.5-bit A / D converter. , FIG. 7 is a table showing the input / output of the 1.5-bit D / A converter, FIG. 8 is an explanatory diagram for explaining the operation in each pipeline stage, and FIG. 9 is an explanatory diagram for showing a specific example of error correction. 10 is a timing chart for explaining the operation of the conventional example shown in FIG. 4, and FIG. 11 is an explanatory diagram for explaining the operation of the conventional example shown in FIG.

In FIG. 5, reference numeral 100 designates the same reference numeral as in FIG. 4, wherein 1a, 1b and 1c are 1.5-bit A / D converters, and 2a, 2b and 2c are 1.5-bit D / A converters. , 3a, 3b and 3c are subtractors, 4a, 4b and 4c
Is an amplifier having twice the gain.

The 1.5-bit A / D converters 1a to 1c output 2-bit codes based on two threshold voltages.
For example, the full span of the analog input signal 100 is set to “F
When “S” is set, “−FS / 8” and “+ FS / 8” are set as threshold voltages.

The 1.5-bit A / D converter 1a
The input and output of .about.1c have the relationship shown in FIG. Change the input signal to "
Vin ”, a 2-bit code“ 00 (= 0) ”and“ −F when “−FS ≦ Vin <−FS / 8” are satisfied.
In the case of S / 8 ≦ Vin <+ FS / 8 ”, the 2-bit code“ 01 (= 1) ”is replaced with“ + FS / 8 ≦ Vin <+ F
In the case of S ", a 2-bit code" 10 (= 2) "is output.

On the other hand, 1.5-bit D / A converters 2a-2
c has the relationship shown in FIG. 7, and the 2-bit input code is "
00 (= 0) ", a voltage of" -FS / 4 "is output, and when the 2-bit input code is" 01 (= 1) ", a voltage of" 0 "is output and 2 bits Input code is "1"
In the case of "0 (= 2)", a voltage of "+ FS / 4" is output.

Here, as shown by "PR01" in FIG. 8, the analog input signal 100 is converted to a full span (-FS / 2 to + FS / 2).
FS / 2), the output code of the A / D converter 1a of the first pipeline stage is switched at the threshold voltage “± FS / 8”, and “A / D converter 1a” in FIG.
DC01 ″ (however, in FIG. 8, the value is represented by a decimal number instead of a 2-bit code).

At this time, the output of the D / A converter 2a changes according to the table shown in FIG. That is, the input code is “0”
(= 00) ”,“ −FS / 4 ”is output, so the subtractor 3 a adds“ FS ”to the analog input signal 100.
/ 4 "is added, and" 0 "is output in the area where the input code is" 1 (= 01) ". Therefore," 0 "is added to the analog input signal 100 by the subtractor 3a, and the input code is" 2 ". (= 10) ”,“ + FS / 4 ”is output, so that the analog input signal 100
Is subtracted from "FS / 4".

Since the output of the subtractor 3a is doubled by the amplifier 4a, the output signal of the amplifier 4a is
As shown in the middle “PR02”. For example, "D" in FIG.
In a region where the input code indicated by C01 is “0 (= 00)”, a signal obtained by adding “FS / 4” to the analog input signal 100 and doubling it is obtained.

Similarly, the output code of the A / D converter 1b of the second pipeline stage is switched at the threshold voltage "± FS / 8", and the output code is changed to the value shown as "DC02" in FIG. Become.

The output of the amplifier 4a indicated by "PR02" in FIG. 8 is applied to the D / A converter 2b according to the table shown in FIG.
Is subtracted and doubled by the amplifier 3b, so that the output signal of the amplifier 4b becomes as shown by "PR03" in FIG. For example, if the input code shown in “DC02” in FIG.
0 (= 00) ", the output of the amplifier 4a is" FS /
4 "is added to form a doubled signal.

Finally, the output code of the A / D converter 1c of the third pipeline stage also switches at the threshold voltage "± FS / 8", and the output code is changed to the value shown as "DC03" in FIG. Become.

Further, error correction will be described. In the vicinity of the timing indicated by “PT01” in FIG. 8, the output of the A / D converter 1b changes from “10 (= 2)” to “00”.
(= 0) ". That is, in FIG.
In the vicinity of PT01 ", output codes as shown in (1) and (2) in FIG. 9 can be obtained.

As shown in FIG. 9 (1), the output codes of the first to third pipeline stages are binary "1".
If the bits are 0, 00, and 01, the A / D conversion of "1001 (= 9)" is performed by shifting the upper bit one bit to the left (double) and adding it to the lower bit. The results are getting.

On the other hand, as shown in (2) of FIG. 9, the output codes of the first to third pipeline stages are binary "0".
Even in the case of 1 "," 10 "and" 01 ", the upper bit is shifted to the left by one bit (doubled) and added to the lower bit, so that" 1001 (= 9) "is obtained (1).
A / D conversion results similar to the above are obtained.

Such error correction corrects code switching even in the vicinity of "PT01" in FIG.

As a result, the code obtained in the three pipeline stages is error-corrected to
A / D conversion result of bits can be obtained. That is, an A / D converter having "the number of pipeline stages + 1" bit resolution can be realized.

However, in practice, it is necessary to store the output codes from the respective pipeline stages sequentially, and perform the error correction at the same timing.

That is, as shown in FIG. 10, a new code is sequentially output from each pipeline stage, so that codes for 7 to 1 cycle are stored by the storage circuits 5 to 11, or 7 to 1 cycle. By delaying,
A code that matches the timing can be input to the arithmetic means 52.

In FIG. 10, symbols such as "DU7"
"DU7" indicates the upper bit of the first pipeline stage, and "DL1" indicates the lower bit of the seventh pipeline stage.

For example, in FIG. 10, "*** _ 1 (*
** is an arbitrary character string such as DU7).
0, the storage circuits 5 to 11 at the timing indicated by “PT11”.
As shown in FIG. 11, the arithmetic means 52 shifts the upper bit of each pipeline stage one bit to the left by one bit (doubles) and adds it to the lower bit as shown in FIG. As a result, "AD7
... AD0 ″ as an 8-bit A / D conversion result.

[0029]

However, as can be seen from FIG. 10, in the conventional pipeline A / D converter, data must be stored until data necessary for error correction is prepared. However, there is a problem that the amount of data to be processed increases and the circuit scale increases.

In addition, there is another problem that the error correction is performed at once after the necessary data has been collected, the circuit scale is large, and the circuit is not suitable for high-speed operation. For example, in the conventional example shown in FIG. 4, an adder for adding 7 bits and 7 bits of data is required to perform error correction. Therefore, an object of the present invention is to realize a pipeline A / D converter capable of reducing the circuit scale.

[0031]

In order to achieve the above object, according to a first aspect of the present invention, there is provided a pipeline A / D converter comprising a plurality of pipeline stages connected in series. Pipeline A /
D means and error correction means for performing error correction of digital data from each of the pipeline stages and obtaining an A / D conversion result.
The circuit scale of the storage circuit can be reduced.

According to a second aspect of the present invention, in the pipeline A / D converter according to the first aspect, the pipeline stage converts the input signal into a digital signal by a 1.5-bit A / D converter. , A 1.5-bit D / A converter for converting the output of the A / D converter into an analog signal, a subtractor for subtracting the output of the D / A converter from the input signal, and the subtractor And an amplifier that amplifies and outputs the output of the storage circuit, it is possible to reduce the circuit scale of the storage circuit.

According to a third aspect of the present invention, in the pipeline A / D converter according to the first aspect, the error correction means stores digital data from the first pipeline stage. 1 and a lower bit of the first pipeline stage in the output of the storage circuit and an upper bit of the second pipeline stage to add a carry from the lower bit to the first pipeline stage. A digital adder circuit for adding to the upper bits of the second pipeline stage; and a second storage circuit for adding the lower bits of the second pipeline stage to the output of the digital adder circuit as the least significant bits for storage. With this configuration, the circuit scale of the storage circuit can be reduced.

According to a fourth aspect of the present invention, in the pipeline A / D converter according to the third aspect of the present invention, the storage circuit is constituted by a D-type flip-flop circuit, so that the circuit scale of the storage circuit is increased. Can be reduced.

According to a fifth aspect of the present invention, in the pipeline A / D converter according to the third aspect of the present invention, the digital adder circuit comprises a half adder and an AND circuit of an inverted output for performing a carry process. By being composed,
The circuit scale of the storage circuit can be reduced.

According to a sixth aspect of the present invention, in the pipeline A / D converter according to the fifth aspect, the half adder comprises an exclusive OR circuit and an exclusive OR circuit having an inverted output. Accordingly, the circuit scale of the storage circuit can be reduced.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a pipeline A / D converter according to the present invention.

In FIG. 1, 1-4, 50a-50g, 5
1 and 100 have the same reference numerals as in FIG.
4, 16, 18, 20, 22, and 24 are storage circuits for storing 2-bit to 8-bit data, and 13, 15, 17, 1
9, 21 and 23 are digital adders for adding the multi-bit data and 1-bit data, 54 is an output circuit,
01a is a digital output signal. Also, 12-24
And 54 constitute an error correction means 55.

The analog input signal 100 is connected to the input terminal of the A / D converter 1 and the addition input terminal of the subtractor 3 constituting the pipeline stage 50a, respectively, and the 2-bit data "DU7" of the A / D converter 1 is provided. And "DL7" is 2
The bit is output to the storage circuit 12 and connected to the digital input terminal of the D / A converter 2. D / A converter 2
Is connected to the subtraction input terminal of the subtractor 3 and the subtractor 3
Are connected to an amplifier 4.

Similarly, the output of the pipeline stage 50a is connected to the pipeline stage 50b, and the output of the pipeline stage 50b is connected to the pipeline stage 50c.
And the output of the pipeline stage 50c is connected to the pipeline stage 50d.

The output of the pipeline stage 50d is connected to the pipeline stage 50e, and the output of the pipeline stage 50e is connected to the pipeline stage 50e.
f, and the output of the pipeline stage 50f is connected to the pipeline stage 50g.

The 2-bit data output of the storage circuit 12 is connected to the first and second input terminals of the digital adder 13, and the upper bit data “DU 6” of the pipeline stage 50 b is supplied to the third adder of the digital adder 13. Is connected to the input terminal.

The lower bit data "DL6" of the pipeline stage 50b and the 2-bit data output of the digital adder 13 are connected to a 3-bit storage circuit 14, and the 3-bit data output of the storage circuit 14 is applied to the digital adder 1
5, the upper bit data "DU5" of the pipeline stage 50c is connected to the fourth input terminal of the digital adder 15.

The lower bit data "DL5" of the pipeline stage 50c and the 3-bit data output of the digital adder 15 are connected to a 4-bit storage circuit 16, and the 4-bit data output of the storage circuit 16 is applied to the digital adder 1
7 is connected to the first to fourth input terminals, and the upper bit data “DU4” of the pipeline stage 50d is connected to the fifth input terminal of the digital adder circuit 17.

The lower bit data "DL4" of the pipeline stage 50d and the 4-bit data output of the digital adder 17 are connected to a 5-bit storage circuit 18, and the 5-bit data output of the storage circuit 18 is connected to the digital adder 1
9 are connected to the first to fifth input terminals, and the upper bit data “DU3” of the pipeline stage 50e is connected to the sixth input terminal of the digital adder circuit 19.

The lower bit data "DL3" of the pipeline stage 50e and the 5-bit data output of the digital adder 19 are connected to a 6-bit storage circuit 20, and the 6-bit data output of the storage circuit 20 is connected to the digital adder 2
The upper bit data “DU2” of the pipeline stage 50f is connected to the seventh input terminal of the digital adder 21.

The lower bit data “DL2” of the pipeline stage 50f and the 6-bit data output of the digital adder 21 are connected to a 7-bit storage circuit 22, and the 7-bit data output of the storage circuit 22 is connected to the digital adder 2
The upper bit data "DU1" of the pipeline stage 50g is connected to the eighth input terminal of the digital adder circuit 23.

Finally, the lower-order bit data "DL1" of the pipeline stage 50g and the 7-bit data output of the digital adder 23 are connected to the 8-bit storage circuit 24, and the 8-bit data output of the storage circuit 24 is output to the output circuit 54.
The output circuit 54 is connected to the digital output signal 101.
a is output.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is an explanatory diagram for explaining the addition operation in each digital addition circuit.

At "S001" in FIG. 2, the digital adder 13 adds the lower bit "DL7" of the pipeline stage 50a, which is the output of the storage circuit 12, and the upper bit "DU6" of the pipeline stage 50b. AD6-1 ", and the carry from the lower bit is added to the upper bit" DU7 "of the pipeline stage 50a and output as" AD7-1 ".

The storage circuit 14 stores "AD7-1" and "AD6-1", which are the outputs of the digital addition circuit 13, and the lower bit "DL6" of the pipeline stage 50b.

In FIG. 2, in "S002", the digital adder 15 adds the upper bit "DU5" of the pipeline stage 50c to the lower bit "DL6" of the pipeline stage 50b in the output of the storage circuit 14, and outputs "AD".
5-2 ", and if a carry occurs in the lower bits, the higher bits" AD6-1 "and" AD7- "
1 ”and carry“ AD6-2 ”and“ AD7 ”.
-2 ".

The storage circuit 16 outputs "AD7-2", "AD6-2" and "AD7" which are the outputs of the digital addition circuit 15.
5-2 "and the lower bits of the pipeline stage 50c"
DL5 "is stored.

In "S003" in FIG. 2, the digital addition circuit 17 adds the upper bit "DU4" of the pipeline stage 50d to the lower bit "DL5" of the pipeline stage 50c in the output of the storage circuit 16, and outputs "AD".
4-3 ", and when a carry occurs in the lower bit, the higher bits" AD5-2 "and" AD6-2 "are sequentially output.
Carry with "AD7-2" and "AD5-
3 "," AD6-3 "and" AD7-3 ".

Similarly, at "S004" in FIG. 2, the digital addition circuit 23 adds the upper bit "DU1" of the pipeline stage 50g to the lower bit "DL2" of the pipeline stage 50f in the output of the storage circuit 22. When a carry occurs in the lower bits, the higher bits are sequentially set to "AD2-5" to "AD1".
6-5 "and" AD7-5 ", carry" A
D2 "to" AD6 "and output as" AD7 ".

Finally, the storage circuit 24 stores the outputs of the digital adder 23, "AD7", "AD6" to "AD".
1 "and the lower bit" DL1 "of the pipeline stage 50g is stored as the least significant bit" AD0. "
4 is output as a digital output signal 101a.

As described above, by alternately providing the storage circuit and the adder circuit and performing the data collection while performing the error correction, there is no need to store the data until the data necessary for the error correction is prepared.
The circuit scale of the storage circuit can be reduced.

Since error correction is performed sequentially during pipeline processing, an adder circuit of a multi-bit data and 1-bit data adder can be used, so that the circuit scale can be reduced.

That is, in the conventional example, the adding means 52 for adding the multi-bit data and the multi-bit data is required. It also leads to higher speed.

For example, FIG. 3 is a block diagram showing a specific example of the adder circuit of the embodiment shown in FIG. In FIG. 3, 50a to 50g, 12 to 24, 51, 54, 100
And 101a have the same reference numerals as in FIG.
35 and 54 constitute an error correction means 55a.

For example, the adder circuit 13 forms a half adder with an exclusive OR circuit (hereinafter, referred to as EXOR) and an exclusive OR circuit for inverted output (hereinafter, referred to as EXNOR), and outputs the inverted output. AND circuit (hereinafter, NAND)
Call. ) To carry up.

Similarly, the adder circuit 23 has an EXOR and six Es
XNOR forms a 6-bit and 1-bit half adder, and carries out a carry process using six NANDs.

For example, the number of transistors in the configuration shown in FIG. 3 is about 2300, while the number of transistors in the configuration of the conventional example shown in FIG. 4 is about 4300, and the ratio is "2300/4300 = 53". % ", Indicating that the circuit scale is reduced.

As a result, it is possible to reduce the circuit scale of the storage circuit by alternately providing the storage circuit and the adder circuit and performing data pipeline while performing error correction.

In the configuration block diagram of FIG. 1 and the like, the 8-bit output of the storage circuit 24 is output via the output circuit 54, but of course, the output may be directly output.

The storage circuit 12 and the like shown in the block diagram of FIG. 1 and the like may be a D-type flip-flop circuit and the like as shown in FIG. Further, a delay means for delaying a certain period may be used.

In FIG. 1 and the like, for simplicity of description, a pipeline A /
Although the D means is illustrated, any number of stages may be used as long as the stages are plural. For example, the minimum configuration is a pipeline A / D means composed of two pipeline stages.

Similarly, error correction means 5
5 may have the same number of configurations as the number of pipeline stages. For example, in the case of pipeline A / D means composed of two pipeline stages, two storage circuits 12
And 14 and one digital addition circuit 12. "N" if the pipeline stage is "n"
And the “n−1” digital adder circuits.

[0069]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first to sixth aspects of the present invention, it is possible to reduce the circuit scale of the storage circuit by alternately providing the storage circuit and the addition circuit and performing data pipeline while performing error correction. .

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a pipeline A / D converter according to the present invention.

FIG. 2 is an explanatory diagram illustrating an addition operation in each digital addition circuit.

FIG. 3 is a configuration block diagram illustrating a specific example of an adder circuit portion;

FIG. 4 is a configuration block diagram illustrating an example of a conventional pipeline A / D converter.

FIG. 5 is a configuration block diagram showing an example of a pipeline A / D means composed of three pipeline stages.

FIG. 6 is a table showing inputs and outputs of a 1.5-bit A / D converter.

FIG. 7 is a table showing inputs and outputs of a 1.5-bit D / A converter.

FIG. 8 is an explanatory diagram illustrating an operation and the like in each pipeline stage.

FIG. 9 is an explanatory diagram showing a specific example of an error collection.

FIG. 10 is a timing chart for explaining the operation of the conventional example.

FIG. 11 is an explanatory diagram illustrating an operation of a conventional example.

[Explanation of symbols]

1 1.5-bit A / D converter 2 1.5-bit D / A converter 3 Subtractor 4 Amplifier 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 16
18, 20, 22, 24 Storage circuits 13, 15, 17, 19, 21, 23 Digital addition circuits 50a, 50b, 50c, 50d, 50e, 50f, 5
0g pipeline stage 51 pipeline A / D means 52 arithmetic means 53, 55 error correction means 54 output circuit 100 analog input signal 101, 101a digital output signal

Claims (6)

[Claims] 1. A pipeline A / D converter, comprising: a pipeline A / D means comprising a plurality of pipeline stages connected in series; and performing error correction of digital data from each of the pipeline stages. A pipeline A / D converter, which further comprises error correction means for pipelinely processing the digital data. 2. A 1.5-bit A / D converter for converting an input signal into a digital signal.
A D converter, and an output of the A / D converter is converted into an analog signal.
It comprises a 5-bit D / A converter, a subtractor for subtracting the output of the D / A converter from the input signal, and an amplifier for amplifying and outputting the output of the subtractor. The pipeline A according to claim 1.
/ D converter. 3. The first memory circuit for storing digital data from the first pipeline stage, wherein the error correction means includes: a first memory circuit for storing digital data from the first pipeline stage; A digital adder circuit for adding an upper bit of the second pipeline stage to the bit and adding a carry from the lower bit to the upper bit of the first pipeline stage; 2. The pipeline A / D converter according to claim 1, further comprising a second storage circuit for adding and storing a lower bit of the second pipeline stage as a least significant bit. 4. The pipeline A / D converter according to claim 3, wherein said storage circuit is constituted by a D-type flip-flop circuit. 5. The pipeline according to claim 3, wherein said digital adder circuit comprises a half adder and an AND circuit of an inverted output for performing a carry process.
D converter. 6. The pipeline A / D converter according to claim 5, wherein said half adder comprises an exclusive OR circuit and an exclusive OR circuit having an inverted output.