JP2001175619A - Single-chip multiprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve performance improvement which is scalable up to an increasing degree of semiconductor integration by improving the price performance ratio with respect to a multiprocessor for parallel processing. SOLUTION: The single-chip multiprocessor includes processing elements 16 each including a CPU 20, a network interface 32 connected to the CPU, an adjustable prefetch instruction cache 24 connected directly to the CPU and network interface, and a data transfer controller 30 connected directly to the CPU and a concentrated common memory 28 which is connected to the respective processing elements and shared by the processing elements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a single-chip processor architecture in which a plurality of CPUs are housed in a single chip. Connected high-performance multiprocessor system architecture.

[0002]

2. Description of the Related Art At present, Japanese supercomputer manufacturers have the world's top hardware technology, and the peak performance at the present time exceeds several TFLOPS, and at the beginning of the 21st century, the peak performance exceeds several tens TFLOPS. The machine is expected to be developed. However, in the current supercomputer, the difference between the peak performance and the effective performance when the program is executed is increasing, that is, the price / performance ratio is not always excellent. In addition, in terms of usability, the user must extract the parallelism in question and create a program that can use the hardware effectively using an extended language or library such as HPF, MPI, or PVM. The user has a problem that it is difficult to use or cannot use it. Furthermore, due to these factors, the inability to expand the world market for high-performance computers has become a major problem.

In order to solve the problems of price / performance ratio and ease of use and to expand the supercomputer market,
It is important to develop an automatic parallelizing compiler that automatically parallelizes programs written in sequential languages such as Fortran and C that the user is familiar with.

In particular, it is important to consider a single-chip multiprocessor that is considered to be one of the main architectures of multiprocessor systems ranging from home servers to supercomputers in general and embedded microprocessors in the early 21st century. Furthermore, even for a single-chip multiprocessor, a conventional main memory sharing architecture cannot provide sufficient performance and an excellent price / performance ratio. Therefore, as in multi-grain parallel processing that can fully use instruction-level parallelism, loop parallelism, and coarse-grained parallelism in a program, more parallelism is extracted from a sequence of instructions to be truly executed. It is important to develop a new automatic parallelizing compilation technology that can improve the price / performance ratio of, and build a user-friendly system that can be used by anyone, and an architecture that can take advantage of it.

[0005]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a compiler-cooperative single-chip multiprocessor that supports multigrain parallelism and a high-performance multiprocessor system combining the same.

[0006]

SUMMARY OF THE INVENTION The present invention comprises a CPU, a network interface, an adjustable prefetch instruction cache directly connected to the CPU and the network interface, and a data transfer controller directly connected to the CPU. And a centralized shared memory connected to each processing element and shared by each processing element.

Further, according to the present invention, in accordance with a memory capacity or data transfer performance requiring a plurality of such single-chip multiprocessors, a plurality of centralized shared memory chips including only a centralized shared memory and further input / output control are performed. Provided is a multiprocessor system configured to be connected to a plurality of input / output chips.

[0008]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a single chip multiprocessor that supports multigrain parallelism. FIG. 1 shows the architecture of a single-chip multiprocessor according to an embodiment of the present invention. In FIG. 1, a plurality of processing elements (PE ₀ , P
E ₁ ,. . . , PE _n ), a plurality of (m + 1) single-chip multiprocessors (SCM ₀ , SCM ₁ ,
SCM ₂ ,. . . , SCM _m ,. . . ) 10 and a plurality (j + 1) of centralized shared memory chips (CSM ₀ ,..., CSM _j ) consisting only of shared memory (however, CSM may be omitted depending on required system conditions). ) And an input / output chip (I) composed of a plurality of (k + 1) single-chip multiprocessors for performing input / output control.
/ O SCM ₀ ,. . . , I / O SCM _k ) (where
An existing processor can be used for input / output control). The inter-chip connection network 12 can be realized by using existing network technologies such as a crossbar, a bus, and a multi-stage network.

In the embodiment shown in FIG. 1, the I / O device has (k + 1) SCMs according to a required input / output function.
Connected to the input / output control chip composed of Furthermore, this chip-to-chip connection network 12
Has j + 1 centralized shared memories (CSMs) composed of only memories shared by all processing elements in the system.
Chip 14 is connected. This serves to supplement the centralized shared memory in the SCM 10.

Multi-grain parallel processing includes coarse-grain parallelism between subroutines, loops, and basic blocks, medium-grain parallelism between loop-type iterations (loop parallelism), and (near) fine-grain parallelism between statements or instructions. This is a parallel processing method that uses the properties hierarchically. This method differs from local parallelism and single-granular parallelism such as instruction parallelism in super scalar and VLIW, which is used in conventional parallelizing compilers for commercial multiprocessor systems. Flexible parallel processing with global and multiple granularity over the entire program is possible.

[Coarse-grained task parallel processing (macro data flow processing)] Coarse-grain parallel processing utilizing parallelism between subroutines, loops, and basic blocks in a single program is also called macro data flow processing. For example, a Fortran program serving as a source is used as a coarse-grained task (macro task) as a repetition block (RB: repeti).
option block), subroutine block (SB: subroutin)
e block), pseudo assignment block (BPA: block of pse)
udo assignment statements) into three types of macro tasks (MT). RB is the outermost natural loop in each hierarchy, SB is a subroutine, and BPA is a basic block that has been fused or divided in consideration of scheduling overhead or parallelism. here,
The BPA is basically a normal basic block, but a single basic block is divided into a plurality of blocks for parallelism extraction, or the processing time of one BPA is short, and the overhead at the time of dynamic scheduling is reduced. If not negligible, a plurality of BPAs can be fused to generate one BPA. When the outermost loop RB is a Double loop, the loop index is divided into a plurality of partial Door loops, and the divided partial Door loop is divided.
The l loop is newly defined as RB. The subroutine SB is expanded inline as much as possible, but the subroutine that cannot be effectively expanded inline in consideration of the code length is directly defined as SB. Furthermore, SB and Doa
In the case of ll impossible RBs, hierarchical macro data flow processing is applied to these internal parallelisms.

Next, control flow and data dependence between macro tasks are analyzed, and a macro flow graph (M
FG). In the MFG, each node represents a macro task (MT), a dotted edge represents a control flow, a solid line edge represents data dependence, and a small circle in the node represents a conditional branch statement. The loop (RB) of MT7 indicates that MT and MFG can be defined hierarchically inside.

Next, the condition that each macro task can be executed earliest (the earliest executable condition), that is, the parallelism between macro tasks, is detected based on the control dependency and data dependency between macro tasks. The macro task graph (MTG) shown in FIG. 3 expresses this parallelism in a graph. MTG,
The node is MT, the solid line edge is data dependent, and the small circle in the node is a conditional branch statement. However, the dotted edge represents the extended control dependence, and the edge with the arrow is the original MF.
The branch destination in G, the solid arc represents the AND relationship, and the dotted arc represents the OR relationship. For example, the edge to MT6 indicates whether the conditional branch in MT2 branches in the direction of MT4,
When the execution of the MT3 is completed, it indicates that the MT6 can be executed earliest.

The compiler allocates the MT on the MTG to a processor cluster (a group of processors realized by software by a compiler or a user) at the time of compilation (static scheduling) or dynamically allocates an MT at the time of execution. A scheduling code is generated using a dynamic CP algorithm, and is embedded in a program. This is because there is a possibility that an overhead of thousands to tens of thousands of clocks may occur if the OS or the library is requested to generate and schedule a coarse-grained task like a conventional multiprocessor. At the time of this dynamic scheduling, since it is not known which processor will execute the task until the time of execution, the inter-task shared data is allocated to a centralized shared memory that is seen at the same distance from all processors.

In generating the static scheduling code and the dynamic scheduling code, a local memory or a distributed shared memory on each processor is effectively used, and a data localization method for minimizing a data transfer amount between the processors is also used. Can be

Data localization analyzes data dependencies between iterations over a plurality of different loops having data dependencies on the MTG (inter-loop data dependency analysis), and divides the loops and data so that data transfer is minimized (inter-loop data dependency analysis). After loop matching division), a task fusion method that fuses those loops at compile time so that those loops and data are scheduled on the same processor, or a partial static that the compiler specifies to be assigned to the same processor at execution time A dynamic scheduling code is generated using a scheduling algorithm. Using this data localization function, each local memory can be used effectively.

At this time, pre-load / post-store scheduling for concealing the data transfer overhead is performed by performing data transfer between processors which could not be removed even by data localization by overlapping data transfer and macro task processing. Algorithms are also used. Data transfer using the data transfer controller on each processor is realized based on the result of this scheduling.

[Loop Parallel Processing (Medium Grain Parallel Processing)] In the multi-grain parallel processing, a loop (RB) assigned to a processor cluster (PC) by macro data flow processing is such that the RB is Doall or Doacr.
In the case of an oss loop, a processing element (PE) in the PC is parallelized (divided) at an iteration level.

As the loop structuring, the following conventional techniques can be used as they are. (A) Change of statement execution order (b) Loop distribution (c) Node splitting scalar expansion (d) Loop interchange (e) Loop unrolling (f) Strip mining (g) Array privatization (h) Unimodular Conversion (loop reversal, permutation, skew)

For a loop to which the loop parallel processing cannot be applied, the loop body part is described as (near) fine-grain parallel processing as shown in FIG. Apply flow processing (coarse-grained task parallel processing).

[(Near) Fine-grained Parallel Processing] If the MT assigned to the PC is a BPA or an RB to which macro data flow processing cannot be applied hierarchically or in a loop-parallel manner, a statement or instruction inside the BPA is narrowed down. Parallel processing is performed by a processor in the PC as a granularity task.

In near-fine-grain parallel processing on a multiprocessor system or a single-chip multiprocessor,
Efficient parallel processing cannot be realized unless tasks are scheduled to the processors so as to minimize not only the load balance between the processors but also the data transfer between the processors. Furthermore, in the scheduling required in this near-fine-grain parallel processing, as shown in the task graph of FIG. 4, there is a restriction on the execution order due to data dependence between tasks, which is a very difficult scheduling problem with strong NP completeness. . This graph is a cycleless directed graph.
In the figure, each task corresponds to each node. The number inside the node represents the task number i, and the number next to the node represents the task processing time t _i on the processing element.
The edge drawn from the node N _i toward N _j represents a partial order constraint that the task T _i precedes T _j . If the data transfer time between tasks is also taken into account, each edge generally has a variable weight. If tasks T _i and T _j are assigned to different processing elements,
This weight t _ij becomes the data transfer time. In FIG. 4, it is assumed that the time required for data transfer and synchronization is 9 clocks. Conversely, when these tasks are assigned to the same processing element, the weight t _ij becomes zero.

The task graph generated in this way is statically scheduled to each processor.
At this time, as a scheduling algorithm, a heuristic algorithm that minimizes the execution time in consideration of data transfer overhead, for example, CP / DT / MIS
The best schedule can be selected by automatically applying the four methods of the F method, the CP / ETF / MISF method, the ETF / CP method, or the DT / CP method. In addition, by allocating tasks to processors in a static manner in this way, optimization of data used in the BPA, such as local memory, distributed shared memory, and allocation to registers, and minimization of data transfer / synchronization overhead are performed. Various optimizations such as optimization are possible.

After scheduling, the compiler generates a machine code for each processor by arranging the instruction sequences of the tasks assigned to the processing elements in order, and inserting data transfer instructions and synchronization instructions at necessary places. The version number method is used for synchronization between near-fine-grained tasks, and the reception of the synchronization flag is performed by the busy wait of the processing element on the receiving side. Here, the data transfer and the setting of the synchronization flag can be performed with low overhead by the processor on the transmitting side directly writing in the distributed shared memory on the processor on the receiving side.

At the time of machine code generation, a compiler can perform code optimization using information of static scheduling. For example, when different tasks using the same data are assigned to the same processing element, the data can be transferred via a register. Further, in order to minimize the synchronization overhead, redundant synchronization can be removed from the task assignment status and the execution order. In particular, in single-chip multiprocessors, strict code execution scheduling is performed during code generation, so that the compiler controls all instruction execution, including data transfer timing during execution, and removes all synchronous code to execute in parallel. Ultimate optimization such as asynchronous parallelization that enables

In order to realize the above-described multi-grain parallel processing on a multi-processor system, for example, a single-chip multi-processor (SCM) 10 has an architecture as shown in FIG.

In the architecture shown in FIG. 1, in addition to the CPU 20, a distributed shared memory (DSM:
A distributed shared memory 22 and an adjustable prefetch instruction cache 24 are provided in each SCM 10. The CPU 20 used here is not particularly limited as long as it can perform an integer operation or a floating-point operation. For example, a simple single issue RISC architecture CPU with load / store architecture
And a superscalar processor, a VLIW processor, and the like. The distributed shared memory 22 is composed of a dual-port memory, and can be directly read / written from other processing elements, and is used for data transfer between near-fine-grained tasks described above.

The adjustable prefetch instruction cache 24 prefetches an instruction to be executed in the future from a memory or a low-level cache according to an instruction from a compiler or a user. The adjustable prefetch instruction cache 24 is a multi-way set associative cache so that a line (instruction sequence) to be executed in the future can be fetched to a way specified by software such as a compiler or determined in advance by hardware. Is what you do. At that time, as a unit of fetch, a continuous transfer instruction of a plurality of lines can be performed. Adjustable prefetch instruction cache 24
Is a cache system that allows coordination and control by a compiler that minimizes mishits to the instruction cache and enables faster instruction execution.

That is, the adjustable prefetch instruction cache 24 can cope with a large program, unlike a local program memory which assumes that all programs (instruction strings) are smaller than the memory size. Depending on the characteristics, it can be used as a normal cache without prefetching, or on the contrary, it can be used as a prefetch cache under the control of a compiler, and can be used as a cache with no miss (no miss hit).

FIG. 5 shows an example of the structure of such an adjustable prefetch instruction cache. In the n-way set associative cache shown in FIG. 5, the j-way designated by the compiler or the user according to the program can be used as an area for prefetching (pre-reading). The prefetch instruction inserted by the compiler (prefetching of a plurality of lines instead of each line is also possible) enables necessary instructions to be present in the instruction cache before instruction execution, thereby realizing high speed. The processing element can read all n ways in the same way as a normal cache. Replacement of line is normal LRU
(Least recently used) method. In general, freely transferred lines can be stored in the ways in each set (set), but only the lines transferred from the CSM by the prefetch instruction are stored in the way designated for prefetch. Other ways are assigned lines as in the normal cache. The prefetch cache controller prefetches an instruction from the CSM according to an instruction from the compiler. The unit of transfer at this time is one line to a plurality of lines. The compiler specifies a prefetch area for j ways, and the other (n−j) ways area is used as a normal cache.

Further, in the architecture of FIG. 1, a local data memory (LDM) 26 is provided. The local data memory 26 is a memory that can be accessed only within each processing element 16 and is used to hold local data used between tasks assigned to each processing element 16 by data localization technology or the like. . The local data memory 26 is used as a local memory when a compiler or a user can divide and allocate data to the local memory for a target application program, and is used when the local memory cannot be used effectively. Is preferably switched to a level 1 cache (D cache) for use. In the case where it is exclusively used for real-time applications such as game machines, it is also possible to design as a local memory only. Since it is basically a memory used in each processing element,
Since the chip area is not consumed as compared with the shared memory, a relatively large capacity can be obtained.

In coarse-grain parallel processing, dynamic scheduling is used to deal with conditional branches. In this case, it is not known at compile time which processor the macro task will execute. Therefore, shared data between dynamically scheduled macro tasks is stored in a centralized shared memory (CSM).
d memory). Therefore, in this embodiment, each processing element 16
The centralized shared memory 28 for storing data shared by
In addition to being provided in the CM, a centralized shared memory 14 connected to the inter-chip connection network 12 is further provided.
The centralized shared memory 28 in the chip is a memory for storing data shared from all the processing elements 16 in the chip 10, and also from processing elements on other chips in a multi-chip configuration. Similarly, the centralized shared memory 14 outside the chip is a memory shared by the respective processing elements. Therefore, in an actual design, the centralized shared memories 28 and 14 are:
Although physically distributed to each chip, it can be logically shared equally by any processing element. It can be implemented so as to be seen from all processing elements at the same distance, or it can be implemented so as to be seen as close as possible from the processing elements in its own chip.

In a system consisting of a single SCM chip, the processing elements (PE) 16 in the chip
This centralized shared memory 28 can be used as an equidistant shared memory shared between the two. When it is difficult to optimize the compiler, it can be used as an L2 cache. The memories 28 and 14 mainly store data shared between tasks during dynamic task scheduling. In the case where the capacity of the centralized shared memory 28 in the SCM chip 10 is insufficient, the centralized shared memory 14 as another chip may be connected to an arbitrary number of large-capacity centralized shared memory chips consisting only of memories, if necessary. can do.

Further, when static scheduling can be applied regardless of the granularity, it is known at compile time which processor needs shared data defined by a certain macro task. It is preferable that the data and the synchronization flag can be directly written in the distributed shared memory.

Data transfer controller (DTC) 30
The DSM 22 on its own processing element or its own or another S
Data transfer is performed with the CSM 28 in the CM 10 or the DSM on another processing element. When a configuration including a plurality of SCMs is adopted, another SCM
Data transfer between the above CSM and DSM, or
Data transfer between independent CSMs.

The dotted line between the local data memory 26 and the data transfer controller 30 in FIG. 1 indicates that the data transfer controller 30 may be configured to access the local data memory (D-cache) 26 depending on the application. ing. In such a case, it is possible to adopt a configuration in which the CPU 20 gives a transfer instruction to the data transfer controller 30 via the local data memory 26 or checks whether the transfer is completed.

The data transfer instruction to the data transfer controller 30 is sent to the local data memory 26, the DSM 22,
Or via a dedicated buffer (not shown)
The report of the end of the data transfer from the data transfer controller 30 to the CPU 20 is made via a local memory, a DSM or a dedicated buffer. At this time, which one to use is determined at the time of processor design according to the use of the processor, or a plurality of methods are prepared in hardware so that a compiler or a user can selectively use software in accordance with the characteristics of the program.

Data transfer instruction to the data transfer controller 30 (for example, from what address to where to store and load the inner byte data, data transfer mode (continuous data transfer, stride, stride / stride transfer, etc.), etc.) Reduces the overhead for driving the data transfer controller 20 by storing a data transfer instruction in a memory or a dedicated buffer and issuing only an instruction on which data transfer instruction is to be executed at the time of execution. Is preferred.

The connection between the processing elements 16 in each SCM chip 10 is achieved by an intra-chip connection network (comprising a multi-bus, crossbar, etc.) 34 via a network interface 32 provided in each processing element. Processing elements are connected to a common centralized shared memory 28 via the intra-chip connection network 34.
The central shared memory 28 is connected to the inter-chip connection network 12 outside the chip. The inter-chip connection network is particularly preferably a crossbar network or a bus (including a plurality of buses), but may be a multistage interconnected network or the like, and can be selected according to the budget, the number of SCMs, and the characteristics of the application. . Further, it is also possible to connect the external inter-chip connection network 12 and the network interface 32 without going through the intra-chip connection network 34.
Allows all processing elements in the system to access the centralized shared memory and the distributed shared memory equally distributed on each chip, and provides this direct connection path when data transfer between chips is large. As a result, the data transfer capability of the entire system can be greatly increased.

The global register file 36 is a multi-port register and is a register shared by processing elements in a chip. For example,
It can be used for data transfer and synchronization of near-fine-grained tasks (such as when using a distributed shared memory). This global register file can be omitted according to the purpose of the processor.

In FIG. 1, a dotted line means that a communication line can be prepared as needed, and when unnecessary or difficult in consideration of cost, the number of pins, etc., operation is performed without connecting the dotted line. It indicates that

As described above, the present invention has been described based on the specific embodiments. However, the technical scope of the present invention is not limited to such embodiments, and is easily understood by those skilled in the art. It includes various modifications.

[0043]

As described above, according to the single-chip multiprocessor of the present invention, it is possible to improve the price / performance ratio and to improve the scalable performance with the increasing degree of integration of semiconductors. The present invention also provides a system including a plurality of such single-chip multiprocessors,
Such a system allows for even faster processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a multi-grain parallel processing system according to an embodiment of the present invention.

FIG. 2 is a graph showing an example of a macro flow graph for coarse-grain parallel processing in a compiler that can be used in the present invention.

FIG. 3 is a graph showing an example of a macro task graph for coarse-grain parallel processing in a compiler that can be used in the present invention.

FIG. 4 is a graph showing an example of a near-fine grain task graph for near-fine grain parallel processing in a compiler that can be used in the present invention.

FIG. 5 is a block diagram showing a configuration of an adjustable prefetch instruction cache that can be used in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Single-chip multiprocessor 12 Inter-chip connection network 14 Centralized shared memory (chip) 16 Processing element 20 CPU 22 Distributed shared memory 24 Adjustable prefetch instruction cache 26 Local data memory 28 Centralized shared memory 30 Data transfer controller 32 Network interface 34 In-chip connection network

Claims (4)

[Claims] 1. A CPU, a network interface connected to the CPU, an adjustable prefetch instruction cache directly connected to the CPU and the network interface, a data transfer controller directly connected to the CPU, A plurality of processing elements including a memory switchable as a local memory or a data cache, a distributed shared memory accessible from all processing elements, and a centralized shared memory connected to each processing element and shared by each processing element And a single-chip multiprocessor. 2. The system of claim 1, further comprising a global register file connected to each processing element.
A single-chip multiprocessor as described. 3. A computer comprising a plurality of single-chip multiprocessors according to claim 1. 4. A single chip multiprocessor according to claim 1 or 2, a centralized shared memory chip including a memory shared by all the single multiprocessors, and a single chip multiprocessor for input / output control. Become a computer.