JP2001168305A - Non-volatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device in which the tunnel insulating film of a memory cell is improved in reliability, and a method of manufacturing the same. SOLUTION: A non-volatile semiconductor memory device, which is equipped with memory cells in which a voltage is applied to a control electrode 20 to enable charge to move between a tunnel region and a charge storage means 19 to store data, is manufactured through a method, the method comprises a process in which a tunnel insulating film 6 is formed on a semiconductor substrate 1, a process in which a charge storing means and a control gate are laminated, a process in which impurities are diffused into a tunnel region through both the ends of the control gate, and charge storing means for the formation of impurity diffusion layers 5 and 12 of concentration gradient in which impurity concentration gets low at the center of the tunnel region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile semiconductor memory device having an improved reliability of a tunnel insulating film in an EEPROM having a floating gate and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art Currently, an EEPROM (Electric) is used.
all Erasable Programmable
e ROM) embedded in a microcomputer etc.
Demands for EEPROMs are increasing and developments are being actively pursued. In particular, when the capacity of the EEPROM to be mounted is a relatively small capacity of several kbits to several tens of kbits and a low voltage operation is required, an FN-type device for injecting and extracting electrons by FN tunneling is used as a rewriting method. The FN method is often adopted.
In such a case, the memory cell generally has a configuration in which one selection transistor is attached to one memory transistor.

[0003] The structure and manufacturing method of a conventional EEPROM will be described below. FIG. 5A shows a conventional EEP.
FIG. 5B is a sectional view of a ROM, and FIG.
It is a top view showing the layout of M. FIG. 5A shows FIG.
It is sectional drawing in AA 'of (b).

[0004] As shown in FIG.
Floating gate 1 on gate oxide film 7
9, an inter-gate insulating film 9 and a control gate 20 are stacked. A high-concentration impurity diffusion layer 5 is formed below the tunnel oxide film 6, and a low-concentration impurity diffusion layer 12 is formed with the high-concentration diffusion layer 5 or a channel formation region below the gate interposed therebetween. These electrodes are covered with an interlayer insulating film 13, and a bit line 15 on the interlayer insulating film 13 and the substrate 1 are connected by a bit contact 14 formed on the interlayer insulating film 13.

[0005] As shown in the plan view of FIG.
On the active region 16 surrounded by the element isolation film 2,
A tunnel window 17, a floating gate 19, a control gate 20, a select gate 21, and a bit contact 14 are formed, and the inside of the tunnel window 17 is a tunnel region 18.

In the above-mentioned memory cell, the injection of electrons
For example a high voltage of about 20V is applied to the control gate and the bit line to 0V, is carried out by applying a V _cc to the selection gate. To extract electrons, for example, 0 V is applied to the control gate, and 2 V is applied to the bit line and the selection gate.
This is performed by applying a high voltage of about 0V.

A method of manufacturing the above-described EEPROM will be described below with reference to FIGS. 6 to 8, the left side (a-1, b-1 and c-1) is A- in FIG. 5 (b).
A cross-sectional view at A 'is shown. 6 to 8, the right side (a-2, b-2, and c-2) is B- in FIG.
The sectional view at B 'is shown.

First, as shown in FIGS. 6A-1 and 6A-2, for example, a LOCOS
The element isolation film 2 is formed by the method. Further, the oxide film 3 is formed by, for example, thermal oxidation. Next, as shown in FIGS. 6B-1 and 6B-2, the photoresist 4 is patterned, and impurities are ion-implanted using the photoresist 4 as a mask to form a high-concentration diffusion layer 5 in a tunnel region. . Further, as shown in FIGS. 6C-1 and 6C-2, the oxide film 3 in the tunnel region is removed by, for example, wet etching using diluted hydrofluoric acid. After that, the photoresist 4 is removed.

Next, as shown in FIGS. 7A-1 and 7A-2, a tunnel oxide film 6 is formed in the tunnel region by, for example, thermal oxidation. At this time, a gate oxide film 7 is formed in an active region other than the tunnel region. Next, as shown in FIGS. 7 (b-1) and 7 (b-2), an electrode material 8 to be a floating gate 19 is deposited in a subsequent step. Subsequently, FIGS. 7 (c-1) and (c-2)
As shown in (1), the electrode material 8 is processed in the word line direction.

Next, as shown in FIGS. 8 (a-1) and 8 (a-2), for example, SiO ₂ / Si
An inter-gate insulating film 9 made of a laminated film of N / SiO ₂ is formed. Further, in a subsequent step, an electrode material 10 to be the control gate 20 or the selection gate 21 is deposited.
Next, as shown in FIG. 8B-1, a photoresist 11 having a gate pattern is formed, and gate processing is performed on the electrode materials 8, 10 and the inter-gate insulating film 9 using the photoresist 11 as a mask. The gate processing is performed by dry etching such as reactive ion etching (RIE).

After that, as shown in FIG. 8C, while the photoresist 11 is left, a relatively low concentration impurity is ion-implanted to form a low concentration diffusion layer 12. Further, as shown in FIG. 5A, an interlayer insulating film 13 made of, for example, SiO ₂ is formed, and a bit contact 14 is formed in the interlayer insulating film 13. Further, a bit line 15 made of, for example, an Al alloy is formed on the interlayer insulating film 13. Through the above steps, the conventional EEPROM shown in FIG. 5 is formed.

[0012]

However, when an EEPROM is manufactured by the above-mentioned conventional manufacturing method, as shown in FIGS. 7 (a-1) and (a-2), the tunnel oxide film 6 has a high concentration of diffusion. Formed on top of layer 5. When the tunnel oxide film 6 is formed after the formation of the high-concentration diffusion layer 5, the oxidation is likely to occur due to the influence of impurities contained in the high-concentration diffusion layer 5. As a result, there is a problem that the controllability of the film thickness is deteriorated and the quality of the tunnel oxide film itself is deteriorated as compared with a case where the tunnel oxide film is formed on a normal silicon substrate.

Since the high-concentration diffusion layer 5 is always formed under the tunnel oxide film 6, this oxide film cannot be used as a gate oxide film of a peripheral transistor. There was also a disadvantage that the degree was low. The present invention has been made in view of the above-described problems, and accordingly, the present invention ensures that the reliability of a tunnel insulating film of a memory cell can be improved while ensuring compatibility with a manufacturing process of a transistor used in a peripheral circuit. An object of the present invention is to provide an improved nonvolatile semiconductor memory device and a method of manufacturing the same.

[0014]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention applies a voltage to a control electrode to move charges between a tunnel region and charge storage means. A non-volatile semiconductor storage device having a memory cell for storing information, comprising: an impurity diffusion layer formed in the tunnel region on a surface of a semiconductor substrate; a tunnel insulating film formed on the tunnel region; The semiconductor device includes the charge storage means formed on a film, and the control electrode formed on the charge storage means, and the impurity diffusion layer has a concentration gradient with a low impurity concentration at a central portion of the tunnel region. It is characterized by the following.

In the nonvolatile semiconductor memory device according to the present invention, preferably, the tunnel insulating film is a silicon oxide film. In the nonvolatile semiconductor memory device of the present invention, preferably, the charge storage means is formed on the tunnel insulating film, and a conductive layer in an electrically floating state is provided between the conductive layer and the control electrode. It is characterized in that it is a charge trap formed discretely in a laminated film composed of the formed inter-gate insulating film. In the nonvolatile semiconductor memory device of the present invention, preferably, a plurality of the memory cells are formed on the semiconductor substrate, and a selection transistor for selecting the memory cell is formed on the semiconductor substrate around the memory cell. It is characterized by being.

Thus, when forming the tunnel insulating film, it is possible to prevent the accelerated oxidation from occurring due to the influence of the underlying impurity diffusion layer and to prevent the film quality of the tunnel insulating film from deteriorating. In addition, since it is not necessary to form a high-concentration impurity diffusion layer in a tunnel region before forming a tunnel insulating film, an oxide film formed as a tunnel insulating film can be used as a gate oxide film of a peripheral circuit, for example. It is possible. Therefore, the degree of freedom in the process can be increased, and the number of manufacturing steps of the nonvolatile semiconductor memory device can be reduced.

Further, in order to achieve the above object, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a voltage is applied to a control electrode to move a charge between a tunnel region and a charge storage means. A method for manufacturing a nonvolatile semiconductor memory device having a memory cell for storing information, comprising: forming a tunnel insulating film on the tunnel region on a surface of a semiconductor substrate; and forming charge storage means on the tunnel insulating film. Forming the control electrode on the charge storage means, and diffusing impurities from both ends of the control electrode and the charge storage means into the tunnel region, so that a low impurity concentration is obtained at a central portion of the tunnel region. Forming an impurity diffusion layer having a concentration gradient.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, preferably, the step of forming the tunnel insulating film includes a step of oxidizing a surface of the semiconductor substrate. In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, preferably, the step of forming the charge storage means and the control electrode includes the step of stacking materials of the charge storage means and the control electrode; Forming a resist having a predetermined pattern on the material, and performing etching using the resist as a mask, wherein the step of forming the impurity diffusion layer includes the step of ion-implanting the impurity using the resist as a mask. Performing the step of
And thermally diffusing the impurities.

Preferably, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the memory cell is provided in a plurality, and a select transistor for selecting the memory cell is formed on the semiconductor substrate around the memory cell. Forming a tunnel insulating film of the memory cell is the same as forming a gate insulating film of the select transistor, and forming the impurity diffusion layer of the memory cell comprises: The process is the same as the process of forming the source / drain regions of the select transistor.

This makes it possible to prevent accelerated oxidation from occurring at the time of forming the tunnel insulating film. Therefore, the film thickness controllability of the tunnel insulating film is improved, and the film quality itself is also improved as compared with the case where the tunnel insulating film is formed on the high-concentration impurity diffusion layer. According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the tunnel insulating film is formed before the high-concentration impurity diffusion layer is formed on the substrate. It is also possible. Therefore, it is possible to improve the reliability of the tunnel insulating film of the memory cell while ensuring compatibility with the manufacturing process of the transistor used in the peripheral circuit.

[0021]

Embodiments of a nonvolatile semiconductor memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1A shows the EE of this embodiment.
FIG. 1B is a sectional view of a PROM, and FIG.
FIG. 2 is a plan view illustrating a layout of an EPROM. FIG.
FIG. 2A is a cross-sectional view taken along line AA ′ of FIG.

In the EEPROM of this embodiment, as shown in FIG. 1A, a floating gate 19, an inter-gate insulating film 9, and a control gate 20 are stacked on a silicon substrate 1 via a gate oxide film 7. In the vicinity of the lower portion of the tunnel oxide film 6, near the surface of the silicon substrate 1 and in a portion where the gate electrode is not formed, the high concentration diffusion layer 5 is formed, and a position deeper than the high concentration diffusion layer 5, or A low concentration diffusion layer 12 is formed below the gate electrode.
Are formed. These electrodes are covered with an interlayer insulating film 13, and the bit line 15 on the interlayer insulating film 13 and the substrate 1 are connected to the bit contact 1 formed on the interlayer insulating film 13.
4.

According to the EEPROM of this embodiment, FIG.
As shown in (a), in the memory cell having the floating gate 19, the impurity diffusion layers 5 and 12 in the tunnel region for injecting / extracting electrons are formed with a concentration gradient such that it becomes thin at the center of the tunnel region. You.

Also, as shown in the plan view of FIG.
On the active region 16 surrounded by the element isolation film 2,
A tunnel window 17, a floating gate 19, a control gate 20, a select gate 21, and a bit contact 14 are formed, and the inside of the tunnel window 17 is a tunnel region 18.

The electron injection in a memory cell of the present embodiment described above, for example a high voltage of about 20V is applied to the control gate and the bit line to 0V, it is carried out by applying a V _cc to the selection gate. Electrons are extracted by applying, for example, 0 V to the control gate and applying a high voltage of about 20 V to the bit line and the selection gate.

Alternatively, in the above-described memory cell of the present embodiment, the injection of electrons is performed by, for example,
It is also possible to apply a high voltage of about V, open the bit line, and apply about -6 V to the well and source lines. Electrons are extracted by applying, for example, -10 V to the control gate, applying 6 V to the bit line, and applying about 8 V to the selection gate.
It is good also as a system.

A method of manufacturing the EEPROM according to the present embodiment will be described below with reference to FIGS. 2 to 4
The left side (a-1, b-1 and c-1) in FIG.
(B) is a cross-sectional view taken along line AA ′. The right side (a-2, b-2 and c-2) in FIGS.
(B) is a cross-sectional view taken along line BB ′.

First, as shown in FIGS. 2A-1 and 2A-2, for example, LOCOS
The element isolation film 2 is formed by the method. Further, the oxide film 3 is formed by, for example, thermal oxidation. Thereafter, wells (not shown) are formed as appropriate by ion-implanting impurities.

Next, as shown in FIGS. 2B-1 and 2B-2, the photoresist 4 is patterned.
Using the resist 4 as a mask, wet etching using, for example, diluted hydrofluoric acid is performed. Thereby, oxide film 3 in the tunnel region is removed. After removing the resist 4, FIG.
As shown in 1) and (c-2), for example, thermal oxidation is performed to form a tunnel oxide film 6 in the tunnel region. At this time, a gate oxide film 7 is formed in an active region other than the tunnel region.

Next, as shown in FIGS. 3A-1 and 3A-2, an electrode material 8 to be a floating gate 19 is deposited in a subsequent step. Subsequently, as shown in FIGS. 3B-1 and B-2, the electrode material 8 is processed in the word line direction. Next, FIGS. 3 (c-1) and (c-
As shown in 2), the surface of the electrode material 8 is, for example, SiO ₂
Inter-gate insulating film 9 composed of a laminated film of / SiN / SiO ₂
To form In the subsequent process, control gate 2
The electrode material 10 which becomes 0 or the selection gate 21 is deposited.

Next, as shown in FIGS. 4A-1 and 4A-2, a photoresist 1 having a gate pattern is formed.
1 is formed, and gate processing is performed on the electrode materials 8 and 10 and the inter-gate insulating film 9 using this as a mask. The gate processing is performed by dry etching such as reactive ion etching (RIE).

Next, as shown in FIGS. 4 (b-1) and 4 (b-2), impurities are ion-implanted with the photoresist 11 left, and then the impurities are thermally diffused. As a result, a high concentration diffusion layer 5 is formed in a portion near the surface of the silicon substrate 1 and where no gate electrode is formed,
A low concentration diffusion layer 12 is formed at a position deeper than the high concentration diffusion layer 5 or below the gate electrode.

Here, the high concentration diffusion layer 5 and the low concentration diffusion layer 1
2, there is no clear boundary, and the high concentration diffusion layer 5 and the low concentration diffusion layer 12 are continuous impurity diffusion layers having a concentration gradient. The impurity diffusion layers 5 and 12 in the tunnel region are formed by diffusing impurities from both ends of the gate electrode and connecting the diffusion layers at the center of the tunnel region. Therefore, impurity diffusion layers 5 and 12 have a concentration gradient that becomes thinner as approaching the center of the tunnel region.

After removing the photoresist 11, an interlayer insulating film 13 made of, for example, SiO ₂ is formed as shown in FIG. 1A, and a bit contact 14 is formed in the interlayer insulating film 13. Further, a bit line 15 made of, for example, an Al alloy is formed on the interlayer insulating film 13. Through the above steps, the EEPROM of the present embodiment shown in FIG. 1 is formed.

According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, the tunnel oxide film 6 is formed not on the surface of the high-concentration impurity diffusion layer but on the well with the low impurity concentration. Therefore, accelerated oxidation occurs due to the influence of impurities contained in the underlayer, and the controllability of the film thickness is deteriorated, or the film quality of the tunnel oxide film itself is deteriorated as compared with the case where the tunnel oxide film is formed on a normal silicon substrate. Avoid problems.

Embodiments of the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention are not limited to the above description.
For example, the floating gate may have a multi-layer structure such as a polycide structure, and the select gate may have a single-layer structure. In addition, various changes can be made without departing from the gist of the present invention.

[0037]

According to the nonvolatile semiconductor memory device of the present invention, the reliability of the tunnel insulating film can be improved. According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the controllability of the thickness of the tunnel insulating film can be improved, and the quality of the tunnel insulating film can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a nonvolatile semiconductor memory device according to the present invention. FIG. 1A is a cross-sectional view taken along line AA ′ in FIG.
Corresponding to

FIGS. 2A to 2C are cross-sectional views illustrating a manufacturing process of a method for manufacturing a nonvolatile semiconductor device according to the present invention, up to a step of forming a tunnel oxide film and a gate oxide film; Is shown. (A-1, b-1 and c-1) are shown in FIG.
(A-2, b-2) is a sectional view corresponding to AA ′ of FIG.
And c-2) are cross-sectional views corresponding to BB 'in FIG. 1 (b).

FIGS. 3A to 3C are cross-sectional views illustrating a manufacturing process of a method for manufacturing a nonvolatile semiconductor device according to the present invention. Show.

FIGS. 4A and 4B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a nonvolatile semiconductor device according to the present invention, in which a gate patterning process and an impurity diffusion layer forming process are performed. Is shown.

FIG. 5 is a cross-sectional view of a conventional nonvolatile semiconductor memory device, and the cross-sectional view of FIG.
Corresponding to

6 (a-1, 2) to (c-1, 2) are cross-sectional views showing a manufacturing process of a conventional method for manufacturing a nonvolatile semiconductor device, and show up to a step of forming a high-concentration impurity diffusion layer. . (A-
1, b-1 and c-1) are cross-sectional views corresponding to AA 'in FIG. 5B, and (a-2, b-2 and c-2).
FIG. 6 is a sectional view corresponding to line BB ′ in FIG.

7 (a-1, 2) to (c-1, 2) are cross-sectional views showing a manufacturing process of a conventional method for manufacturing a nonvolatile semiconductor device, and show up to a process of processing an electrode material of a floating gate. .

FIGS. 8A to 8C are cross-sectional views illustrating manufacturing steps of a conventional method for manufacturing a nonvolatile semiconductor device;
The steps up to the gate patterning step are shown.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation film 3 oxide film 4
11: photoresist, 5: high concentration diffusion layer, 6: tunnel oxide film, 7: gate oxide film, 8: electrode material of floating gate, 9: inter-gate insulating film, 10: electrode material of control gate, 12: low Concentration diffusion layer, 13: interlayer insulating film, 14: bit contact, 15: bit line, 1
6 active area, 17 tunnel window, 18 tunnel area, 19 floating gate, 20 control gate, 21 selection gate.

Continued on the front page F term (reference) 5F001 AA09 AA21 AA23 AA25 AA30 AA43 AA61 AA63 AB08 AC02 AD14 AD17 AD62 AE02 AE08 AG07 AG12 AG22 AG30 5F083 EP03 EP23 EP32 EP45 EP55 EP56 EP63 EP68 EP72 ER10 ER30 PR12 ER30 PR20 5F101 BA03 BA05 BA07 BA12 BA24 BA28 BA34 BA36 BB05 BC02 BD04 BD07 BD37 BE05 BE07 BH04 BH09 BH16 BH19

Claims (8)

[Claims] 1. A non-volatile semiconductor memory device having a memory cell for storing information by applying a voltage to a control electrode to move electric charge between a tunnel region and electric charge accumulating means. An impurity diffusion layer formed in the tunnel region; a tunnel insulating film formed on the tunnel region; the charge storage unit formed on the tunnel insulating film; and the charge storage unit formed on the charge storage unit. A nonvolatile semiconductor memory device having a control electrode, wherein the impurity diffusion layer has a concentration gradient with a low impurity concentration at a central portion of the tunnel region. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said tunnel insulating film is a silicon oxide film. 3. The charge storage means includes: a conductive layer formed on the tunnel insulating film and in an electrically floating state; and an inter-gate insulating film formed between the conductive layer and the control electrode. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said non-volatile semiconductor memory device is a charge trap formed discretely in said laminated film. 4. The non-volatile semiconductor device according to claim 1, wherein a plurality of said memory cells are formed on said semiconductor substrate, and select transistors for selecting said memory cells are formed on said semiconductor substrate around said memory cells. Storage device. 5. A method of manufacturing a nonvolatile semiconductor memory device having a memory cell for storing information by applying a voltage to a control electrode to move a charge between a tunnel region and a charge storage means, comprising the steps of: Forming a tunnel insulating film on the tunnel region on the substrate surface; forming a charge storage means on the tunnel insulating film; forming the control electrode on the charge storage means; And diffusing impurities from both ends of the charge storage means into the tunnel region to form an impurity diffusion layer having a concentration gradient with a low impurity concentration at the center of the tunnel region. Method. 6. The method according to claim 5, wherein the step of forming the tunnel insulating film includes a step of oxidizing a surface of the semiconductor substrate. 7. The step of forming the charge storage means and the control electrode includes the steps of laminating materials of the charge storage means and the control electrode, and forming a resist having a predetermined pattern on the material of the control electrode. Performing the step of performing etching using the resist as a mask. The step of forming the impurity diffusion layer includes the steps of performing ion implantation of the impurity using the resist as a mask, and thermally diffusing the impurity. 6. The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, comprising: 8. The method according to claim 8, further comprising: forming a select transistor for selecting the memory cell on the semiconductor substrate around the memory cell, wherein a plurality of the memory cells are provided, and forming a tunnel insulating film of the memory cell. Is the same step as the step of forming the gate insulating film of the select transistor, the step of forming the impurity diffusion layer of the memory cell,
6. The method according to claim 5, wherein the step is the same as the step of forming the source / drain regions of the select transistor.