JP2001167578A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a memory cycle time can be shortened appropriately while securing reliability of operation. SOLUTION: A semiconductor memory (DRAM) is constituted by providing a memory cell array section 10, an address specifying section 20, an input/output section 30 of memory data, a sense amplifier 40, a signal generating circuit 50, and the like. A row address decoder 22 constituting the address specifying section 20 is provided with a row selection latch circuit 23 holding a selected word line WL at a start state even after change of a row address XA. Also, the sense amplifier 40 is provided with a data latch circuit A 45 and a data latch circuit B 46 holding respectively and independently data of a memory cell MC amplified by the amplifier 40 and connected to two different word line WL or returning held data to the sense amplifier 40 again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a technique for reducing a memory cycle time of the memory device.

[0002]

2. Description of the Related Art FIG. 7 shows an outline of a conventional dynamic random access memory (DRAM) as a semiconductor memory device.

As shown in FIG. 7, a DRAM generally includes a memory cell array section 10 in which memory cells MC are formed in a matrix, and a row and column address for designating each memory cell MC. An address designation unit 20, a memory data input / output unit 30, and a sense amplifier 40 that amplifies and holds data when writing and reading data to and from each memory cell MC;
The storage device includes a signal generation circuit 50 that generates an internal control signal from various control signals input from the outside of the storage device.

Here, the memory cell array section 10
A plurality of bit line pairs BL, / BL ("/" indicates logical inversion), a plurality of word lines WL intersecting the same bit line pairs BL, / BL, and a pair of bit lines BL, / BL and a word line W
It is provided with a plurality of memory cells MC and the like provided at the intersection with L.

The address designating section 20 includes a row address buffer 21, a row address decoder 22, a column address buffer 25, a column address decoder 26 and the like.

The row address buffer 21 includes an externally applied address signal (external address) A0.
An, and outputs row address (internal row address) signal XA in response to control signal φ / RAS. Then, in response to the row address signal XA, the row address decoder 22 outputs a word line selection signal WLX for selecting one of the plurality of word lines WL.

Column address buffer 25 receives externally applied address signals A0 to An, and responds to control signals .phi. / RAS and .phi. / CAS to provide column address signal Y.
A is output. In response to the column address signal YA, the column address decoder 26 outputs a column selection signal YLX for selecting one of the plurality of bit line pairs BL and / BL to a transfer gate (not shown). .

On the other hand, the sense amplifier 40 is provided for each of the bit line pairs BL and / BL. When the sense amplifier activating signal SE attains the logic level "H (high)",
The potential difference between the bit line pair BL and / BL is amplified. The bit line pairs BL and / BL are connected to the data bus DB via the sense amplifier 40 and the transfer gate (not shown). A data input buffer 31 for storing write data to the memory cell and a data output buffer 32 for storing read data from the memory cell MC are connected. The input / output unit 30 includes:
The data input buffer 31 and the output buffer 32 are provided.

A / RAS buffer 61 shown in FIG. 7 receives an externally applied row address strobe signal / RAS and outputs a control signal φ / RAS. / CAS buffer 62 receives an externally applied column address strobe signal / CAS and receives control signal φ / CAS.
Is output. Similarly, / OE buffer 63 receives an externally applied output enable signal / OE and receives control signal φ
/ WE buffer 64 receives an externally applied write enable signal / WE and outputs a control signal φ / WE.

The signal generation circuit 50 controls the control signal φ.
Data output activation signal OE is output in response to / RAS, φ / CAS and φ / OE. In response to the activation signal OE, the data output buffer 32 outputs the data amplified by the sense amplifier 40 as output data Dout via the data bus DB.

The signal generating circuit 50 outputs a data input activation signal WE in response to the control signals φ / RAS, φ / CAS, φ / WE. The data input buffer 31 supplies the externally applied input data Din to the data bus DB in response to the activation signal WE. Further, the same signal generation circuit 50
A sense amplifier activation signal SE for activating 0 is output based on a control signal φ / RAS or the like.

Next, the operation of the conventional DRAM configured as described above will be described with reference to the timing chart of FIG. Here, the memory cycle time τ is a time from the start of a read or write operation to the start of the next read or write operation. This is, for example, a row address strobe signal (/ RAS pulse).
Time from one fall to the next fall (/ RAS
Cycle time).

In the memory cycle time τ, first, the row address XA is applied from the row address buffer 21 to the row address decoder 22 in response to the fall of the row address strobe signal / RAS (FIG. 8A,
(C), (d)). When the row address XA is applied to the row address decoder 22, one of the word lines is selected and rises to the logic level "H" (FIG. 8 (e)). As a result, a corresponding bit line pair BL, / B from a plurality of memory cells MC connected to the selected word line WL, respectively.
Data is read to L.

When the data of memory cell MC is output to bit line pair BL, / BL, sense amplifier activation signal SE rises to logic level "H". As a result, the sense amplifier 40 is activated, and the data of the bit line pair BL, / BL is amplified (FIG. 8F,
(G)).

After the address signals A0 to An change from the row address XA to the column address YA, the column address YA is changed from the column address buffer 25 to the column address decoder 26 in response to the fall of the column address strobe signal / CAS. (FIGS. 8 (b), (c),
(H)), the same column address decoder 26 raises any one of the plurality of column selection signals YLX to a logic level “H” (not shown). Thereby, one transfer gate is turned ON, and the corresponding bit line pair BL,
/ BL is selected. As a result, data is read from the selected bit line pair BL to the data bus DB (FIG. 8 (i)).

When the cycle is a read cycle, when the data output activation signal OE rises to the logic level "H", the data output buffer 32 is activated, whereby the output data Dout is output from the data output buffer 32. Is output to the outside (FIG. 8 (j),
(K)).

On the other hand, when the cycle is a write cycle, when data input activation signal WE rises to logic level "H", input data Din is applied from data input buffer 31 to data bus DB (FIG. 8).
(L), (m), (n)). Then, the sense amplifier 40
The data of the bit line pair BL, / BL designated by the column address out of the data of the bit line pair BL, / BL amplified by the above is rewritten to the data of the input data Din (FIG. 8).
(O)).

Thereafter, row address strobe signal / RA
In response to the rise of S, the word line WL falls (FIGS. 8A and 8E). At this time, the data of the bit line pair BL and / BL amplified by the sense amplifier 40 is stored in the memory cell MC. Restored.

Subsequently, when the word line WL falls to the logic level "L (low)", the row address buffer 21 is reset (FIGS. 8D and 8E). Then, in preparation for the next access, the bit line pair BL, / BL is precharged.

The above is an outline of a series of operations for one memory cycle (/ RAS cycle) of a conventional DRAM.

[0021]

As described above, in the above-mentioned conventional DRAM, one of the following problems occurs in the memory operation.
Within one memory cycle (/ RAS cycle) time τ,
A series of processing operations from the determination of the row address to the rise of the word line, the amplification of the bit line data by the sense amplifier, the restoration of the cell data, the fall of the word line, and the precharge of the bit line are performed in series. Done. In addition, in order to reliably execute the series of processes, an execution margin time is indispensable in addition to an execution time required for each process.

Therefore, when speeding up access to the DRAM, there is naturally a limit to shorten the memory cycle time τ. The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device capable of appropriately shortening a memory cycle time while ensuring operation reliability. It is in.

[0023]

The means for achieving the above object and the effects thereof will be described below. According to the first aspect of the present invention, a plurality of signal lines crossing each other, a memory cell array portion including a plurality of memory cells formed at intersections of the signal lines, and An address decoder for selecting one signal line from at least one signal line group arranged in the same direction, wherein the address decoder includes a selection latch circuit for holding a state of the selected signal line for an arbitrary period. The gist is to provide separately for each corresponding signal line.

Further, in the invention described in claim 2, a memory cell array section comprising a plurality of word lines and a plurality of bit line pairs and a plurality of memory cells formed at intersections thereof, and In a semiconductor memory device comprising: a row address decoder for selecting one word line from word lines; and a sense amplifier connected to each of the plurality of bit line pairs, the row address decoder includes a row address decoder for selecting the selected word line. The gist is that a row selection latch circuit for holding a state for an arbitrary period is separately provided for each corresponding word line.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the semiconductor memory device further comprises a data holding means for holding data of a memory cell connected to the selected word line for an arbitrary period. Is the gist.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the data holding means is provided in the sense amplifier, and stores data of memory cells connected to different word lines. The main point is that the data latch circuit is constituted by a plurality of data latch circuits.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the gist is that the data latch circuit includes two data latch circuits. According to a sixth aspect of the present invention, in the semiconductor memory device according to the third aspect, the data holding means includes a plurality of sense amplifiers provided for each of the bit line pairs. And

According to a seventh aspect of the present invention, in the semiconductor memory device of the sixth aspect, two sense amplifiers are provided for each bit line pair.

According to the first aspect of the present invention, it is possible to simultaneously activate a plurality of signal lines through the latch function of the selection latch circuit. This eliminates the need to perform the data processing of the memory cells connected to the selected signal line within the same memory cycle time even in the processing related to the memory operation such as writing and reading of the memory data. It is possible to do. That is, the memory cycle time can be reduced.

According to each configuration of the present invention, a plurality of word lines can be simultaneously activated. Therefore, in processing related to memory operations such as writing and reading of memory data, for example, it is not necessary to perform processing related to data of a memory cell connected to a selected word line within the same memory cycle time. Therefore, processing related to memory operation can be performed by the pipeline through the latch circuit or the sense amplifier, and the memory cycle time can be reduced.

Further, according to the configuration of the present invention, the pipeline processing of the memory operation can be realized with a minimum necessary configuration.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment in which a semiconductor memory device according to the present invention is applied to a DRAM will be described below with reference to FIGS. In addition,
Here, the description will focus on the differences from the conventional DRAM shown in FIG. 7, and the same components as those in the conventional DRAM will be assigned the same reference numerals and redundant description will be omitted.

FIG. 1 is a diagram showing a DR according to the first embodiment.
FIG. 2 is a block diagram schematically showing an internal configuration of an AM. As shown in FIG. 1, the DRAM of the present embodiment also has a memory cell array unit 10, an address designating unit 20,
It comprises a memory data input / output unit 30, a sense amplifier 40, a signal generation circuit 50 and the like.

The memory cell array section 10 includes, for example, m word lines WL1 to WLm selected by the row address decoder 22, and n sets of bit line pairs (BL1, / BL1) to (BL
n, / BLn) and m × n memory cells MC formed at their intersections.

The address specifying section 20 includes a row address buffer 21, a row address decoder 22, a column address buffer 25, a column address decoder 26 and the like.

The memory data input / output unit 30
Is provided with a data input buffer 31 and an output buffer 32. Then, the signal generation circuit 50
Are the control signals φ / RAS, φ / CAS, φ / OE,
In response to φ / WE, a data output activation signal OE, a data input activation signal WE, etc. are generated.

On the other hand, in the DRAM of the present embodiment, in addition to the basic structure of the conventional DRAM, as shown in FIG. A circuit 23 is provided. The row selection latch circuit 23 enables the state of the word line WL selected by the row address decoder 22 and raised to the logic level “H” to be held even after the row address XA changes.

Further, each sense amplifier 40 is provided with two data latches, a data latch circuit (A) 45 and a data latch circuit (B) 46. The data latch circuits (A) 45 and (B) 46 independently retain the data of the memory cells MC connected to the two different word lines WL amplified by the sense amplifier 40, or retain the retained data. Can be returned to the sense amplifier 40 again.

Next, the operation of the DRAM of this embodiment will be described with reference to the timing charts of FIGS. Here, FIG. 2 shows a timing chart of a memory data read operation, and FIG. 3 shows a timing chart of a memory data write operation.

First, the operation of reading memory data will be described with reference to FIG. [1] Read operation of memory data (1) Memory cycle Cr1 In the memory cycle Cr1 shown in FIG.
In response to the fall of the AS signal, the address "A" is latched in the row address buffer 21 as the row address XA input from the outside of the memory.
The RAS signal is held until it falls again (FIG. 2).
(A), (d)). In response to the fall of the / CAS signal, a column address Y also input from outside the memory is input.
The address "P" is latched as A in the column address buffer 25, and is held until the / CAS signal falls again in the next cycle Cr2 (FIGS. 2B and 2E).

Based on the latch data in the row address buffer 21, the word line WLA rises by the row address decoder 22 (FIG. 2 (f)), and the data of all the memory cells MC connected to the word line WLA is changed. It is output to the bit line pair BLX (X = 1 to m). And
The data is amplified by the sense amplifier 40 activated by the sense amplifier activation signal SE (FIG. 2 (j)).

In this embodiment, as described above,
The word line WLA does not fall during the memory cycle Cr1, but falls during the memory cycle Cr3 as shown in FIG. (2) Memory Cycle Cr2 Subsequently, in the memory cycle Cr2, first, the data amplified by the sense amplifier 40 in the memory cycle Cr1 is transferred to the data latch circuit (A).
The data is temporarily held in the data latch circuit (A) 45 in synchronization with the rise of the timing signal LIA taken into the memory 45 (FIG. 2 (k), (o)). Thereafter, the bit line pair BLX is precharged. At this time, the word line WLA is still held up (FIG. 2 (f)).

Subsequently, the row address "B" is latched in the row address buffer 21 and the column address "Q" is latched in the column address buffer 25 in the same manner as in the memory cycle Cr1. Then, based on the latch data in the row address buffer 21, the row address decoder 22
The word line WLB rises (FIG. 2 (f)), and the data of all the memory cells MC connected to the word line WLB are output to the bit line pair BLX (X = 1 to m). Then, the data is amplified by the activated sense amplifier 40 (FIG. 2 (j)). Word line WLB
Does not fall during the memory cycle Cr2, but falls during the memory cycle Cr4.

When the column address "P" is given to the column address decoder 26 as described above, the column address decoder 26 applies the corresponding column selection signal YLX.
(X = 1 to n) is raised to a logic level “H” (not shown). Thereby, one transfer gate is ON
Then, the data latch circuit (A) 45 corresponding to the column selection signal YLX is selected. As a result, the data held in the selected data latch circuit (A) 45 is read out to the data bus DB as data “AP” (FIG. 9G). When the data output activation signal OE rises to the logic level “H” and the data output buffer 32 is activated, the data “AP” is held in the data output buffer 32 and the read data “AP” is read.
It is output to the outside as (output data Dout) (FIG. 2
(R), (s)). (3) Memory Cycle Cr3 Subsequently, in the memory cycle Cr3, first, the memory cell MC connected to the word line WLB amplified by the sense amplifier 40 in the memory cycle Cr2.
Of the data latch circuit (B) 4
6 is temporarily held in the same data latch circuit (B) 46 in response to the rise of the timing signal LIB taken into the memory 6 (FIG. 2 (m), (p)). And then, the bit line pair B
LX is precharged.

Next, the memory cell MC connected to the word line WLA held in the data latch circuit (A) 45
Are returned to the sense amplifier 40 in response to the rise of the timing signal LOA for writing the data to the sense amplifier 40 (FIGS. 2 (j) and 2 (o)). Thus, the data of the bit line pair BLX becomes the data of the memory cell MC connected to the word line WLA held in the data latch circuit (A) 45 again. After that, the word line WLA
To the logic level "L", the word line W
The data of the memory cell MC connected to the LA is restored. Then, the bit line pair BLX is precharged again. At this time, the word line WLB is still held in a raised state (FIG. 2 (g)).

Subsequently, the memory cycles Cr1 and Cr
Similarly to 2, the row address “C” is latched in the row address buffer 21 and the column address “R” is latched in the column address buffer 25. Then, the word line WLC rises by the row address decoder 22 (FIG. 2).
(F)), the data of all the memory cells MC connected to the word line WLC are output to the bit line pair BLX. The word line WLC does not fall during the memory cycle Cr3, but falls during the memory cycle Cr5 (not shown).

When the column address "Q" is given to the column address decoder 26 as described above, the column address decoder 26 applies the corresponding column selection signal YLX.
Rise to a logical level "H" (not shown). As a result, one transfer gate is turned ON, the corresponding data latch circuit (B) 46 is selected, and the data held in the selected data latch circuit (B) 46 is set as data “BQ”. The data is read out to the bus DB (FIG. 7G). Then, the data output activation signal OE rises to the logic level “H”, and the data output buffer 32
Is activated, the data "BQ" is held in the data output buffer 32, and the read data "BQ" is read.
Q "(output data Dout) is output to the outside (FIGS. 2 (r) and (s)).

(4) Memory Cycle Cr4 Subsequently, in the memory cycle Cr4, similarly to the memory cycle Cr3, the data latch circuit (A) 4 for the data of the memory cell MC connected to the word line WLC.
5, the data of the memory cell MC connected to the word line WLB held in the data latch circuit (B) 46 is restored, and the read data “CR” is output to the outside of the memory. Thereafter, the read operation of the memory data is performed by this repetition.

As described above, in the memory data read operation of the present embodiment, after one row address is determined, the word line is raised, and the bit line pair data is amplified by the sense amplifier, that is, in the memory cycle Cr2. , From the determination of another row address to the rise of a word line to the amplification of bit line pair data by a sense amplifier.

As shown in the above memory cycle Cr3, pipeline processing can be performed for memory cell data restoration, word line fall, and bit line pair precharge, and row address input is performed at high speed. be able to.

That is, in the present embodiment, the row selection latch circuit 23 and the data latch circuit (A) 4
By providing 5, (B) 46, pipeline processing of memory operation becomes possible. As a result, the memory cycle time τ can be reduced.

Next, the write operation of the memory data will be described with reference to FIG. [2] Write Operation of Memory Data (1) Memory Cycle Cw1 In the memory cycle Cw1 shown in FIG. 3, first, the write data “AP” is latched in the data input buffer 31 in response to the fall of the / RAS signal. (FIGS. 3A and 3D). Subsequently, similarly to the read operation, the row address "A" input from outside the memory is latched in the row address buffer 21, and the / R is output in the next cycle.
The AS signal is held until it falls again (FIG. 3
(E)). In response to the fall of the / CAS signal, the column address "P" also input from the outside of the memory is latched in the column address buffer 25, and in the next cycle / C
The AS signal is held until it falls again (FIG. 3
(B), (f)).

Then, by the row address decoder 22,
The word line WLA rises (FIG. 3F), and the data of all the memory cells MC connected to the word line WLA are output to the bit line pair BLX (X = 1 to m). Then, the data is amplified by the sense amplifier 40 (FIG. 3 (k)). Subsequently, in response to the activation signal WE, the data input buffer 31 supplies the latched input data "AP" to the data bus DB (FIG. 3 (m)).

As described above, in this embodiment,
The word line WLA does not fall during the memory cycle Cw1, but falls during the memory cycle Cw3 as shown in FIG. (2) Memory Cycle Cw2 Subsequently, in the memory cycle Cw2, first, the data amplified by the sense amplifier 40 in the memory cycle Cw1 and the input data “AP” are timing signals for taking the data into the data latch circuit (A) 45. In synchronization with the rise of the LWA, the data is temporarily stored in the data latch circuit (A) 45 (FIGS. 3 (n) and 3 (r)).
Thereafter, the bit line pair BLX is precharged. At this time, the word line WLA is still held in a raised state (FIG. 3 (g)).

Subsequently, in the same manner as in the memory cycle Cw1, the next write data "B" is stored in the data input buffer 31.
"Q" is latched, the row address "B" is latched in the row address buffer 21, and the column address "Q" is latched in the column address buffer 25. Then, the word line WLB rises to the logic level "H" (FIG. 3 (h)) by the row address decoder 22, and the data of all the memory cells MC connected to the word line WLB are output to the bit line pair BLX. The word line WLB does not fall during the memory cycle Cw2, but falls during the memory cycle Cw4.

Subsequently, in response to the activation signal WE, the data input buffer 31 stores the latched input data "B".
"Q" to the data bus DB (FIG. 3 (m)). (3) Memory Cycle Cw3 Subsequently, in the memory cycle Cw3, first, the data and the input data “BQ” of all the memory cells MC connected to the word line WLB amplified by the sense amplifier 40 in the memory cycle Cw2 are These data are temporarily held in the data latch circuit (B) 46 in synchronization with the rise of the timing signal LWB which takes in the data into the data latch circuit (B) 46 (FIGS. 3 (p) and 3 (s)).
Thereafter, the bit line pair BLX is precharged.

Next, the data of the memory cell MC connected to the word line WLA and the input data "AP" held in the data latch circuit (A) 45 are supplied with the rising edge of the timing signal LOA for writing the data to the sense amplifier 40. 3 and are taken in by the sense amplifier 40 (FIG. 3
(K), (r)). Thus, the data of the bit line pair BLX becomes the data held in the data latch circuit (A) 45. After that, when the word line WLA falls, the input data “AP” is written in the selected memory cell MC connected to the word line WLA, and the selected memory cell MC is connected to another unselected memory cell MC connected to the word line WLA. Will restore the previous data. Then, the bit line pair BLX is precharged again. At this time,
The word line WLB is still held in a raised state (FIG. 3 (h)).

Subsequently, similarly to the memory cycles Cw1 and Cw2, the row address "C" is stored in the row address buffer 2
1 and the column address “R” is latched in the column address buffer 25. And the row address decoder 22
As a result, the word line WLC rises (see FIG. 3).
(I), the data of all the memory cells MC connected to the same word line WLC are output to the bit line pair BLX (X = 1 to m). The word line WLC does not fall during the memory cycle Cw3, but falls during the memory cycle Cw5 (not shown).

Subsequently, in response to the activation signal WE,
The data input buffer 31 supplies the latched input data "CR" to the data bus DB (FIG. 3 (m)). (4) Memory Cycle Cw4 Subsequently, in the memory cycle Cw4, similarly to the memory cycle Cw3, the data latch circuit (A) 45 of the data of all the memory cells MC connected to the word line WLC and the input data “CR” 45 , Writing of data of the memory cell MC connected to the word line WLB held in the data latch circuit (B) 46, restoration, and the like. Thereafter, a memory data write operation is performed by repeating this operation.

As described above, in the memory data write operation, for example, in the memory cycle Cw3, the data write and restore of the memory cell MC connected to the word line WLA, which have been performed in the memory cycle Cw1 in the past, are performed. Is performed.

That is, even in the write operation of the memory data, the provision of the row selection latch circuit 23 and the data latch circuits (A) 45 and (B) 46 enables pipeline processing of the memory operation. as a result,
The memory cycle time can be reduced.

As described above, according to the semiconductor memory device of the first embodiment, the following effects can be obtained. (1) By providing the row selection latch circuit 23 and the data latch circuits (A) 45 and (B) 46, it is possible to perform a pipeline process for an operation related to reading or writing of stored data. As a result, the memory cycle time can be reduced.

(2) Precharging and the like of the bit line pair BLX can be performed at an arbitrary timing. That is, the degree of freedom of the timing at which each process is executed increases. this is,
As a result, it contributes to the multi-functionality of the semiconductor memory device.

The first embodiment can be implemented in the following manner. In the first embodiment, the number of data latch circuits provided in one sense amplifier is two. However, the number of data latch circuits may be three or more.
Due to the increase in the number of data latch circuits, the number of pipeline stages increases, and the memory cycle (/ RAS cycle) time can be further reduced. However, if there are two data latch circuits, the above-described pipeline processing can be performed with a minimum configuration.

(Second Embodiment) Next, a second embodiment in which the semiconductor memory device according to the present invention is similarly applied to a DRAM will be described with reference to FIGS. The following description focuses on the differences from the embodiment. Note that also in this case, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will not be repeated.

The difference between the second embodiment and the first embodiment in the structure is as follows. That is, as shown in FIG. 4, instead of the data latch circuit (A) 45 and the data latch circuit (B) 46 shown in FIG.
The difference is that a sense amplifier (A) 41 and a sense amplifier (B) 42 are provided which can independently hold data of memory cells MC connected to two different word lines WL similarly to these data latch circuits. The sense amplifier (A) 41 and the sense amplifier (B) 42 are provided for each bit line pair BL, / BL.
BL is connected via a transfer gate (not shown) so that it can be electrically connected and disconnected.

The operation of the DRAM according to the second embodiment will be described below with reference to the timing charts of FIGS. Note that, also here, the description will be made focusing on differences from the first embodiment. Here, FIG. 5 shows a timing chart of a memory data read operation, and FIG. 6 shows a timing chart of a memory data write operation.

First, a read operation of memory data will be described with reference to FIG. [1] Memory Data Read Operation (1) Memory Cycle Cr1 ′ In the memory cycle Cr1 ′ shown in FIG. 5, after the word line WLA rises as described above, all the memory cells connected to the word line WLA The data of MC is output to the bit line pair BLX (X = 1 to m). Then, the sense amplifier (A) 41 is activated by the sense amplifier activation signal SEA, and the signal TG for connecting the sense amplifier (A) 41 to the bit line pair BLX is provided.
When A rises (FIGS. 5 (i) and (l)), the data output to the bit line pair BLX is transferred to the sense amplifier (A) 41.
And the sense amplifier (A) 41
(FIG. 5 (k), (n)). (2) Memory Cycle Cr2 'Subsequently, in the memory cycle Cr2', after the connection signal TGA falls and the sense amplifier (A) 41 is electrically disconnected from the bit line pair BLX, the bit line pair BLX is turned off. Precharged.

Next, the word line WLB selected by the input row address "B" rises (FIG. 5 (g)).
At this time, the selected state of the word line WLA is held by the row selection latch circuit 23, and the state in which the word line WLA has risen to the logical level “H” is held (FIG. 5).
(F)). Further, data of all the memory cells MC connected to the word line WLB is output to the bit line pair BLX. Then, the sense amplifier (B) 42 is activated by the sense amplifier activation signal SEB, and the signal TGB for connecting the sense amplifier (B) 42 to the bit line pair BLX rises (FIG. 5 (j , (M)), the data output to the bit line pair BLX is amplified by the sense amplifier (B) 42 and latched by the sense amplifier (B) 42 (FIGS. 5 (k), (o)). )).

When column address "P" is applied to column address decoder 26 as described above, column address decoder 26 applies column selection signal YLX corresponding thereto.
(X = 1 to m) is raised to a logic level “H” (not shown). Thereby, one transfer gate is ON
Then, the corresponding sense amplifier (A) 41 is selected. As a result, data “AP” is read from the selected sense amplifier (A) 41 to the data bus DB (FIG. 5).
(P)). When the data output activation signal OE rises to the logic level "H" and the data output buffer 32 is activated, the data "A" is stored in the data output buffer 32.
P ”is latched and read data“ AP ”
It is output to the outside as (output data Dout) (FIG. 5
(Q), (r)). (3) Memory Cycle Cr3 'Subsequently, in the memory cycle Cr3', first, the connection signal TGB falls and the sense amplifier (B) 42 is electrically disconnected from the bit line pair BLX. Is precharged.

Subsequently, when the connection signal TGA rises and the sense amplifier (A) 41 is connected to the bit line pair BLX, the word line W held by the sense amplifier (A) 41 is held.
The data of the memory cells MC connected to the LA are returned to the respective memory cells MC (FIGS. 5 (k) and (l)). After that, the word line WLA is caused to fall, so that the word line WL
The data of the memory cell MC connected to A is restored. Subsequently, the bit line pair BLX is precharged again. At this time, the word line WLB is still held in a raised state (FIG. 5 (g)).

Subsequently, the row address “C” is latched in the row address buffer 21 and the column address “R” is latched in the column address buffer 25. Then, the word line WLC
Rises to the logic level "H" (FIG. 5 (h)), and the data of all the memory cells MC connected to the same word line WLC are output to the bit line pair BLX. The sense amplifier (A) 41 is supplied by the sense amplifier activation signal SEA.
Is activated and the connection signal TGA rises (FIGS. 5 (i) and 5 (l)), the bit line pair BLX
Is amplified by the sense amplifier (A) 41 and latched by the sense amplifier (A) 41 (FIGS. 5 (k) and 5 (n)). Note that the word line WLC
Does not fall during the memory cycle Cr3 ', but falls during the memory cycle Cr5' (not shown).

When column address "Q" is applied to column address decoder 26 as described above, column address decoder 26 applies column selection signal YLX corresponding thereto.
Rise to a logical level "H" (not shown). Thereby, one transfer gate is turned on, and the corresponding sense amplifier (B) 42 is selected. As a result, data "BQ" is read from the selected sense amplifier (B) 42 to the data bus DB (FIG. 5 (p)). When the data output activation signal OE rises to the logic level "H" and the data output buffer 32 is activated, the data "BQ" is latched in the data output buffer 32 and the read data "BQ" (output data Dout). ) Is output to the outside (FIGS. 5 (q) and 5 (r)).

(4) Memory Cycle Cr 4 ′ Subsequently, in the memory cycle Cr 4 ′, the sense amplifier (A) of the data of all the memory cells MC connected to the word line WLC, similarly to the memory cycle Cr 3 ′.
Holding at 41, restoring data of the memory cell MC connected to the word line WLB held at the sense amplifier (B) 42, reading data "CR" out of the memory, and the like are performed. Thereafter, the read operation of the memory data is performed by this repetition.

As described above, also in the memory data read operation of the second embodiment, one row address is determined, a word line is raised, and after a bit line pair data is amplified by a sense amplifier, that is, the memory data is read. Recycle C
At r2 ', it becomes possible to perform a pipeline process from the determination of another row address to the rise of a word line and the amplification of bit line pair data by a sense amplifier.

As shown in the memory cycle Cr3 ', pipeline processing is also possible for memory cell data restoration, word line fall, and bit line pair precharge, so that row address input can be performed at high speed. It can be carried out.

That is, also in the second embodiment, by providing the row selection latch circuit 23 and the two sense amplifiers (A) 41 and (B) 42, the pipeline processing of the read operation can be performed. It becomes possible.
As a result, the memory cycle time can be reduced.

Next, the write operation of the memory data will be described with reference to FIG. [2] Memory Data Write Operation (1) Memory Cycle Cw1 'In the memory cycle Cw1' shown in FIG.
The write data "AP" is latched at 1 (FIG. 6).
(A), (d)). Subsequently, similar to the read operation,
Row address "A" input from outside the memory is latched in row address buffer 21, and in the next cycle, / RAS
The signal is held until the signal falls again (FIG. 6E).
When the / CAS signal falls, the column address “P” also input from outside the memory is stored in the column address buffer 2.
5 and held until the / CAS signal falls again in the next cycle (FIGS. 6B and 6F).

Then, based on the latch data of the row address buffer 21, the row address decoder 22
The word line WLA rises (FIG. 6 (g)), and the data of all the memory cells MC connected to the word line WLA are output to the bit line pair BLX (X = 1 to m).

Similarly to the above-mentioned read operation, the sense amplifier (A) 41 is activated by the sense amplifier activation signal SEA and the signal for connecting the sense amplifier (A) 41 to the bit line pair BLX. When the TGA rises (FIGS. 6 (j) and 6 (o)), the data output to the bit line pair BLX is amplified by the sense amplifier (A) 41 and latched by the sense amplifier (A) 41. (FIG. 6 (l), (s)).

In response to the activation signal WE, the data input buffer 31 outputs the latched input data “A”.
"P" to the data bus DB (FIG. 6 (n)). Then, with the rise of the timing signal SWA for writing this write data to the sense amplifier (A) 41,
Sense amplifier (A) 41 with the same data “AP” selected
(FIG. 6 (s)).

The word line WLA does not fall during the memory cycle Cw1 ', but falls during the memory cycle Cw3' as shown in FIG. (2) Memory Cycle Cw2 'Subsequently, in the memory cycle Cw2', the connection signal TGA falls as in the case of reading, and after the sense amplifier (A) 41 is electrically disconnected from the bit line pair BLX, The line pair BLX is precharged.

Subsequently, in the same manner as in the memory cycle Cw1 ', the next write data "B" is stored in the data input buffer 31.
Q "is latched. Further, the row address “B” is latched in the row address buffer 21, and the column address “Q” is latched in the column address buffer 25. Then, the word line WLB rises (FIG. 6 (h)), and the word line WLB rises.
Are output to the bit line pair BLX.

Then, similarly to the memory cycle Cw1 ', the sense amplifier (B) 42 is activated by the sense amplifier activation signal SEB, and the connection between the sense amplifier (B) 42 and the bit line pair BLX is established. Signal T for performing
When GB rises (FIGS. 6 (k) and 6 (q)), the data output to the bit line pair BLX is applied to the sense amplifier (B) 4.
2 and the sense amplifier (B) 4
2 (FIG. 6 (l), (t)).

In response to the activation signal WE, the data input buffer 31 outputs the latched input data "B".
"Q" to the data bus DB (FIG. 6 (n)). Then, with the rise of the timing signal SWB for writing the write data to the sense amplifier (B) 42,
The sense amplifier (B) 42 in which the same data “BQ” is selected
(FIG. 6 (t)).

The word line WLB does not fall during the memory cycle Cw2 ', but falls during the memory cycle Cw4'. (3) Memory Cycle Cw3 'Subsequently, in the memory cycle Cw3', the connection signal T
With the fall of GB, the sense amplifier (B) 42 is electrically disconnected from the bit line pair BLX, and thereafter, the bit line pair BLX is precharged.

Subsequently, during the rising period of the connection signal TGA, the data of the non-selected memory cell MC connected to the word line WLA held in the sense amplifier (A) 41 and the input data “AP” of the selected memory cell. Are written into the memory cells MC (FIG. 6 (o),
(L)). After that, the word line WLA falls, thereby causing the memory cells MC connected to the word line WLA to fall.
Is restored and written. Then, the bit line pair BLX is precharged again. At this time, the word line WLB is maintained in a state where it is still raised (FIG. 6 (h)).

Subsequently, the write data "CR" is latched in the data input buffer 31 (FIG. 6D). Then, the row address “C” is latched in the row address buffer 21 and the column address “R” is latched in the column address buffer 25. Then, the word line WLC rises (FIG. 6).
(I), the data of all the memory cells MC connected to the same word line WLC are output to the bit line pair BLX. Note that the word line WLC does not fall during the memory cycle Cw3 ', and the memory cycle Cw5' does not fall.
It falls during the period (not shown).

When the sense amplifier (A) 41 is activated by the sense amplifier activation signal SEA and the connection signal TGA rises (FIG. 6 (j),
(O)), the data output to the bit line pair BLX is amplified by the sense amplifier (A) 41 and latched by the sense amplifier (A) 41 (FIG. 6 (l),
(S)).

In response to the activation signal WE, the data input buffer 31 outputs the latched input data "C".
R "to the data bus DB (FIG. 6 (n)). Then, with the rise of the timing signal SWA for writing this write data to the sense amplifier (A) 41,
Sense amplifier (A) 41 with the same data “CR” selected
(FIG. 6 (s)).

(4) Memory Cycle Cw4 'Subsequently, in the memory cycle Cw4', similarly to the memory cycle Cw3 ', the bit line pair BLX is precharged and the word line WLB held in the sense amplifier (B) 42 is held. The data writing and restoration of the memory cell MC connected to the memory cell MC are performed. Thereafter, a memory data write operation is performed by repeating this operation.

As described above, in the memory data write operation, for example, in the memory cycle Cw3 ′, data write to the memory cell MC connected to the word line WLA, which has been performed in the conventional memory cycle Cw1 ′, is performed. And restoration are performed.

That is, even in the write operation of the memory data, by providing the row selection latch circuit 23 and the two sense amplifiers (A) 41 and (B) 42, pipeline processing of the memory operation can be performed. Become. As a result, the memory cycle time can be reduced.

As described above, according to the semiconductor memory device of the second embodiment, the following effects can be obtained. (1) By providing the row selection latch circuit 23 and the two sense amplifiers (A) 41 and (B) 42, it is possible to perform a pipeline process of an operation related to reading or writing of stored data. As a result, the memory cycle time can be reduced.

(2) Precharging and the like of the bit line pair BLX can be performed at an arbitrary timing. That is, the degree of freedom of the timing at which each process is executed increases. The second embodiment can be implemented in the following modes.

In the second embodiment, two sense amplifiers are provided for one bit line pair BL and / BL. However, the number of sense amplifiers may be three or more. As the number of sense amplifiers increases, the number of pipeline stages increases, and the memory cycle (/ RAS cycle) time can be further reduced. However, if there are two sense amplifiers, the above-described pipeline processing can be performed with a minimum configuration.

In addition, the following elements can be commonly changed in the above embodiments. In the above embodiments, two data latch circuits (A) and (B) or two sense amplifiers are used as means for holding data output to each bit line pair with activation of a word line. Although examples of (A) and (B) are shown, the data holding means is not limited to these.
The point is that the data of the memory cell connected to the activated word line can be held for an arbitrary time without being restricted by the memory cycle time.

In each of the above embodiments, an example is shown in which a row address decoder is provided with a selection latch circuit for holding a state of a selected word line for an arbitrary period. However, the present invention is not limited to this. The point is that the selection latch circuit capable of holding the state of the signal line selected by the address decoder for an arbitrary period in the row direction or the column direction may be provided separately for each of the corresponding signal lines. .

In each of the above embodiments, the DRAM
The case where the semiconductor memory device according to the present invention is applied has been described above, but the present invention is not limited to this. The semiconductor memory device according to the present invention includes an SRAM, an EEPR
It can be applied to all RAMs and ROMs such as OM.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a first embodiment of a semiconductor memory device according to the present invention;

FIG. 2 is a timing chart showing a data read operation of the semiconductor memory device according to the first embodiment;

FIG. 3 is a timing chart showing a data write operation of the semiconductor memory device according to the first embodiment;

FIG. 4 is a block diagram schematically showing a configuration of a second embodiment of the semiconductor memory device according to the present invention;

FIG. 5 is a timing chart showing a data read operation of the semiconductor memory device according to the second embodiment;

FIG. 6 is a timing chart showing a data write operation of the semiconductor memory device according to the second embodiment;

FIG. 7 is a block diagram schematically showing a configuration of a conventional semiconductor memory device.

FIG. 8 is a timing chart showing a memory cycle of the conventional semiconductor memory device.

[Explanation of symbols]

10 memory cell array section, 20 address specifying section, 2
1 ... row address buffer, 22 ... row address decoder,
23: row selection latch circuit, 25: column address buffer,
26: column address decoder, 30: data input / output unit, 3
1 data input buffer, 32 data output buffer
40: sense amplifier, 41: sense amplifier (A), 42
... sense amplifier (B), 45 ... data latch circuit (A), 46 ... data latch circuit (B), 50 ... signal generation circuit.

Claims (7)

[Claims] 1. A memory cell array section comprising a plurality of signal lines crossing each other, a plurality of memory cells formed at intersections of the signal lines, and a plurality of signal lines arranged in at least the same direction among the plurality of signal lines. And an address decoder for selecting one signal line from a group of signal lines to be selected, wherein the address decoder includes a selection latch circuit for holding a state of the selected signal line for an arbitrary period for each corresponding signal line. A semiconductor memory device provided separately. 2. A memory cell array section comprising a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells formed at intersections thereof, and selecting one word line from the plurality of word lines. A row address decoder, and a sense amplifier connected to each of the plurality of bit line pairs, wherein the row address decoder includes a row selection latch for holding a state of the selected word line for an arbitrary period. A semiconductor memory device comprising a circuit separately for each corresponding word line. 3. The semiconductor memory device according to claim 2, further comprising data holding means for holding data of a memory cell connected to the selected word line for an arbitrary period. 4. The data holding means according to claim 3, wherein said data holding means comprises a plurality of data latch circuits provided in said sense amplifier and latching data of memory cells connected to different word lines. Semiconductor storage device. 5. The semiconductor memory device according to claim 4, wherein said data latch circuit comprises two. 6. The semiconductor memory device according to claim 3, wherein said data holding means comprises a plurality of sense amplifiers provided for each of said bit line pairs. 7. The semiconductor memory device according to claim 6, wherein two sense amplifiers are provided for each bit line pair.