JP2001166991A - Memory controller and memory module and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller and a memory module for improving random access performance by using a conventional memory element in a memory controller and a memory module for performing access to a memory element capable of performing random access. SOLUTION: This memory controller is provided with a virtual bank memory 25 with a small capacity constituted of more banks than those of a memory 19, and a memory controller 18 is arranged between the memory 19 and the virtual bank memory 25 so that it is possible to perform access through the virtual bank memory 25 to the memory 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, a memory module, and an information processing device, and more particularly, to a memory control device, a memory module, and an information processing device for accessing a memory element that can be randomly accessed. In recent years, with the speeding up of processors, it has been desired to speed up access to memory modules. When speeding up access to the memory module, it is effective to increase the number of banks.

However, a general memory element generally has about four banks, and it is difficult to increase the number of banks to four or more, which hinders improvement in access performance.

[0003]

2. Description of the Related Art A conventional memory module generally has a four-bank configuration, and the capacity of one bank increases as the capacity of a memory element increases, whereby data on the same row address is continuously read. When writing / writing, data can be read / written only by changing the column address, so that high-speed access has been possible.

[0004]

However, the conventional memory device has a small number of banks, usually about 4 banks, and a large capacity of one bank. Therefore, in random access, when a different row address of a specific bank is accessed in random access. However, since both the row address and the column address are reset, the latency increases and the access speed cannot be increased.

In order to perform random access at high speed,
What is necessary is just to increase the number of banks of the memory element. However, it is not easy to increase the number of banks of the memory element in terms of the chip size and the price of the memory element. The present invention has been made in view of the above points, and has as its object to provide a memory control device, a memory module, and an information processing device that can improve random access performance using a conventional memory element.

[0006]

According to a first aspect of the present invention, there is provided a memory control device for accessing an external memory device, comprising: a virtual bank buffer having a larger number of banks than the external memory device and having a smaller capacity; Access control means for accessing the memory element via the buffer.

According to a second aspect of the present invention, when the virtual bank buffer is accessed by the access control means and there is no necessary data in the virtual bank buffer, the memory element starts from a position corresponding to the virtual bank buffer. The data is read, output to the outside, and controlled to be stored in the virtual bank buffer. A memory module which has a memory element and accesses the memory element to read and write data is provided with a virtual bank buffer having a larger number of banks and a smaller capacity than the memory element, and the virtual bank buffer. Access control means for accessing the memory device via the memory device.

According to a fourth aspect of the present invention, when the virtual bank buffer is accessed by the access control means and there is no necessary data in the virtual bank buffer, the memory element starts from a position corresponding to the virtual bank buffer. The data is read, output to the outside, and controlled to be stored in the virtual bank buffer. 6. An information processing apparatus having a memory element and accessing the memory element to process data, the virtual bank buffer having a larger number of banks and a smaller capacity than the memory element, and the virtual bank buffer. And access control means for accessing the memory element through the memory.

According to a sixth aspect of the present invention, when the virtual bank buffer is accessed by the access control means and there is no necessary data in the virtual bank buffer, the memory element starts from a position corresponding to the virtual bank buffer. The data is read, output to the outside, and controlled to be stored in the virtual bank buffer. According to the first, third, and fifth aspects of the present invention, the memory device is configured to have a larger number of banks than the memory device, and the memory device is accessed through a small-capacity virtual bank buffer. Therefore, random access performance can be improved.

According to the second, fourth, and sixth aspects, when there is no necessary data in the virtual bank buffer, the data is read from the memory element at a position corresponding to the virtual bank buffer, output to the outside, and By controlling the data to be stored in the bank buffer, necessary data is directly read from the memory element, so that data can be read even when the required data does not exist in the virtual bank buffer.

[0011]

FIG. 1 is a block diagram showing an embodiment of the present invention. The information processing system 1 according to the present embodiment includes a motherboard 2, a processor 3, a memory module 4, a graphics board 5, a display 6, a hard disk drive 7, a floppy disk drive 8, and a CD-ROM.
It comprises a ROM drive 9, a keyboard 10, and a mouse 11.

The motherboard 2 has a processor 3, a memory module 4, a graphics board 5, a hard disk drive 7, a floppy disk drive 8, and a CD.
A ROM drive 9, a keyboard 10, a mouse 11 and the like are connected to control each unit. The motherboard 2 includes a north bridge controller 12, a south bridge controller 13, an I / O controller 14, a ROM 15, and the like. The north bridge controller 12 controls connection between the processor 2, the memory module 4, the graphics board 5, and the south bridge 13.

The south bridge 13 controls connection of the I / O controller 14, ROM 15, hard disk drive 7, floppy disk drive 8, and CD-ROM drive 9. The I / O controller 14
It controls input and output between the south bridge 13 and input devices such as the keyboard 10 and the mouse 11, serial and parallel connectors, and the like. The ROM 15 stores a startup program and the like. The startup program stored in the ROM 15 is executed by the processor 3 at startup. The system is started by executing the start program.

The processor 3 processes data according to a desired program. The memory module 4 is used as a storage area for processing in the processor 3. The graphics board 5 is connected to the north bridge 12 and controls the screen display on the display 6 according to the processing of the processor 3. The hard disk drive 7 has a built-in hard disk and stores data processing results in the processor 3. A floppy disk 16 is mounted on the floppy disk drive 8, and provides data stored in the floppy disk 16 to the processor 3,
The data processed by the processor 3 is stored.

The CD-ROM drive 9 has a CD-RO
The M17 is attached, reads data recorded on the CD-ROM 17, and provides the data to the processor 3. Keyboard 1
0 and the mouse 11 are used to input commands and data. Next, the memory module 4 which is a main part of the present embodiment will be described.

FIG. 2 is a block diagram showing a memory module according to an embodiment of the present invention. The memory module 4 includes a memory control device 18 and a memory 19. The memory control device 18 is formed of one semiconductor chip, has virtual banks of a multi-bank configuration, and controls access to the memory 19 according to the set virtual bank configuration.

The memory 19 is composed of, for example, a synchronous DRAM having a 4-bank configuration, and a memory controller 18.
The writing and reading of data are controlled in accordance with the access from. The memory control device 18 includes the bank selection circuit 2
0, external memory control circuit 21, data selection circuit 22, I
/ O buffers 23-1 to 23-4, a virtual bank control circuit 24, and a virtual bank memory 25.

The bank selection circuit 20 is connected to the north bridge controller 12 of the motherboard 2, and receives a chip select signal CS #, a write enable signal WE #, a column address strobe signal C via a memory bus.
AS #, a row address strobe signal RAS #, addresses A0 to Axx, and BA0 to Axx are supplied. The bank selection circuit 20 controls the external memory control circuit 21, the data selection circuit 22, and the virtual bank control circuit 24 according to the addresses A0 to Axx and BA0 to Axx supplied from the north bridge controller 12.

The external memory control circuit 21 has a chip select signal CS #, a write enable signal WE #, and a column address strobe signal CA for accessing the memory 19 in accordance with the bank selected by the bank selection circuit 20.
S #, a row address strobe signal RAS #, addresses A0 to Axx, and BA0 to BAxx are generated and supplied to the memory 19.

The exchange of data DA0-DAxx with the motherboard 2 is performed via I / O buffers 23-1, 23-2. Further, data DB0 to DBxx with the memory 19 are stored.
Are exchanged via the I / O buffers 23-3 and 23-4. Also, the I / O buffers 23-1 to 23-
4 is connected to the data selection circuit 22. The data selection circuit 22 selects an input / output destination of the data DA0 to DAxx and the data DB0 to DBxx according to a control signal from the bank selection circuit 20. The data selection circuit 22 includes the bank selection circuit 20
Supplies the data DA0 to DAxx to both the virtual bank memory 25 and the memory 19 or to the virtual bank memory 25 in response to the control signal from the CPU.

The data selection circuit 22 includes a bank selection circuit 2
The data DA0 to DAxx are supplied to both the virtual bank memory 25 and the memory 19 or the port 2 or the port 1 of the virtual bank memory 25 in response to a control signal from 0. Also,
The data selection circuit 22 stores data DB0 to DBxx in the virtual bank memory 2 in accordance with a control signal from the bank selection circuit 20.
5 and motherboard 2 or virtual bank memory 25
To port 1 or port 2.

The virtual bank control circuit 24 selects a bank of the virtual bank memory 25 in response to a control signal from the bank selection circuit 20, and selects a column address.
Data DA0 to DAxx supplied from the data selection circuit 22
And write / read data DB0 to DBxx to / from the virtual bank memory 25 and control the ports 1 and 2. The virtual bank memory 25 has, for example, a multi-bank configuration of N (N> 4) banks and a small-capacity dual-port RAM having a data length m. The motherboard 2 recognizes the virtual bank memory 25 as a memory bank configuration.

FIG. 3 is a diagram for explaining a storage area of a memory module according to one embodiment of the present invention. Memory 19
Is composed of m memory devices 26-1 to 26-m. Each of the memory devices 26-1 to 26-m is divided into four banks B1 to B4, and data is input / output with an n-bit width.

The virtual bank memory 25 is composed of data of N banks B11 to B1N having a width of n.times.m bits. The correspondence between the memory 19 and the virtual bank memory 25 is managed by a register 20 a provided in the bank selection circuit 20. The register 20a is managed in the order of priority of the banks B11 to B1N of the virtual bank memory 25. Register 20
In a, the bank of the virtual bank memory 25, the bank B of the memory 19 corresponding to the bank of the virtual bank memory 25, and the row address Rx of the bank of the memory 19 corresponding to the bank of the virtual bank memory 25 are stored in the order of priority.

In FIG. 3, as the highest priority, the data of the row address Rx of the bank B1 of the memory 19 is stored in the bank B11 of the virtual bank memory 25, and the banks B12... B1N of the virtual bank memory 25 are empty. Is shown. Next, the operation of the bank selection circuit 20 will be described. FIG. 4 is a flowchart showing the processing of the bank selection circuit according to one embodiment of the present invention.

In the bank selection circuit 20, the motherboard 2
Is supplied (step S1), it is determined whether the supplied command is an active command, a read command, a write command, a precharge command, or another command (steps S2 to S6). The active command specifies a bank to be accessed in the virtual bank memory 25 before the read / write command. The read command instructs to read data from a corresponding address of the bank specified by the active command of the virtual bank memory 25.

The write command is transmitted to the virtual bank memory 25
Instructs to write data to the corresponding address of the bank specified by the active command of The precharge command is a command for precharging the bank specified by the active command after read / write. When the active command is recognized in step S2, it is determined whether or not the bank specified by the active command has been allocated to the register 20a to the virtual bank memory 25 (step S7). The determination in step S7 is performed in the
This is performed by determining whether the bank of the memory 25 corresponding to the virtual bank memory 25 of a and the row address Rx is empty.

In step S7, if the contents of the corresponding virtual bank memory 25 are empty in the register 20a, the corresponding bank of the memory 19 is allocated to the virtual bank memory 25, and data of a predetermined row address is written (step S8). . After assigning the corresponding bank and row address of the memory 19 to the virtual bank memory 25 in step S8,
The contents of the register 20a are updated so that the bank of the virtual bank memory 25 allocated in step S8 has the highest priority (step S9).

If the bank of the virtual bank memory 25 has already been allocated in step S7, the bank priority is adjusted so that the bank to be activated has the highest priority (step S7). S1
0), update the contents of register 20a accordingly. Next, in step S3, when the read command is recognized,
It is determined whether or not data to be accessed exists in the designated bank of the virtual bank memory 25 (step S11). In accessing the virtual bank memory 25, it is necessary to cope with random access that can occur at the same row address during burst transfer. Thus, the determination in step S11 is made by comparing the contents of the burst transfer status register 20b incorporated in the bank selection circuit 20 with the column address.

FIG. 5 is a diagram for explaining the operation of the memory module according to one embodiment of the present invention. The minimum value Acmin and the maximum value Acmax of the column address of the data stored in the virtual bank memory 25 are stored in the burst transfer status register 20 b built in the bank selection circuit 20. Motherboard 2
The address Acx specified by the column address recorder 20c incorporated in the bank selection circuit 20 with the address Acx and the minimum value Acmin and the maximum value Acmax of the column address stored in the burst transfer status register 20b are compared with the address Acx. Is the minimum column address Acm
If the value is between in and the maximum value Acmax, it is determined that there is data to access the virtual bank, and the address A
If cx is not between the minimum value Acmin and the maximum value Acmax of the column address, it is determined that there is no data to access the virtual bank.

Returning to FIG. 4, the description will be continued. Step S1
In step 1, if there is data corresponding to the corresponding virtual bank in the virtual bank memory 25, the data is read from the virtual bank memory 25 and output (step S12). In step S11, if there is no corresponding data in the corresponding bank of the virtual bank memory 25, that is, data of a different bank in the memory 19 and data of a row address are written in the corresponding bank of the virtual bank memory 25. In this case, the corresponding data is read from the memory 19 by controlling the external memory control circuit 21 and read to the motherboard 2 via the data selection circuit 22, and the virtual bank memory 25 is read via the data selection circuit 22.
Is written to the corresponding virtual bank (step S
13).

Next, when a write command is recognized in step S4, data is written to the designated virtual bank memory 25 in the virtual bank (step S14). Next, in step S5, when the precharge command is supplied, the priority is adjusted so that the priority of the virtual bank of the virtual bank memory 25 to which read / write has been performed by the read command or the write command becomes the highest priority ( Step S1
5) Update the register 20a. The register 20
The data of the lowest virtual bank registered in a is saved in the memory 19 (step S16).

Next, if another command is recognized in step S6, another command is executed (step S6).
17). Next, the read processing of the above processing will be described with reference to a timing chart. FIG. 6 shows a timing chart of the memory module according to one embodiment of the present invention. FIG. 6A is a timing for issuing a read command, FIG. 6B is a timing for reading data, and FIG.
(D) is the access timing of the memory 19, FIG.
(E) and (F) show the access timing of the virtual bank memory 25.

When the read commands Cr1 and Cr2 are issued at the time t1, the memory 1 is read as shown in FIGS.
Nine corresponding banks are activated. At this time,
When the data D1 corresponding to the read commands Cr1 and Cr2 does not exist in the virtual bank memory 25, FIG.
As shown in (D), at time t2, the corresponding data D1 is read from the memory 19, and as shown in FIG. 6 (B), the data D1 is stored in the memory module 4 by the data selection circuit 22.
And output to the motherboard 2.

At this time, as shown in FIG. 6 (E), data D1 to D4 corresponding to the data length of the virtual bank memory 25 of the same memory 19 are read out, and as shown in FIG. It is stored in one virtual bank B11 of the bank memory 25. Therefore, the data D1 corresponding to the read command Cr1 is read from the memory 19, but the data D2 corresponding to the read command Cr2 is
9 is read out from the virtual bank memory 25 because it is stored in the virtual bank B11 of the virtual bank memory 25.
From the virtual bank B11.

Next, at time t3, when read commands Cr5, Cr3, and Cr7 of different virtual banks are successively supplied, the corresponding bank of the memory 19 is activated. At this time, since data corresponding to the read command Cr5 does not exist in the virtual bank memory 25, FIG.
As shown in (D), at time t4, data D5 corresponding to the read command Cr5 is read, and as shown in FIG. 6 (B), data D5 is output from the memory module 4 by the data selection circuit 22 and transmitted to the motherboard 2. Supplied.

At this time, as shown in FIG. 6E, data D5 to D8 corresponding to the data length of the virtual bank memory 25 of the memory 19 are read out, and as shown in FIG. 25 are stored in one virtual bank B12. Read command Cr3 following read command Cr5
Is stored in the virtual bank B11 of the virtual bank memory 25 at the time of reading data from the memory 19 at time t2, so that the data D3 read from the virtual bank B11 is output as shown in FIG. You.

The data D7 corresponding to the read command Cr7 is stored in the virtual bank B12 of the virtual bank memory 25 when the data D5 is read from the memory 19, and thus is read from the virtual bank B12 of the virtual bank memory 25. For example, conventionally, read commands Cr5, Cr
Between 3 and Cr7, latency from bank active to data output and latency for reactivating the same bank from bank precharge occurred.
In this embodiment, since the latency can be hidden by using the virtual bank as described above, the random access performance can be improved.

As described above, when data that does not exist in the virtual bank memory 25 is read, the requested data is directly output from the memory 19, and the virtual banks B11 and B12 are stored in the corresponding virtual banks B11 and B12. Random access performance can be improved by simultaneously writing continuous data to data requested by the data length.

The present embodiment includes an invention in which the access control means controls to rewrite the data stored in the virtual bank buffer according to the priority set according to the access frequency. According to the present invention, data can be read directly from the virtual bank buffer by rewriting the data stored in the virtual bank buffer according to the priority set according to the access frequency, so that random access performance can be improved. .

Further, the present embodiment includes an invention in which the access control means controls to pre-read data from the external memory element to the virtual bank buffer in response to the access to the virtual bank buffer. According to the present invention, the virtual bank buffer can be used in the same manner as the multi-bank memory element by controlling the data to be read from the memory element to the virtual bank buffer in advance in response to the access to the virtual bank buffer. Therefore, random access performance can be improved.

[0042]

As described above, according to the first, third, and fifth aspects of the present invention,
According to the method, the memory element can be virtually treated as a multi-bank configuration by accessing the memory element through a virtual bank buffer having a smaller capacity and a larger number of banks than the memory element. It has features such as the ability to be improved.

According to the second, fourth, and sixth aspects, when there is no necessary data in the virtual bank buffer, the data is read from the memory element at a position corresponding to the virtual bank buffer, output to the outside, and By controlling the data to be stored in the bank buffer, necessary data is directly read from the memory element. Therefore, even when the required data does not exist in the virtual bank buffer, the data can be read, thereby improving the random access performance. Features such as

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a memory module according to one embodiment of the present invention.

FIG. 3 is a diagram for explaining a storage area of a memory module according to one embodiment of the present invention.

FIG. 4 shows a processing flowchart of a bank selection circuit according to one embodiment of the present invention.

FIG. 5 is an explanatory diagram of an operation of the memory module according to one embodiment of the present invention.

FIG. 6 is a timing chart of the memory module according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Information processing system 2 Motherboard 3 Processor 4 Memory module 5 Graphics boat 6 Display 7 Hard disk drive 8 Floppy disk drive 9 CD-ROM drive 10 Keyboard 11 Mouse 18 Memory controller 19 Memory 20 Bank selection circuit 20a Register 20b Burst transfer status register 20c column address decoder 21 external memory control circuit 22 data selection circuit 23-1 to 23-4 I / O buffer 24 virtual bank control circuit 25 virtual bank memory

Claims (6)

[Claims] 1. A memory control device for accessing an external memory element, writing data to the external memory element, and reading data from the external memory element, comprising: a multi-bank configuration having a smaller capacity than the external memory element; A memory control device comprising: a virtual bank buffer; and access control means for accessing the external memory element via the virtual bank buffer. 2. The access control means, when accessing the virtual bank buffer, if there is no necessary data in the virtual bank buffer, the access control means stores the data from a position corresponding to the virtual bank buffer in the memory element. 2. The memory control device according to claim 1, wherein the memory control device reads the data, outputs the data to the outside, and stores the data in the virtual bank buffer. 3. A memory module having a memory element and reading and writing data by accessing the memory element, comprising: a virtual bank buffer having a larger number of banks than the memory element and having a smaller capacity; A memory module having access control means for accessing the memory element through the memory module. 4. When the virtual bank buffer is accessed and there is no necessary data in the virtual bank buffer when accessing the virtual bank buffer, the access control means stores the data from a position corresponding to the virtual bank buffer in the memory element. 4. The memory module according to claim 3, wherein the memory module reads the data, outputs the data to the outside, and stores the data in the virtual bank buffer. 5. An information processing apparatus having a memory element and processing data by accessing the memory element, comprising: a virtual bank buffer having a larger number of banks than the memory element and having a smaller capacity; Access control means for accessing the memory element via a buffer. 6. When the virtual bank buffer is accessed and there is no necessary data in the virtual bank buffer when accessing the virtual bank buffer, the access control means stores the data from a position corresponding to the virtual bank buffer in the memory element. 6. The information processing apparatus according to claim 5, wherein the information is read, output to the outside, and stored in the virtual bank buffer.