JP2001156763A - Preamble addition circuit and optical transmitter- receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical transmitter-receiver where a preamble is generated by hardware so as to reduce software development man-hours and that is applicable to an optical fiber communication network provided with a passive optical multiplexing path. SOLUTION: The preamble addition circuit of this invention is provided with 1st and 2nd delay circuits that delay both a transmission request signal and data to be sent by a prescribed time and with a device that generates a synchronizing signal for the prescribed delay time and also with a device that is triggered by the transmission request signal to continue transmission for a 2nd prescribed time and with a mechanism that transmits an idle signal as its control when the transmission request signal goes to a low level within the 2nd prescribed time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical transceiver used for optical communication. In particular, it relates to a preamble generation circuit for forming a synchronization header (preamble).

[0002]

2. Description of the Related Art An example of an optical fiber communication network system using a passive optical branch circuit is shown in FIG.
Stations 120 , 121 , 122 , and 12 including optical transmitters
3 are connected via a passive optical branching path 124 . In an optical fiber communication network system using a passive type optical branch, when there is no signal (packet) to be transmitted, each station must not transmit an optical signal to the network side. Therefore, at the rising portion of the packet, FIG.
As shown in (b), a header portion (preamble) 131 of the packet 130 is provided. The header part (preamble) is a mechanism that provides a preparation period for stable transmission and reception by the automatic output control mechanism (APC) of the transmission unit of the optical transceiver and the phase synchronization circuit (PLL) of the reception unit. It is. Conventionally, this preamble has been generated by software.

[0003]

The length required for the preamble actually depends on the hardware. For example, APC
And the response speed of the PLL and the encoding format. Rewriting software one by one in response to hardware has led to an increase in product development man-hours.

[0004]

In order to solve the above-mentioned problems, a preamble adding circuit according to the present invention comprises first and second delay circuits for delaying both a transmission request signal and data to be transmitted for a predetermined time, and a predetermined delay circuit. A mechanism for generating a synchronization signal during the delay time. Further, a mechanism for continuing the transmission state for a second predetermined time triggered by the transmission request signal is provided,
A mechanism is provided for controlling to transmit an idle signal when the transmission request signal falls to a low level within the second predetermined time.

[0005] Preambles can be inserted while the data to be transmitted is being delayed. In addition, if the transmission time is within the second predetermined time, an idle signal is inserted during a period in which the transmission request is interrupted, so that the minimum packet duration can be set to the second predetermined time or more.

[0006]

Embodiments of the present invention will be described below. First Embodiment FIG. 1 shows an optical transceiver 10 with a packet generation mechanism according to a first embodiment of the present invention. Medium control device (MA
C) Optical transmission / reception module 1 with packet generation mechanism from 1
Toward 0, data to be transmitted (TX-DATA) is output, for example, in 8-bit parallel. The transmission request signal (TX_E) indicates that data to be transmitted exists.
N) is also output from the medium control device (MAC) 1 to the optical transmission / reception module 10 with a packet generation mechanism. A preamble is added by the preamble adding circuit 2 to the data to be transmitted. Then, after being converted into a serial signal by the serial / parallel converter (SERDES) 3,
After being converted into an optical signal by the optical transceiver 4, it is transmitted to the optical fiber 6 via the optical coupler 5. The optical signal transmitted through the optical fiber 6 passes through an optical coupler 5, an optical transceiver 4, and a serial / parallel converter (SERDES) 3, and is converted into a parallel signal (RX-D).
ATA) and then sent to the media controller (MAC) 1.

The preamble adding circuit 2 is a circuit that performs an operation of delaying data from the medium control device (MAC) 1 by a first-in first-out memory for a predetermined time and inserting a header (preamble) during the delay time.

FIG. 2 is a diagram illustrating the internal structure of FIG. 1 in more detail. The preamble adding circuit 2 includes first-in first-out memories 21 and 22, an OR gate 23, and a one-side negative input AND gate 24.

As shown in FIG. 2, a serial-to-parallel converter (S
The ERDES 3 includes an encoder 31, a serializer (parallel-serial converter) 32, a decoder 34, and a deserializer (serial-parallel converter) 33. The encoder 31 and the decoder 34 encode / decode the 8-bit data signal into, for example, an 8B / 10B code.
Further, the encoder 31 has a function of generating a special code (a code called a K character in an 8B / 10B code) using an external signal.

Further, the inside of the optical transceiver 4 has a gate 46,
It comprises a laser drive circuit 43, a laser diode 41 with a built-in monitoring photodiode, an automatic output control circuit 45, a photodiode with a built-in preamplifier 42, and a post-amplifier 44 for waveform shaping (see FIG. 2).

FIG. 3 is a timing chart showing the operation of the preamble adding circuit 2 of FIG. The first-in first-out memories 21 and 22 have the same depth, and 8-bit parallel data is sent to the first-in-first-out memory 21 and the TX_EN signal is sent to the first-in-first-out memory 22. These first-in first-out memories 21 and 22 operate as delay circuits.

FIG. 3A shows the TX_EN signal and FIG.
(B) shows the first-in first-out memory 22 output. It can be seen that the signal is delayed. FIG. 3D shows OPT_E.
This signal enables the optical transceiver 4 to transmit the N signal. This OPT_EN signal is obtained by ORing the TX_EN signal and the output of the first-in first-out memory 22 with the OR gate 23. The gate 46 in the optical transceiver 4 is opened and closed by the OPT_EN signal.

FIG. 3C shows a Preamble_EN signal obtained by using a one-sided negative input AND gate 24 to perform an AND operation on the OPT_EN signal and the output of the first-in first-out memory 22. The Preamble_EN signal is applied to the encoder 31, and when the Preamble_EN signal is high, a special code, for example, a K28.5 code is generated.

The data signal sent from the medium control device (MAC) 1 is delayed by a first-in first-out memory 21,
Since the Preamble_EN signal is high during the delay, the output of the encoder 31 is a K28.5 code. Then, the entity of the data is the first-in first-out memory 2
When output from 1, the Preamble_EN signal goes low and the K28.5 code is disabled. FIG. 3E shows the output of the serializer 32. Since the preamble adding circuit 2 operates as described above, the preamble 28 made of the K28.5 code is added to the head of the data encoded into the 8B / 10B code.

In the above description, an 8-bit parallel signal is transmitted from the medium control device. However, the parallel bit width may be another value, for example, 4 bits or 16 bits. Further, the encoding format is not limited to 8B / 10B. For example, it may be 4B / 5B. Also, the code serving as the preamble may not be the K28.5 code.

[Second Embodiment] FIG. 4 is a block diagram showing a preamble adding circuit according to a second embodiment of the present invention. FIG.
In FIG. 7, only the preamble adding circuit 2 is taken out and drawn. This embodiment is characterized in that a set / reset flip-flop 26 and a down counter 27 are added to the preamble adding circuit 2 in FIG. 2, and a three-input OR gate is used instead of the OR gate 23.

In this embodiment, the TX_EN signal triggers the down counter 27 to generate a pulse of a predetermined length. Then, an instruction is given to the optical transceiver 4 to continue the transmission of the optical signal during the period of this pulse, and when there is no data to be transmitted during this transmission period (TX
When the _EN signal is low), the idle signal 29 becomes K
It is configured to insert a 28.5 code between data. Further, a preamble 28 is added to the head of the packet as in the first embodiment.

In this embodiment, a CSMA / CD (Carrier Se) used in a bus type network system is used.
nse Multiplex Access with
It is suitable for a system that employs a Collision Detection) protocol. In the CSMA / CD protocol, the minimum duration of a packet is defined by the size of a bus, so that a transmission signal must continue for a predetermined time or longer. In this embodiment, the minimum time can be realized by hardware using the down counter 27.

FIG. 5 is a timing chart showing the operation of the preamble adding circuit shown in FIG. The first-in first-out memories 21 and 22 have the same depth, and 8-bit parallel data is sent to the first-in-first-out memory 21 and the TX_EN signal is sent to the first-in-first-out memory 22. These first-in first-out memories 21 and 22 operate as delay circuits.

FIG. 5A shows the TX_EN signal and FIG.
(B) shows the first-in first-out memory 22 output. It can be seen that the signal is delayed. FIG. 5C shows a signal of the output Slot Time of the down counter 27. TX
The high level continues for a second predetermined time triggered by _EN. FIG. 5D shows the Reset output of the down counter 27, which generates a short pulse after the high level continues for the second predetermined time. This Reset output is set reset
Reset the flip flop 26. FIG. 5F shows a signal that enables the optical transceiver 4 to transmit using the OPT_EN signal. The OPT_EN signal includes a TX_EN signal, an output from the first-in first-out memory 22, and an output Slo
The three-input OR with t Time is obtained by the OR gate 25. The gate 46 in the optical transceiver 4 is opened and closed by the OPT_EN signal.

FIG. 5 (e) shows the Preamble_EN signal obtained by taking the AND logic of the OPT_EN signal and the output of the first-in first-out memory 22 by the one-sided negative input AND gate 24. The Preamble_EN signal is applied to the encoder 31, and when the Preamble_EN signal is high, a special code, for example, a K28.5 code is generated. The data signal sent from the medium control device (MAC) 1 is delayed by the first-in first-out memory 21. During the delay, the Preamble_EN signal is high, so that the output of the encoder 31 is a K28.5 code. When the data entity is output from the first-in first-out memory 21, the Preamble_EN signal becomes low, and the K28.5 code is invalidated (disabled).

FIG. 5G shows the output of the serializer 32. Since the preamble adding circuit 2 operates as described above, the preamble 28 made of the K28.5 code is added to the head of the data encoded into the 8B / 10B code. Also, valid data outputs DATA1 and DATA1
During 2, the idle signal 29 is inserted after DATA2.

[0023]

According to the present invention, a preamble can be generated in hardware, and the number of steps for software development can be reduced. Further, it is possible to provide an optical transceiver applicable to an optical fiber communication network using a passive optical branch circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an optical transceiver according to the present invention.

FIG. 2 is a block diagram depicting FIG. 1 in further detail.

FIG. 3 is a timing chart showing the behavior of the optical transceiver according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a pre-angle adding circuit according to a second embodiment of the optical transceiver of the present invention.

FIG. 5 is a timing chart showing the behavior of the optical transceiver according to the second embodiment of the present invention.

FIG. 6 is a diagram showing a conventional optical fiber communication network system using a passive optical branching line, a packet and a header thereof.

[Description of Signs] 1 ... Media control device (MAC) 2 ... Preamble addition circuit 3 ... Serial-parallel conversion circuit (SERDES) 4 ... Optical transceiver 5 ... Optical coupler 6 ... Optical fiber 10 ... Optical transmission / reception modules 21, 22 ... First in first out Memory (FIFO) 23 ... OR gate 24 ... Negative input AND gate 25 ... 3 input OR gate 26 ... Set reset / Flip flop 27 ... Down counter 28 ... Preamble 29 ... Idle signal 31 ... Encoder 32 ... Serializer (parallel-serial converter) 33) Deserializer (serial-parallel converter) 34 ... Decoder 41 ... Laser diode with built-in photodiode for monitoring 42 ... Photodiode with built-in preamplifier 43 ... Laser drive circuit 44 ... Post-amplifier for waveform shaping 45 ... Automatic output control circuit ( AP ) 46 ... header portion of the gate 120, 121, 122, 123 ... station 124 ... passive optical branching path 130 ... packet 131 ... packet 131

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Claims (4)

[Claims] A first delay circuit for delaying a transmission request signal and data to be transmitted together for a first predetermined time; and a mechanism for generating a preamble for the first predetermined delay time. A preamble adding circuit characterized by the following. 2. An optical transceiver comprising the preamble adding circuit according to claim 1. 3. The preamble adding circuit according to claim 1, further comprising a mechanism for continuing the transmission state for a second predetermined time triggered by the transmission request signal, wherein the transmission request signal falls to a low level within the second predetermined time. A preamble adding circuit comprising a mechanism for controlling an idle signal to be transmitted when the preamble is dropped. 4. An optical transceiver comprising the preamble adding circuit according to claim 3.