US7480751B2 - Serial data interface system and method using a selectively accessed tone pattern generator - Google Patents
Serial data interface system and method using a selectively accessed tone pattern generator Download PDFInfo
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- US7480751B2 US7480751B2 US10/656,234 US65623403A US7480751B2 US 7480751 B2 US7480751 B2 US 7480751B2 US 65623403 A US65623403 A US 65623403A US 7480751 B2 US7480751 B2 US 7480751B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1438—Negotiation of transmission parameters prior to communication
Definitions
- the present invention is related to toning for connectivity and speed handshaking in Beta and/or Bilingual ports of IEEE1394 devices.
- a Bilingual port is a single port that includes a system allowing for transceiving of both Legacy and Beta signals.
- Bilingual ports reference can be made to U.S. patent application Ser. No. 10/660,670, filed Sep. 12, 2003, entitled “Serial Data Interface System And Method Having Bilingual Functionality,” to van Engelen et al., which is incorporated by reference herein in its entirety.
- Beta signaling is usually done using serializer/deserializer (SerDes) technology for its dual simplex signaling scheme.
- SerDes serializer/deserializer
- TPs twisted-pairs
- a first TP is used only to transmit from a serializer and a second TP is used only to receive at a deserializer.
- All idle, arbitration, and packet speed information is transmitted as symbols in the data, which can allow for continuous clock recovery.
- a special toning scheme is used to check for connection and signal speed.
- An on/off keyed tone is send as a differential output signal with a certain output amplitude, frequency, and repetition.
- toning is used for speed and connectivity determination in Beta signal ports. Therefore, what is needed is a simple and inexpensive system and method for toning.
- Embodiments of the present invention provide a system and method for performing speed and connection handshaking between Beta signal systems in serial data interface devices.
- a tone pattern generator e.g., a flip-flop
- a selecting system e.g., a multiplexer
- These signals include a driver control signal.
- a serializing device serializes either the tone pattern signal or the data input signal.
- a clock device e.g., a clock divider
- a driver receives and differentially transmits either the serialized tone pattern signal or the serialized data input signal.
- FIG. 1 shows an IEEE1394 system.
- FIG. 2 shows an IEEE1394 node in the system of FIG. 1 .
- FIG. 3 shows an IEEE1394 PHY chip in the IEEE1394 node of FIGS. 1 and 2 .
- FIG. 4 shows a typical peer-to-peer connection scheme between Legacy and Beta ports, in the case of copper twisted pair (TP) cable media.
- TP copper twisted pair
- FIGS. 5 , 6 , 7 and 8 show various tone signal producing arrangements according to various embodiments of the present invention.
- Embodiments of the present invention provide a system and method for performing speed and connection handshaking between Beta signal systems in serial data interface devices. Handshaking is done using a signal approximately 49 MHz to approximately 62 MHz, as discussed above.
- a tone pattern generator e.g., a flip-flop
- a specified number of HIGH and LOW signals can be continuously generated at a predetermined rate in order to output the approximately 49 MHz to approximately 62 MHz tone pattern signal from the Beta signal system. For example, at S 800 data rate, 10 HIGHS and 10 LOWS can be generated in order to form an approximately 49.152 MHz tone signal.
- a selecting system selectively transmits either the tone pattern signal or a data input signal that is input from a PHY digital core. Either the tone pattern or the data input is serialized using a serializing system. Serialized tone or data signals are differentially transmitted along the media (e.g. the twisted pairs in cables of the short-haul copper media), via a driver, to peer serial data interface devices.
- media e.g. the twisted pairs in cables of the short-haul copper media
- FIG. 1 is a block diagram of a section 100 of an IEEE 1394 system including a plurality of nodes 102 (e.g., 102 A- 102 D) according to embodiments of the present invention.
- nodes 102 e.g., 102 A- 102 D
- Up to 1000 systems 100 can be interconnected, and each system 100 can include, for example, up to 63 peers or nodes 102 .
- Nodes 102 include one or more ports 104 .
- Nodes 102 having multiple ports 104 behave as repeaters. Loops are generally not allowed, so all nodes 102 are connected in a tree structure via cables 106 .
- Each cable 106 includes at least two twisted-wire pairs (TPs).
- Node-to-node (e.g., peer-to-peer) connections can be at various speeds and using various modes (e.g., Legacy or Beta).
- Arbitration is used to determine which node 102 can talk on a particular bus to another node.
- An algorithm is used to process requests from nodes 102 to determine which node 102 will talk on the bus at a particular time period.
- Bus speeds or signaling speeds are based on multiples of a base speed S 100 that is formed from multiples of 24.576 MHz.
- Base Legacy speed S 100 is about 98.304 Mbps and base Beta speed S 100 is about 122.88 Mbps. Every port 102 has to support lower speeds than its rated speed. For example, a Legacy S 400 port must support Legacy S 200 and Legacy S 100 .
- Data transfer is packet based using either Isochronous (e.g., periodic, guaranteed bandwidth, usually video, audio, etc.) or Asynchronous (e.g., a-periodic, usually data transfer, etc.) packets.
- Isochronous e.g., periodic, guaranteed bandwidth, usually video, audio, etc.
- Asynchronous e.g., a-periodic, usually data transfer, etc.
- data can be sent over several media, which can include copper twisted pair cables, glass, fiber, or other interconnect materials.
- the material used can depend on the data speed and/or the standard or mode of the signals (e.g., Legacy or Beta).
- the mode also dictates a number of pins (e.g., Legacy 4 or 6 and Beta 9) required for connectors coupled to either end of the cables 106 , in the case of the copper twisted pair (TP) media.
- pins e.g., Legacy 4 or 6 and Beta 9
- Legacy signaling (e.g., data or strobe signals) is performed using half-duplex signaling.
- a Legacy system has a TP bias (TPBIAS) system (e.g., for setting and controlling signal speed, common mode voltage, checking connections, and other functions) and first and second TPs.
- TPBIAS TP bias
- sending or receiving of signals is performed using both the first and second TPs, but sending and receiving is not done at the same time.
- FIG. 4 shows a typical IEEE 1394 connection scheme for Legacy ports 104 A and Beta ports 104 B between nodes 102 A, 102 B, and 102 C, respectively.
- Signals from the first and second TPs (e.g., TPA 1 and TPB 1 ) cross.
- TPA 1 at a first node 102 A transmits a signal that is received by TPB 2 at a second node 102 B.
- TPB 2 a second node 102 B.
- Data traveling from a first node 102 A along TPA 1 is used by second node 102 B along TPB 2 .
- the data and strobe signals are differential binary signals. Mixed speed signals can be transmitted on the same wires. Arbitration is performed using DC-like line states (e.g., 1, 0, and Z where Z indicates a high-impedance state) with no continuous clock recovery, and using asynchronous analog technology.
- DC-like line states e.g., 1, 0, and Z where Z indicates a high-impedance state
- Beta signaling is usually performed with serializer/deserializer (SerDes) technology and using dual simplex signaling. For example, when two TPs are used, a first TPB 3 , 4 is used only to transmit from a serializer, and a second TPA 3 , 4 is used only to receive at a deserializer. Idle, arbitration, and packet speed information is transmitted as symbols in the data, which can allow for continuous clock recovery. Toning is used to check for connection and signal speed.
- SerDes serializer/deserializer
- FIG. 2 is a block diagram of a node 102 , including an IEEE1394 link chip 200 , which performs a similar function as a media access controller (MAC) in the IEEE802.3 (Ethernet) standard.
- the node 102 also includes an IEEE 1394 physical layer device (PHY) chip 202 .
- PHY physical layer device
- FIG. 3 is a block diagram of PHY chip 202 .
- a PHY analog core 300 includes ports 104 .
- a PHY digital core 302 processes all digital signals received and transmitted by port 104 .
- a PHY/link interface 304 links PHY chip 202 to link chip 200 .
- Supporting circuitry 306 is used to control, power, and other functionality, and couple these and other devices in PHY chip 202 .
- Legacy ports 104 A include drivers (D) 400 and receivers (R) 402 for directing Legacy signals.
- Legacy signals travel from TPA and TPB pins along TPA 1 , 2 and TPB 1 , 2 from ports 104 A and 104 B to connection systems 404 that include supporting circuitry 406 .
- Signals from 104 A and 104 B are cross-connected using connection system 404 (e.g., TPA 1 and TPB 2 connect, while TPA 2 and TPB 1 connect). Doing this allows signals transmitted from a first node 102 A along TPA 1 to be received along TPB 2 at node 102 B.
- Beta ports 104 B include standard-based receivers (R) 410 and drivers (D) 412 for directing Beta signals. Beta signals are always received along TPA 3 , 4 and always transmitted along TPB 3 , 4 using connection system 414 having supporting circuitry 416 . Devices 418 perform clock recovery and deserialization on received signals. Transmitted signals are serialized and transmitted using device 412 and 420 before being transmitted.
- R receivers
- D drivers
- PHY analog core 300 could include a Legacy port 104 A, a Beta port 104 B, and Bilingual port 104 C.
- FIG. 5 shows a portion 500 of a Beta signal system having a tone pattern generating device 502 (e.g., an oscillator) according to an embodiment of the present invention.
- Oscillator receives a Tone 13 on signal from PHY digital core 302 .
- Portion 500 uses a selecting device 510 (e.g. an analog multiplexer) to selectively transmit either a tone pattern signal 504 from oscillator 502 or a data signal 506 , which is input from a serializer (not shown) (e.g., serializer 420 ) along data path 508 .
- Driver 512 differentially transmits one of the signals 504 or 506 as signals tpbp and tpbn along TPB.
- data signal 506 When data signal 506 is transmitted, it is first serialized using a serializer, as discussed above. In the embodiment shown, when tone signal 504 is being transmitted, the serializer can go into standby mode to conserve power.
- Signals 504 and 506 include a driver control portion 514 (e.g., highZ) that places driver 512 in either one of two modes (e.g., high-impedance (inactive) or normal). For example, when highZ is active, driver 512 is in a high-impedance mode, which makes driver 512 inactive. In contrast, when highZ is inactive, driver 512 is a normal operating mode during which driver 512 transmits a HIGH or LOW signal based on signals 504 and 506 .
- driver control portion 514 e.g., highZ
- driver 512 is in a high-impedance mode, which makes driver 512 inactive.
- driver 512 is a normal operating mode during which driver 512 transmits a HIGH or LOW signal based on signals 504 and 506 .
- FIG. 6 shows a portion 600 of a Beta signal system having a tone pattern generating device 602 (e.g., an oscillator) according to an embodiment of the present invention.
- a tone signal 604 from oscillator 602 is received, along with a Tone_on signal from PHY digital core 302 , at a driver 620 .
- a second driver 612 receives data input signal 606 from a serializer (not shown) (e.g., serializer 420 ) and a driver control signal (e.g., highZ).
- a serializer not shown
- driver control signal e.g., highZ
- Tone_on and High_Z control drivers 620 and 612 respectively, either making them active or inactive.
- tone signal 604 is transmitted from portion 600 .
- the serializer can be placed in stand-by mode for power savings.
- driver 612 while driver 612 is active, data signal 606 is transmitted from portion 600 .
- Tone Pattern Generating System Using Tone Pattern Generating Device
- FIG. 7 shows a portion 700 of a Beta signal system according to embodiments of the present invention.
- a tone pattern generator 702 e.g., a flip-flop
- a selecting system 704 e.g., a digital multiplexer
- portion 700 receives an input data signal 706 from PHY digital core 302 at a selecting system 704 .
- Selecting system 704 also receives a tone pattern signal 708 from tone pattern generator 702 .
- selecting system 704 selectively passes data or tone pattern signal 706 or 708 to serializer 710 .
- Serializer 710 and tone pattern generator 702 are both driven by low speed clock signal 712 generated from high speed clock signal 714 in clock divider 716 .
- Serializer 710 is also driven by the high speed clock 714
- both data signal 706 and tone pattern signal 708 include a driver control portion 718 (e.g., highZ), discussed in more detail below.
- serialized data signal 706 ′ or serialized tone pattern signal 708 ′ and driver control signal 718 (e.g., highZ) is directed to driver 720 .
- driver 720 differentially transmits either serialized data 706 ′ or tone 708 ′ signal as tpbn and tpbp along TPB 3 or 4 to peer Beta signal systems (e.g., during a normal operating or active state).
- highZ 718 is high, driver 720 is placed in a high-impedance or inactive state.
- tone pattern generator 702 produces an approximately 49 MHz to approximately 62 MHz tone pattern signal 708 .
- This can be done using a continuous string of 10 HIGH signals and 10 LOW signals produced at a predetermined rate (e.g., S 800 data rate or 981.204 Mbaud/sec), which appears to peer Beta signal systems as an approximately 49.152 MHz signal.
- a predetermined rate e.g., S 800 data rate or 981.204 Mbaud/sec
- a size of a string of HIGH and LOW signals will vary. This is accomplished because a clock driving serializer 710 should be very accurate and have very little jitter, which means that tone pattern signal 708 will have a very accurate frequency.
- selecting system 704 can be a multiplexer 804 (e.g. a digital multiplexer) and tone generating device 702 can be a flip-flop 802 .
- a digital multiplexer can be used, which is easier to implement than an analog multiplexer and can run at lower speeds.
Abstract
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US10/656,234 US7480751B2 (en) | 2003-09-08 | 2003-09-08 | Serial data interface system and method using a selectively accessed tone pattern generator |
US12/348,572 US8024501B2 (en) | 2003-09-08 | 2009-01-05 | Serial data interface system and method using a selectively accessed tone pattern generator |
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US8024501B2 (en) | 2003-09-08 | 2011-09-20 | Broadcom Corporation | Serial data interface system and method using a selectively accessed tone pattern generator |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7657799B2 (en) * | 2006-05-04 | 2010-02-02 | Agere Systems, Inc. | Method and apparatus for testing a dual mode interface |
US9112602B2 (en) * | 2010-06-25 | 2015-08-18 | Intel Corporation | Method of automatically determining link speed for a multispeed fiber link module |
KR102453113B1 (en) * | 2015-12-16 | 2022-10-12 | 삼성전자주식회사 | Signal transmitting circuit reducing power at standby state |
US10135538B2 (en) * | 2016-08-02 | 2018-11-20 | Finisar Corporation | Signaling on a high-speed data connector |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5264958A (en) | 1991-11-12 | 1993-11-23 | International Business Machines Corp. | Universal communications interface adaptable for a plurality of interface standards |
US5559967A (en) * | 1993-03-18 | 1996-09-24 | Apple Computer, Inc. | Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers |
US5715409A (en) * | 1993-05-24 | 1998-02-03 | I-Tech Corporation | Universal SCSI electrical interface system |
US5909464A (en) | 1994-02-18 | 1999-06-01 | Telebit Corporation | Serial communications interface that supports multiple interface standards |
US6037828A (en) | 1997-10-09 | 2000-03-14 | Exar Corporation | Transmission line driver with high output impedance at power off |
US20010007436A1 (en) * | 2000-01-07 | 2001-07-12 | Matsushita Electric Industrial Co., Ltd. | Frequency detector and phase-locked loop circuit including the detector |
US6295519B1 (en) | 1995-03-03 | 2001-09-25 | Datascape, Inc. | Method and apparatus for coupling multiple computer peripherals to a computer system through a single I/O port |
US6334160B1 (en) * | 1999-01-28 | 2001-12-25 | Hewlett-Packard Co. | Apparatus and method for providing multiple protocols through a common connector in a device |
US20030065859A1 (en) | 2001-04-27 | 2003-04-03 | Dao Tuan A. | Fibre channel transceiver |
US20030067884A1 (en) | 1997-11-21 | 2003-04-10 | Abler Joseph Michael | Dynamic detection of LAN network protocol |
US6727728B1 (en) | 1997-12-30 | 2004-04-27 | Lsi Logic Corporation | XOR circuit |
US20040103219A1 (en) | 2002-08-26 | 2004-05-27 | Jun Okazaki | Network device and method |
US20040218052A1 (en) | 2001-08-17 | 2004-11-04 | Didomenico John | Method and system for video capture of vehicle information |
US20050021890A1 (en) | 2003-07-22 | 2005-01-27 | Keith Baker | Multi-functional port |
US20050036506A9 (en) | 1998-11-12 | 2005-02-17 | Dove Daniel Joseph | Apparatus & method for automatically switching media connections when operating in forced speed and duplex mode |
US20050060471A1 (en) | 2003-09-12 | 2005-03-17 | Broadcom Corporation | Serial data interface system and method having bilingual functionality |
US6965950B1 (en) | 1999-06-29 | 2005-11-15 | Sony Corporation | Signal input and output apparatus that discriminates between plurality of different devices each issuing unique control signals substantially simultaneously through single transmission path |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4862514A (en) * | 1986-11-24 | 1989-08-29 | World Electronics, Inc. | Hybrid electronic radio repeater |
JP4025429B2 (en) * | 1998-08-21 | 2007-12-19 | 富士通株式会社 | Connection control device and connection control method |
US6519544B1 (en) * | 1999-09-29 | 2003-02-11 | Fujitsu Limited | Method and apparatus for IEEE 1394 bus analysis |
US6618785B1 (en) * | 2000-04-21 | 2003-09-09 | Apple Computer, Inc. | Method and apparatus for automatic detection and healing of signal pair crossover on a high performance serial bus |
JP3450274B2 (en) * | 2000-04-26 | 2003-09-22 | エヌイーシーマイクロシステム株式会社 | Communication control circuit |
JP3544932B2 (en) * | 2000-10-05 | 2004-07-21 | Necエレクトロニクス株式会社 | Electronic device and power control method thereof |
US6898721B2 (en) * | 2001-06-22 | 2005-05-24 | Gallitzin Allegheny Llc | Clock generation systems and methods |
US20040133912A1 (en) * | 2002-10-22 | 2004-07-08 | Chris Thomas | Method and apparatus of IEEE 1394 tone transmission in beta mode |
US20040114585A1 (en) * | 2002-12-17 | 2004-06-17 | Kraemer Finn Leif | Clock provisioning techniques |
US7480751B2 (en) | 2003-09-08 | 2009-01-20 | Broadcom Corporation | Serial data interface system and method using a selectively accessed tone pattern generator |
-
2003
- 2003-09-08 US US10/656,234 patent/US7480751B2/en active Active
-
2009
- 2009-01-05 US US12/348,572 patent/US8024501B2/en not_active Expired - Fee Related
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5264958A (en) | 1991-11-12 | 1993-11-23 | International Business Machines Corp. | Universal communications interface adaptable for a plurality of interface standards |
US5559967A (en) * | 1993-03-18 | 1996-09-24 | Apple Computer, Inc. | Method and apparatus for a dynamic, multi-speed bus architecture in which an exchange of speed messages occurs independent of the data signal transfers |
US5715409A (en) * | 1993-05-24 | 1998-02-03 | I-Tech Corporation | Universal SCSI electrical interface system |
US5909464A (en) | 1994-02-18 | 1999-06-01 | Telebit Corporation | Serial communications interface that supports multiple interface standards |
US6295519B1 (en) | 1995-03-03 | 2001-09-25 | Datascape, Inc. | Method and apparatus for coupling multiple computer peripherals to a computer system through a single I/O port |
US6037828A (en) | 1997-10-09 | 2000-03-14 | Exar Corporation | Transmission line driver with high output impedance at power off |
US20030067884A1 (en) | 1997-11-21 | 2003-04-10 | Abler Joseph Michael | Dynamic detection of LAN network protocol |
US6727728B1 (en) | 1997-12-30 | 2004-04-27 | Lsi Logic Corporation | XOR circuit |
US20050036506A9 (en) | 1998-11-12 | 2005-02-17 | Dove Daniel Joseph | Apparatus & method for automatically switching media connections when operating in forced speed and duplex mode |
US6334160B1 (en) * | 1999-01-28 | 2001-12-25 | Hewlett-Packard Co. | Apparatus and method for providing multiple protocols through a common connector in a device |
US6965950B1 (en) | 1999-06-29 | 2005-11-15 | Sony Corporation | Signal input and output apparatus that discriminates between plurality of different devices each issuing unique control signals substantially simultaneously through single transmission path |
US20010007436A1 (en) * | 2000-01-07 | 2001-07-12 | Matsushita Electric Industrial Co., Ltd. | Frequency detector and phase-locked loop circuit including the detector |
US20030065859A1 (en) | 2001-04-27 | 2003-04-03 | Dao Tuan A. | Fibre channel transceiver |
US20040218052A1 (en) | 2001-08-17 | 2004-11-04 | Didomenico John | Method and system for video capture of vehicle information |
US20040103219A1 (en) | 2002-08-26 | 2004-05-27 | Jun Okazaki | Network device and method |
US20050021890A1 (en) | 2003-07-22 | 2005-01-27 | Keith Baker | Multi-functional port |
US20050060471A1 (en) | 2003-09-12 | 2005-03-17 | Broadcom Corporation | Serial data interface system and method having bilingual functionality |
Non-Patent Citations (11)
Title |
---|
1394 Integrated Devices Product Home from Texas Instruments, Texas Instruments Inc., from http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=analog&family-Id=547&uiTemplateId=NODE-STRY-PGE-T¶mCriteria=no, 2 pages, printed Mar. 17, 2006 (Copyright 1995-2005). |
1394, Agere Systems Inc., from http://www.agere/cpm/entnet/1394.html, 2 pages, printed Mar. 17, 2006 (Copyright 2002-2006). |
1394, Philips, from http://www.semiconductors.philips.com/products/connectivity-/1394/index.html, 2 pages, printed Mar. 17, 2006 (Copyright 2004-2005). |
1394b(TM) IEEE Standard for a High Performance Serial Bus-Amendment 2, IEEE Std 1394b(TM)-2002, entire document submitted (Copyright 2002). |
FW803 PHY IEEE* 1394A Three-Cable Transceiver/Arbiter Device, Data Sheet, Rev. 3, Agere Systems Inc., 24 pages (Jun. 2001). |
IEEE Standard for a High Performance Serial Bus, IEEE Std 1394-1995, entire document submitted (Copyright 1996). |
IEEE Standard for a High Performance Serial Bus-Amendment 1, IEEE Std 1394a-2000, entire document submitted (Copyright 2000). |
PDI1394P21 3-port 400 Mbps physical layer interfaec, Data Sheet, Philips, 40 pages (Sep. 6, 2001). |
PDI1394P23 2 port/1-port 400 Mbps physical layer interface, Data Sheet, Philips, 42 pages (Sep. 6, 2001). |
TSB41AB3 IEEE 1394a-2000 Three-Port Cable Transceiver/Arbiter, Texas Instruments Inc., 50 pages (Copyright 2001). |
TSB81BA3 IEEE 1394b Three-Port Cable Transceiver/Arbiter, Texas Instruments Inc., 57 pages (Copyright 2002). |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8024501B2 (en) | 2003-09-08 | 2011-09-20 | Broadcom Corporation | Serial data interface system and method using a selectively accessed tone pattern generator |
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US20090119426A1 (en) | 2009-05-07 |
US8024501B2 (en) | 2011-09-20 |
US20050053019A1 (en) | 2005-03-10 |
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