JP2001156567A - High frequency amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency amplifier circuit whose gain variable range by an AGC voltage can be increased. SOLUTION: The high frequency amplifier circuit is provided with a dual gate FET 1 having a 1st gate receiving a high frequency signal, a 2nd gate where an AGC voltage is applied and with a 1st capacitor means 9 placed between the 2nd gate and a high frequency ground point. The capacitance of the 1st capacitor means 9 is gradually changed to be smaller corresponding to the attenuation of a gain of the dual gate FET 1 due to a change in the AGC voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency amplifier circuit, and more particularly to a high frequency amplifier circuit suitable for use in a variable gain amplifier circuit of a television tuner or the like.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional high frequency amplifier circuit has a dual gate FET (hereinafter simply referred to as "FET").
1. The source S of the FET 31 is grounded at a high frequency and the drain D is connected to the choke inductor 3.
2. The power supply voltage Vb is supplied through the protection resistor 33 in series, and the power supply voltage Vb is supplied to the first gate G1 by the bias resistor 3.
The bias voltage obtained by the voltage division by 4 and 35 is applied. The AGC voltage Va for changing the gain is applied to the second gate G
2 is applied. Then, a high-frequency signal is input to the first gate G1, and the amplified signal is supplied to the choke inductor 32.
It is output from the connection point between the power supply and the protection resistor 33.

AGC voltage V applied to second gate G2
a is changed according to the level of the input high-frequency signal,
It changes so as to gradually decrease as the level increases. However, the maximum value is set lower than the power supply voltage Vb. For example, if the power supply voltage Vb is 5 volts, A
The maximum value of the GC voltage Va is 4 volts, and changes to the minimum value of 0 volt. The second gate G2 is grounded at a high frequency by a DC cut capacitor 36.

In the above arrangement, the drain current also changes due to the change in the AGC voltage Va, and as a result, the voltage of the first gate G1 relative to the voltage of the source S changes, and the transconductance with respect to the first gate changes. The gain changes. When the level of the input high-frequency signal is extremely low, the AGC voltage Va of 4 volts is applied, so that the drain current is maximized, and the transconductance is increased, so that the gain of the FET 31 is maximized. On the other hand, as the level of the high-frequency signal increases, the AGC voltage Va decreases, the drain current decreases, the transconductance decreases, and the gain decreases. For example, when the AGC voltage Va is 0 volt, the gain becomes negative and the FET 31 functions as an attenuator. As a result, FE
The signal level output from T31 is controlled to be substantially constant irrespective of the level of the input high-frequency signal.

By the way, the dual gate FET 31
As shown in FIG. 7, two single-gate FETs 41,
It is considered to be equivalent to a circuit in which 42 is cascaded. Accordingly, the gate g1 and the source s1 of the first single-gate FET 41 correspond to the first gate G1 and the source S in FIG.
2 correspond to the second gate G2 and the drain D in FIG. 6, respectively. Then, a high-frequency signal is input to the gate g1 of the first single-gate FET 41 whose source is grounded, and an amplified signal is output from the drain d2 of the second single-gate FET 42 whose gate g2 is grounded. Then, the gate g1 with respect to the source s1 of the first single-gate FET 41
Is controlled so as to change almost the entire gain.

[0006]

As described above, the gain of the conventional high-frequency amplifier circuit is controlled by the first single-gate FET 41 as shown in FIG. 6 has a narrow range of variable gain.
Even if the AGC voltage applied to the second gate G2 was reduced to 0 volt, the gain could not be sufficiently attenuated.

[0007] Therefore, the high-frequency amplifier circuit of the present invention comprises an AG
The purpose is to increase the variable range of the gain by the C voltage.

[0008]

In order to solve the above-mentioned problems, a high-frequency amplifier circuit according to the present invention includes a first gate to which a high-frequency signal is input, a second gate to which an AGC voltage is applied, and a source. A high frequency grounded dual gate FET, and a first capacitance means provided between the second gate and the high frequency grounding point to cope with attenuation of the gain of the dual gate FET due to a change in the AGC voltage. Thus, the capacitance value of the first capacitance means is gradually reduced.

Further, in the high frequency amplifier circuit according to the present invention, the first capacitance means is constituted by a varactor diode, and an anode of the varactor diode is connected to the second gate.
A voltage higher than the maximum value of the AGC voltage was applied to the cathode of the varactor diode.

In the high frequency amplifier circuit according to the present invention, a second capacitance means having a fixed capacitance is connected between the second gate and the high frequency ground point.

The high-frequency amplifier circuit according to the present invention has a first single-gate FET having a gate to which a high-frequency signal is input and a source grounded in a high-frequency manner, and cascade-connected to the first single-gate FET; A at the gate
A second single-gate FET to which a GC voltage is applied, wherein a first capacitance means is provided between the gate of the second single-gate FET and a high-frequency ground point;
The capacitance value of the first capacitance means is gradually reduced in accordance with the attenuation of the gain of the first single gate FET due to the change of the C voltage.

Further, in the high frequency amplifier circuit according to the present invention, the first capacitance means is constituted by a varactor diode, an anode of the varactor diode is connected to a gate of the second single gate FET, and a cathode of the varactor diode is connected. , A voltage higher than the maximum value of the AGC voltage was applied.

In the high frequency amplifier circuit according to the present invention, a second capacitance means having a fixed capacitance is connected between the gate of the second single gate FET and the high frequency ground point.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a high-frequency amplifier circuit according to the present invention will be described below with reference to FIGS.
FIG. 1 shows a first embodiment of a high-frequency amplifier circuit according to the present invention, in which a source S of a dual-gate FET (hereinafter simply referred to as FET) 1 is grounded by a bias resistor 2 and
The cut capacitor 3 is grounded at a high frequency, and a drain D is supplied with a power supply voltage Vb via a choke inductor 4 and a protection resistor 5 in series. A bias voltage obtained by dividing the power supply voltage Vb by the bias resistors 6 and 7 is applied to the first gate G1 via the choke inductor 8. Further, the anode of the varactor diode 9 serving as the first capacitance means is connected to the second gate G2, and the power supply voltage Vb serving as a high-frequency ground point is applied to the cathode of the varactor diode 9. Then, a high-frequency signal is input to the first gate G1, and an amplified signal is output from a connection point between the choke inductor 4 and the protection resistor 5.

The AGC voltage Va for changing the gain is applied to the second gate G2 via the power supply resistor 10. AGC
The voltage Va is changed according to the level of the input high-frequency signal, and changes so as to gradually decrease as the level increases. However, the maximum value is set lower than the power supply voltage Vb. For example, if the power supply voltage Vb is 5 volts, the maximum value of the AGC voltage Va is 4 volts, and gradually changes to the minimum value of 0 volts as the level of the input high-frequency signal increases.

Therefore, the AGC voltage Va is the maximum value of 4
In the case of volts, the voltage applied to both ends of the varactor diode 9 is as low as 1 volt, the equivalent capacitance value is extremely large, and the second gate G2 is grounded at a high frequency. Further, as the AGC voltage Va decreases toward 0 volt, the voltage across the varactor diode 9 becomes 5
As the voltage increases to volts, the equivalent capacitance value gradually decreases, and an impedance Zc based on this capacitance value is interposed between the second gate G2 and the high-frequency ground point. Therefore, this impedance Zc is
It increases as the voltage Va decreases.

In the above configuration, the drain current also changes due to the change in the AGC voltage Va, and as a result, the voltage of the first gate G1 relative to the voltage of the source S changes, and the transconductance with respect to the first gate changes. The gain changes. When the level of the input high-frequency signal is extremely low, the AGC voltage Va of 4 volts is applied, so that the drain current is maximized and the transconductance is increased, so that the gain of the FET 21 is maximized.

The equivalent circuit at this time is as shown in FIG.
It is represented by a cascade amplifier circuit of a first single-gate FET 21 whose source is grounded and a second single-gate FET 22 whose gate is grounded. The gate g2 of the second single-gate FET 22 is grounded at a high frequency. The operation is the same as the conventional operation shown in FIG.

On the other hand, as the level of the high-frequency signal increases, the AGC voltage Va decreases, the drain current decreases, the transconductance decreases, and the gain decreases. For example, when the AGC voltage Va is 0 volt, the gain becomes negative and the FET 21 functions as an attenuator. At this time, the capacitance value of the varactor diode 9 becomes minimum, and its impedance Zc becomes maximum.

Therefore, the equivalent circuit at this time is, as shown in FIG. 3, a first single gate FE whose source is grounded.
T21 and grounded second single-gate FET2
2, the gate g2 of the second single-gate FET 22 is grounded by a finite impedance Zc due to the capacitance of the varactor diode 9. As a result, the second single gate F
In the ET 22, negative feedback is applied by the impedance Zc, and the gain is reduced. Therefore, a large gain reduction as a whole is obtained together with the gain reduction of the first single gate FET 21.

FIG. 4 shows a circuit in which a capacitor 11 which is a second capacitance means having a fixed capacitance is connected between the second gate G2 and the ground (high-frequency ground point) in the circuit shown in FIG. Also in this case, the sum of the capacitance value of the varactor diode 9 and the capacitance value of the capacitor 11 when the AGC voltage Va is the maximum (4 volts) is set to a value sufficient to ground the second gate G2 at high frequency. When Va is minimum (0 volt), the sum of the capacitance values has a finite value of impedance Zc so that negative feedback is applied. By using the capacitor 11, a balance between the maximum gain and the amount of negative feedback in the second single-gate FET 22 can be obtained.

FIG. 5 shows a second embodiment in which the high-frequency amplifier circuit of the present invention is constituted by using the two single-gate FETs 21 and 22 shown in the equivalent circuits of FIGS. . The first single-gate FET 21 and the second single-gate FET 22 are cascaded, and the source s1 of the first single-gate FET 21 is grounded by the bias resistor 2 and the DC cut capacitor 3
And the second single gate F
The power supply voltage Vb is supplied to the drain d2 of the ET 22 via the choke inductor 4 and the protection resistor 5 in series.

A bias voltage obtained by dividing the power supply voltage Vb by the bias resistors 6 and 7 is applied to the gate g1 of the first single-gate FET 21 via the choke inductor 8. In addition, the second single gate FET 22
The gate of the varactor diode 9 is connected to the gate of the varactor diode 9, and the cathode of the varactor diode 9 is applied with a power supply voltage Vb serving as a high-frequency ground point. The AGC voltage Va for changing the gain is applied to the gate g2 of the second single-gate FET 22 via the power supply resistor 10. And the first single gate FE
A high-frequency signal is input to the gate g1 of T21, and an amplified signal is output from a connection point between the choke inductor 4 and the protection resistor 5.

The AGC voltage Va is changed according to the level of the input high-frequency signal, and changes so as to gradually decrease as the level increases. However, the maximum value is set lower than the power supply voltage Vb. For example, the power supply voltage Vb
Is 5 volts, the maximum value of the AGC voltage Va is 4 volts, and the minimum value of 0 increases as the level of the input signal increases.
It gradually changes up to the bolt.

The capacitance value of the varactor diode 9 becomes maximum when the AGC voltage Va is 4 volts. The gate value of the second single-gate FET 22 depends on the capacitance value at this time.
2 is grounded at a high frequency. When the AGC voltage Va is 0 volt, the voltage becomes minimum, and the gate g2 is grounded by the finite impedance Zc.

The operation of the above configuration is the same as that of the first embodiment shown in FIG. That is, the AGC voltage Va is 4
In the case of volts, the first single gate F with the source grounded
The gain of the ET21 increases, and the second single gate F
The ET 22 operates as a common-gate amplifier circuit. Also,
As the AGC voltage Va gradually decreases, the gain of the first single-gate FET 21 decreases. On the other hand, the second single-gate FET 22 has a negative feedback operation in which the impedance between the gate g2 and the ground gradually increases,
The gain decreases. Therefore, the amount of decrease in gain is large. In FIG. 5, the second single-gate FET
Between the gate g2 of 22 and the ground, a capacitor 11 which is a second capacitance means having a fixed capacitance value as shown by a dotted line may be connected. Thus, the amount of negative feedback is appropriately determined.

[0027]

As described above, the high-frequency amplifier circuit of the present invention has a dual gate having a first gate to which a high-frequency signal is input and a second gate to which an AGC voltage is applied, and a source grounded in high frequency. A gate FET, and a first capacitance means provided between the second gate and the high-frequency ground point;
Since the capacitance value of the first capacitance means is gradually reduced in accordance with the attenuation of the gain of the dual gate FET due to the change in the GC voltage, negative feedback is applied by the first capacitance means, and the amount of gain attenuation is reduced. growing. In addition, distortion characteristics are improved by negative feedback.

In the high frequency amplifier circuit according to the present invention, the first capacitance means is constituted by a varactor diode, the anode of the varactor diode is connected to the second gate, and the cathode of the varactor diode is higher than the maximum value of the AGC voltage. Since the voltage is applied, the capacitance value of the varactor diode can be automatically changed by the AGC voltage.

Further, in the high frequency amplifier circuit of the present invention, since the second capacitance means having a fixed capacitance is connected between the second gate and the high frequency ground point, the second capacitance means is connected to the first capacitance. Means is connected in parallel, and the amount of negative feedback can be easily set.

Further, the high-frequency amplifier circuit of the present invention cascade-connects a first single-gate FET grounded to a source and a second single-gate FET grounded to a gate,
A first capacitance means is provided between the gate of the second single-gate FET and the high-frequency ground point, and the first capacitance means corresponds to the attenuation of the gain of the first single-gate FET due to a change in the AGC voltage. Since the capacitance value is gradually decreased, negative feedback is applied to the second single-gate FET by the first capacitance means, and the overall gain attenuation is increased.

In the high frequency amplifier circuit according to the present invention, the first capacitance means is constituted by a varactor diode, the anode of the varactor diode is connected to the gate of the second single-gate FET, and the cathode of the varactor diode has an AGC voltage. Since the voltage higher than the maximum value is applied, the capacitance value of the varactor diode can be automatically changed by the AGC voltage.

In the high frequency amplifier circuit according to the present invention, the second capacitance means having a fixed capacitance is connected between the gate of the second single gate FET and the high frequency ground point. Are connected in parallel with the first capacitance means, and the setting of the amount of negative feedback is facilitated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a high-frequency amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the high-frequency amplifier circuit according to the present invention.

FIG. 3 is an equivalent circuit diagram of the high-frequency amplifier circuit according to the present invention.

FIG. 4 is a modification example of the first embodiment of the high-frequency amplifier circuit of the present invention.

FIG. 5 is a circuit diagram showing a high-frequency amplifier circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional high-frequency amplifier circuit.

FIG. 7 is an equivalent circuit diagram of a conventional high-frequency amplifier circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dual gate FET 2, 6, 7 Bias resistance 3 DC cut capacitor 4, 8 Choke inductor 5 Protection resistance 9 Varactor diode (first capacitance means) 10 Power supply resistance 11 Capacitor (second capacitance means) 21 First single Gate FET 22 Second single-gate FET

Claims (6)

[Claims] A first gate to which a high-frequency signal is input;
A dual gate FET having a second gate to which a GC voltage is applied and a source grounded at a high frequency, and a first capacitance means provided between the second gate and a high frequency ground point; A high-frequency amplifier circuit wherein the capacitance value of the first capacitance means is gradually reduced in accordance with the attenuation of the gain of the dual gate FET due to a change in AGC voltage. 2. The varactor diode comprises a varactor diode, the anode of the varactor diode is connected to the second gate, and a voltage higher than the maximum value of the AGC voltage is applied to a cathode of the varactor diode. 2. The high-frequency amplifier circuit according to claim 1, wherein: 3. The high frequency amplifier circuit according to claim 1, wherein a second capacitance means having a fixed capacitance value is connected between said second gate and said high frequency ground point. 4. A first single gate F whose gate receives a high-frequency signal and whose source is grounded in terms of high frequency.
ET and a second single-gate FET cascade-connected to the first single-gate FET and having an AGC voltage applied to the gate, between the gate of the second single-gate FET and the high-frequency ground point. Wherein a capacitance value of the first capacitance means is gradually reduced in accordance with the attenuation of the gain of the first single gate FET due to a change in the AGC voltage. High-frequency amplifier circuit. 5. The varactor diode comprises a varactor diode having an anode connected to the gate of the second single-gate FET, and a varactor diode having a cathode connected to a maximum value of the AGC voltage. The high-frequency amplifier circuit according to claim 4, wherein a high voltage is applied. 6. A second capacitance means having a fixed capacitance value is connected between the gate of said second single gate FET and said high frequency ground point.
A high-frequency amplifier circuit as described in the above.