JP2001156287A - Method of manufacturing silicide structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicide structure which is more improved in quality and where a leakage current is prevented from occurring. SOLUTION: A method of manufacturing a silicide structure is that the silicide structure is self-aligned and prevented from increasing in sheet resistance due to a reduction in a wire width by taking advantage of the specific characteristic of cobalt in which cobalt moves downward to react on silicon atoms. Furthermore, the characteristics of silicon atom in which silicon atoms move upward to react on titanium is also utilized. Titanium induces the upward movement of silicon atoms. A titanium layer is used as a barrier layer, by which cobalt acts less on silicon atoms, and a leakage current is prevented. A silicide multilayered structure is kept stable in resistance and capable of preventing a leakage current from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a self-aligned silicide (salicide).

[0002]

2. Description of the Related Art In submicron integrated circuit technology, line widths, contact areas and contact depths have been reduced. Effectively improve device quality, reduce resistance and reduce RC due to high resistance and capacitance
In order to reduce the delay time, there is a tendency to use silicide instead of normal polysilicon for forming the gate. Since silicide formation does not require a photolithography process, silicide formation is known as a self-aligned silicide process. Commonly known silicides include titanium silicide (TiSi ₂ ). Titanium silicide has become commonplace in the manufacture of semiconductor devices.

[0003] A typical self-aligned silicide formation process includes a step of preparing a semiconductor substrate having a shallow trench structure. A polysilicon gate is formed on the substrate, the gate including a spacer. Source / drain regions are also formed on both sides of the gate of the substrate. Then, titanium / silicon covering the surface of the gate and source / drain regions
Titanium nitride is deposited on a semiconductor substrate.
A two-step rapid thermal process (RTP) is performed to react titanium with the silicon on the source / drain regions and the gate surface.

[0004] Titanium silicide has two structures, a high resistance metastable C29 phase titanium silicide (C49-TiSi ₂ ) and a low resistance thermodynamically stable C54 phase titanium (C54-TiSi ₂ ). By the first step of this rapid heat treatment,
A titanium silicide layer (TiSi ₂ ) having a high content of the C49 phase and a low content of the C54 phase results. Thereafter, the unreacted titanium is removed. In the second step of the rapid processing, the temperature is further increased and rapid annealing is performed to transform the titanium silicide layer into a high-resistance C54 phase titanium silicide.

[0005] The resistance of C49 phase titanium silicide is higher and its formation temperature is lower. In contrast, the resistance of the C54 phase titanium silicide is low, and its formation temperature is high. Generally, a rapid heat treatment is performed to convert titanium silicide from a high-resistance C49 phase to a low-resistance C54 phase. In order to react the metal layer with silicon to form a silicide having a substantial thickness and a more uniform quality, it is necessary to increase the temperature and time of the heat treatment.

[0006]

During the heat treatment of the formation of titanium silicide, silicon is the primary mobile element.
The higher the temperature, the higher the mobility of the mobile element. The temperature must be at least 700 ° C. in order for the reaction to form titanium silicide to occur. On the other hand, if the temperature or time of the heat treatment is increased, some silicon diffuses from the source / drain regions of the substrate and the polysilicon layer and reacts with titanium metal.
Therefore, excess titanium silicide is formed on the surface of the spacer, a bridge is formed between the gate and the source / drain region and electrically connected, and the gate and the source / drain region are electrically connected.
Unexpected short circuit and current leakage occur with the drain region. Bridge formation and current leakage damage semiconductor devices and reduce device yield. In order to prevent the problem of bridge formation, it is necessary to lower the heat treatment temperature and shorten the time, and this will adversely affect the quality of the metal silicide, and will not effectively reduce the resistance. .

Further, with the miniaturization of the polysilicon gate, the formation temperature of the C54 phase titanium silicide rises due to the thin wire effect. This thin line effect is related to the relationship between line width and phase inversion temperature. As the line width decreases, the phase transition temperature of titanium silicide from high resistance C49 to low resistance C54 increases. As the temperature of the RTP process increases to form C54 titanium silicide, the quality of the titanium silicide becomes unstable, making it unsuitable for the fabrication of small size devices. In addition, the higher the reaction temperature, the more difficult it is to control and the risk of lateral growth of silicon from the source / drain regions to the spacer. As a result, as device integration increases and device dimensions shrink, bridge formation can occur on the sides of the gate. The reaction temperature cannot be raised to avoid the occurrence of bridge formation. Therefore,
The polysilicon gate has a higher resistance due to the fine line effect.

In order to solve the above-mentioned problem, there is another method of manufacturing a self-aligned silicide in which titanium silicide is replaced by cobalt silicide. In the heat treatment of the formation of cobalt silicide (CoSi ₂ ), the dominant mobile element is cobalt, which moves continuously downward until all the silicon elements have reacted to form CoSi ₂ . In order to avoid the occurrence of problems such as an increase in sheet resistance due to the miniaturization of the line width, the unique characteristics of cobalt are used. However, due to the total reaction of cobalt deposited on the surface of the shallow junction forming cobalt silicide, a current leak may occur at the shallow junction of the source / drain region. Invades through the joints of.

[0009]

Based on the above description, the present invention provides a multi-layered silicide layer formed by reacting a multilayer structure of Ti / Co / TiN with silicon and forming a multi-layered silicide layer on the source / drain region. Provided is a method for manufacturing a self-aligned silicide structure that prevents penetration into a junction and prevents current leakage.

According to the present invention, there is provided a self-alignment method in which a multilayer structure of Ti / Co / TiN reacts with silicon to form a multilayer silicide layer, thereby effectively eliminating the thin line effect of a transistor gate and obtaining a lower sheet resistance. To provide a method for manufacturing a silicide structure.

The present invention provides a method of manufacturing a self-aligned silicide structure in which a polysilicon gate having spacers is formed on a semiconductor substrate. Source / drain regions are formed on both sides of the gate of the semiconductor substrate. A pre-amorphization implant is performed on the polysilicon gate to further enhance the quality of the silicide structure formed in the subsequent self-aligned silicide structure fabrication process. Next, a two-stage rapid annealing process is performed on the surfaces of the polysilicon gate and the source / drain regions to form a silicide layer having a multilayer structure.

The present invention takes advantage of the unique property of cobalt moving downward and reacting with silicon atoms, thereby preventing the problem of increased sheet resistance due to finer linewidths. In addition, the present invention takes advantage of the unique properties of silicon atoms moving upward and reacting with titanium. Silicon atoms are guided to move upward. On the other hand, by using the titanium layer as the barrier layer, the reaction between the cobalt layer and the silicon atoms is suppressed, and the occurrence of current leakage at the junction is prevented. As a result, the multilayer structure of silicide according to the present invention not only forms a resistor for stability but also prevents the occurrence of current leakage.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide detailed explanations of the subject matter of the invention as set forth in the appended claims. It is.

[0014]

1A and 1B are schematic cross-sectional views illustrating the fabrication of a self-aligned silicide structure according to a preferred embodiment of the present invention. In this preferred embodiment, the present invention will be described with reference to an N-type metal oxide semiconductor (NMOS) polysilicon gate.

Referring to FIG. 1A, a semiconductor substrate 10, which is a P-type silicon substrate, is prepared. A gate 13 composed of a gate oxide layer 11 and a polysilicon layer 12 is
Form on top. Using the gate 13 as a mask, ion implantation is performed to form lightly-doped source / drain regions 14 on both sides of the gate 13 of the semiconductor substrate 10. Here, the implanted ions are N-type ions. After that, a spacer 16 is formed on the sidewall of the gate 13. Further, using the gate 13 and the spacer 16 as a mask, ion implantation is performed to form a source / drain region 17 having a high impurity concentration on both sides of the gate 13 of the semiconductor substrate 10. Here, the implanted ions are N-type ions. Lightly doped source / drain region 14
The source / drain region 17 to which the high concentration impurity is added together forms the source / drain region 19.

Next, an annealing process is performed to
The impurities in 0 are driven in and distributed in an appropriate region at a uniform concentration. Since the ion implantation process is known to those skilled in the art, it will not be described in detail in this preferred embodiment.

As the dimensions of the polysilicon gate are gradually reduced, the quality of the thin silicide layer formed on the polysilicon gate is degraded. This is because a large contact stress occurs between the silicide layer and the polysilicon gate, and the number of aggregation sites on the gate 13 and the substrate 10 is too small. Therefore, the sheet resistance is increased and the function of the gate is adversely affected. To this end, a pre-morphization implantation (PAI) is performed on the surface of the silicon layer to form an amorphous silicon layer, and then a self-aligned silicide process is performed on the gate 13 and the substrate 19 to obtain a lower sheet resistance.

Ion implantation is performed for the reason described above. Due to the ionic damage on the source / drain region surface, an amorphous thin layer (not shown) for increasing the aggregation sites is formed on the source / drain region surface, and is further improved in a self-aligned silicide process performed thereafter. A silicide layer having good quality can be formed. The implanted ions include arsenic ions (As ⁺ ).

Next, the substrate 1 is formed, for example, by sputtering.
A conformal titanium layer 20 and a cobalt layer 22 are sequentially formed on the top layer 0. The thickness of the titanium layer 20 is about 30
Å to about 500Å, and the thickness of the cobalt layer 22 is 30 to
It shall be 1000 °. Titanium nitride (TiN)
A layer 24 or titanium layer is further deposited on the cobalt layer 22 to a thickness of about 100 to 500 degrees. When a titanium layer is deposited, it can be reacted with ammonia to form a titanium nitride layer 24 on the cobalt layer 22.

Referring to FIG. 1B, the first step of the rapid thermal annealing process is performed at a temperature of about 400.degree. C. to 800.degree. C. for about 30 seconds to 2 minutes, and the surface of the polysilicon layer 12 and the source / drain regions 13 are coated with CoSi. to form a ₂ / TiSi ₂ / TiN sandwich multilayer structure.

Next, the unreacted titanium layer 20, eg, by wet etching using an RCA solution,
The cobalt layer 22 and the titanium nitride layer 24 are removed to form a CoSi ₂ / TiSi _{2 (silicide)} layer 26. In the second step of the rapid thermal anneal, the temperature is increased from about 700 ° C. to 1000 ° C. and maintained for about 15 seconds to about 2 minutes, completing the manufacture of an N-type metal oxide semiconductor (NMOS) transistor.

The present invention overcomes the problem of increased sheet resistance due to reduced linewidth, utilizing the unique properties of the reaction of cobalt with silicon atoms moving downward. In addition, the present invention also exploits the unique properties of the reaction of upward moving silicon atoms with titanium, where titanium also induces upward movement of silicon atoms. The titanium layer 20 also acts as a barrier layer, reducing the reaction between the cobalt layer 22 and the silicon atoms and the source / drain regions of the polysilicon gate 13, thereby suppressing the occurrence of junction current leakage. The formation of the CoSi ₂ / TiSi ₂ silicide layer 26 according to the present invention not only reduces the resistance but also prevents the occurrence of current leakage by the CoSi ₂ / TiSi ₂ silicide layer 26.

In this embodiment, the present invention has been described with reference to an N-type metal oxide semiconductor (NMOS) transistor. However, the present invention relates to a P-type metal oxide semiconductor transistor (PMOS),
The present invention can also be applied to a complementary metal oxide semiconductor transistor (CMOS) and a dual-gate element.

Obviously, various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the invention includes modifications and variations that fall within the scope of the following claims and equivalents thereof.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating the fabrication of a self-aligned silicide structure according to a preferred embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Gate oxide layer 12 Polysilicon layer 13 Gate 19 Source / drain region 20 Titanium layer 22 Cobalt layer 24 Titanium nitride layer

Continued on the front page F term (reference) 4M104 AA01 BB01 BB20 CC01 CC05 DD04 DD37 DD64 DD79 DD80 DD84 DD88 DD91 DD99 FF13 FF14 GG09 GG10 GG14 HH16 5F040 DA00 DA10 DC01 EC02 EC04 EC07 EC13 EF02 EF11 EH01 EH02 FA03 FB02 FC03 FB02

Claims (20)

[Claims] 1. A method for producing a self-aligned silicide structure applicable to a silicon structure, comprising: performing a pre-amorphization implantation process on a polysilicon gate and source / drain regions; and forming a titanium layer, a cobalt layer and A method of manufacturing a silicide structure, comprising: a step of sequentially forming a titanium nitride layer; and a step of performing a heat treatment to form a multilayer silicide layer in a polysilicon gate and source / drain regions. 2. The method according to claim 1, wherein the titanium layer has a thickness of about 30 to 500 degrees. 3. The method according to claim 1, wherein said cobalt layer has a thickness of about 30-1000 °. 4. The method according to claim 1, wherein said titanium nitride layer has a thickness of about 100-500 °. 5. The manufacturing method according to claim 1, wherein said heat treatment includes a rapid heat treatment. 6. The manufacturing method according to claim 5, wherein said rapid heat treatment includes two annealing processes. 7. The manufacturing method according to claim 6, wherein the annealing in the two steps includes a step of removing a titanium layer, a cobalt layer, and a titanium nitride layer that have not reacted. 8. The manufacturing method according to claim 6, wherein the first step of the annealing is performed at a temperature of about 400 ° C. to 800 ° C.
At a temperature of about 30 seconds to about 2 minutes. 9. The manufacturing method according to claim 6, wherein the second step of the annealing is performed at a temperature of about 700 ° C. to 1000 ° C.
A manufacturing method performed at a temperature of ° C. for a time of about 15 seconds to 2 minutes. 10. The method according to claim 1, wherein
A method of forming the titanium nitride layer by reacting the titanium layer with ammonia. 11. When manufacturing a metal oxide semiconductor transistor, a substrate having a device isolation structure is formed, a gate oxide layer is formed on the substrate, and a polysilicon layer is formed on the gate oxide layer. Forming a gate by defining the polysilicon source and a gate oxide layer, forming lightly doped source / drain regions on the substrate on both sides of the gate using the gate as a mask, and forming a spacer on a sidewall of the gate. Forming a source / drain region doped with a high concentration of impurities on the substrate using the gate and the spacer as a mask, wherein the lightly doped source / drain region and the region doped with a high concentration of impurities are formed Form source / drain regions together, perform pre-amorphization implant process, A method for manufacturing a metal oxide semiconductor transistor, wherein a titanium layer, a cobalt layer, and a titanium nitride layer are sequentially formed on the substrate, and heat treatment is performed to form a silicide layer having a multilayer structure. 12. The method for manufacturing a metal oxide semiconductor transistor according to claim 11, wherein the titanium layer has a thickness of about 30 to 500 °. 13. The method of manufacturing a metal oxide semiconductor transistor according to claim 11, wherein said cobalt layer has a thickness of about 30 ° to 1000 °. 14. The method according to claim 11, wherein the titanium nitride layer has a thickness of about 100 to 500 degrees. 15. The method according to claim 11, wherein the heat treatment includes a rapid heat treatment. 16. The method according to claim 15, wherein said rapid heat treatment includes two annealing processes. 17. The manufacturing method according to claim 16, wherein the first step of the annealing is performed at a temperature of about 400 ° C. to 8 ° C.
A manufacturing method performed at a temperature of 00 ° C. for a time of about 30 seconds to about 2 minutes. 18. The manufacturing method according to claim 11, wherein the second step of the annealing is performed at a temperature of about 700 ° C. to 1 ° C.
A manufacturing method performed at a temperature of 000 ° C. for a time of about 15 seconds to 2 minutes. 19. A method of forming a substrate having a gate and source / drain regions, a step of performing pre-amorphization implantation processing, a step of forming a first metal layer and a second metal layer on a substrate. A metal layer and a metal nitride layer are sequentially formed, and the metal of the second metal layer moves downward and reacts with silicon, and the first metal layer reacts with silicon moving upward and acts as a barrier layer. Reacting the metal of the second metal layer with silicon, thereby causing the metal nitride layer to act as a barrier layer; and performing heat treatment to form a multilayer silicide layer on the surface of the gate and source / drain regions. Forming a silicide. 20. The method for forming a silicide according to claim 19, wherein the first metal layer includes titanium.
A method for forming a silicide, wherein the second metal layer includes a cobalt layer, and the metal nitride layer includes a titanium nitride layer.