JP2001150740A - Imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor in which test print is carried out through a simple arrangement. SOLUTION: In the imaging apparatus, an image processing section for processing image data and a test print control section performing test print shares a memory. A storage means stores test print data in the memory during test print and stores conversion data for image processing during normal print. A switching means switches the memory to be connected with the test print control section during test print and switches the memory to be connected with the conversion processing section of some image data during normal print thus utilizing the memory in time sharing mode during normal print and test print.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a process for printing image data.

[0002]

2. Description of the Related Art In an image forming apparatus such as a printer,
A test printing circuit for performing test printing is provided in addition to the image processing circuit for the normal mode. A service person or the like finely adjusts image formation using a test printing circuit.

[0003]

In an image forming apparatus, test printing and normal image formation cannot be performed simultaneously.
Therefore, the test print circuit (including the RAM) and the image processing circuit for the normal print mode are not used at the same time. However, in the past, both functions were prepared with their own components, which was one factor in increasing the cost of the image forming apparatus.

An object of the present invention is to provide an image processing apparatus for performing test printing with a simple configuration.

[0005]

According to the present invention, there is provided an image forming apparatus having a test printing mode, comprising: an image processing unit for processing image data; a test printing control unit for performing test printing;
A memory shared by the image processing unit and the test print control unit, and a test print control unit for controlling the test print during the test print are connected to the memory, and the normal image print unit is connected to the memory during the normal print. And a storage means for storing test print data in the memory during test printing and storing conversion data for image processing in the memory during normal printing. The above memory is used in a time-division manner between normal printing and test printing. For example, in this image forming apparatus,
It comprises a part of the image processing unit, a test print control unit, and a rewritable device. In test print mode,
The test print control unit is written to the device,
In the normal mode, some circuits of the image processing unit are written in the device. For example, a part of the image processing unit is a density conversion unit that converts image data into density data, and the memory stores conversion data for image data conversion.

[0006]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference symbols indicate the same or equivalent ones. FIG. 1 shows the overall configuration of a color image processing apparatus. This color image processing apparatus has a test print mode in addition to the normal mode. In the normal mode, the red, green, and blue output signals of the color CCD sensor 10 including the three color line sensors are:
Each is converted into a digital signal by the AD converter 12. The obtained red (R), green (G), and blue (B) digital signals are corrected by the shading correction unit 14 and then input to the scaling unit 16. The data R4, which has been subjected to the scaling process and the movement process in the scaling unit 16,
G4 and B4 are the HVC converter 18 and the area discriminator 20.
Is output to The HVC conversion unit 18 includes R4, G4, B4
The data is converted to HVC data, the saturation signal W is sent to the under color removal / black printing unit 30, and the output data is
The data is sent to the density conversion unit 22 as G5 and B5 data. In addition,
The common RAM 26 is connected to the density converter 22 and the test print controller 24. A look-up table for density conversion is stored in the RAM 26. Density converter 22
Is an HVC converter 1 based on the conversion data in the RAM 26.
8 is -log data R5, G5, B5 sent
The data is converted into density data DR, DG, DB by conversion. The masking calculation unit 28 converts the density data DR, DG, and DB into print color data of cyan (C0), magenta (M0), and yellow (Y0). Further, the under-color removal / ink printing processing unit 30 performs under-color removal processing and black printing processing on the C0, M0, and Y0 data by using the saturation conversion data SW.
1, M1, Y1, and K1 data are output. On the other hand, the area determining unit 20 determines various areas based on the input data. M
The TF correction unit 32 corrects the C1, M1, Y1, and K1 data according to the determination result of the area determination unit 20 (eg, edge processing) and outputs data C3, M3, Y3, and K3. The CPU 34 controls the above-described color image processing device. In the test print mode, one of them is 512
* Prints a 512-dot patch at a predetermined density. In advance, the CPU 34 stores the gradation data at the corresponding patch address in the shared RAM 26. The test print control unit 24 sends the test print data of the RAM 26 to the MTF correction unit 32, and the MTF correction unit 32 outputs the data C3, M3,
Y3 and K3 are output to the print engine unit.

In the color image processing apparatus shown in FIG.
The block that processes between the HVC conversion unit 18 and the MTF correction unit 32 (portion surrounded by a broken line) is configured by a device whose circuit contents can be rewritten many times in a component mounted state. This device is, for example, a field programmable
This is a component called a gate array (FPGA). ROM3
6 stores algorithm information of a processing circuit for the FPGA. With respect to this FPGA, a plurality of functions can be achieved with a relatively small gate scale by the CPU 34 programming a circuit corresponding to the operation mode from the ROM 36. Explaining with reference to FIG.
In the test print mode, the circuit of the RAM 26 and the test print control unit 24 is programmed in the FPGA to rewrite the circuit contents, and the test print processing is performed. After this processing is completed, the density converter 22 and the
The circuit of the RAM 26, the masking operation unit 28, and the under color removal / black printing unit 30 are programmed to rewrite the circuit contents, and a process for image formation is performed. Note that the circuit written to the FPGA is configured to have almost the same volume in any mode.

FIG. 2 shows the configuration of the shared RAM 26. R
The AM 26 has four memories 260 for R, G, B, and W,
262, 264 and 266, which are shared by the test print control unit 18 and the density conversion unit 22. Selector 10
0, 102, 104, and 106, the select signal (MODESEL) input to each selector selects R
Address ADD of AM260, 262, 264, 266
RESS is switched between the test print control unit 24 and the density conversion unit 22. In the test print mode, the CPU 3
4 sets the mode selection signal MODESEL to 0,
26 is connected to the test print control unit 24. In the normal mode, the CPU 34 sets MODESEL to 1 and sets R
The AM 26 is connected to the density converter 22.

In the normal mode, the density converter 22
The R, G, and B data from the C conversion unit 18 are converted into densities DR, DG, and DB by -log conversion. The lookup table for the density conversion is handled by the shared RAM 26,
The PU 34 stores the converted data in the RAM 26 in advance. Further, the CPU sets the selectors 100, 102, 104, and 106 with MODESEL set to 0, and outputs the wavelength component data R5, G5, B5 and the saturation data W from the density converter 22 to the address of the shared RAM.
When the wavelength component data R5, G5, B5 and the saturation data W from the density converter 22 are input to the address of the common RAM 26, the corresponding density data DR, DG, DB, SW are output and returned to the density converter 22. It is. The density data DR, DG, DB, and SW from the density conversion unit 22 are further processed in the masking calculation unit 28 and the undercolor removal / black printing unit 30 and sent to the MTF correction unit 32. MTF correction unit 3
2 sends the data to the print engine unit after performing MTF correction according to the result of the area determination unit 20 and the like.

FIG. 3 shows an FPGA in the normal print mode.
Shows a block (including a density conversion unit, a masking operation unit, and an undercolor removal / ink printing unit) to be written. Shared RAM2
6 comprises memories 260, 262, 264, 266. R, G, B and W data are stored in RAMs 260 and 2 respectively.
Data DR, DG, DB, and SW that have been input to addresses 62, 264, and 266 and have been subjected to density conversion are output. R
The AM 26 functions as the density converter 22. The masking calculation unit 28 converts the DR, DG, DB, and SW data into C,
Convert to M, Y data. Finally, the undercolor removal / black printing section 30 performs the undercolor removal and black printing. here,
For the C, M, and Y data, the product of the saturation conversion data SW and the minimum value of the density data is subtracted from the masking operation result. C1 = C0−SW * MIN (DR, DG, DB) M1 = M0−SW * MIN (DR, DG, DB) Y1 = Y0−SW * MIN (DR, DG, DB) K data K1 is chroma conversion It is obtained by subtracting a predetermined value from the product of the data SW and the minimum value of the density data. K1 = SW * MIN (DR, DG, DB) -SD

In the test print mode, one of them is 512 * 5
A 12-dot patch is printed at a predetermined density. FIG.
The patch and the patch address when a test print is performed on A3 paper at 00 DPI are shown. 117 patches are printed on A3 paper. The numbers in the squares indicate the patch addresses. Each patch is printed with the gradation data stored in the shared RAM 26. In the shared RAM 26,
The gradation data is stored in the corresponding patch address.

FIG. 5 is a circuit block diagram written in the FPGA in the test print mode. The test print control unit 24 controls the dot counters 240 and 242 in the main (sub) scanning direction according to main scanning and sub-scanning effective area signals (not shown).
To work. The address control unit 244 sets HVA (VA) [15: 0] as the output, which is the position information, and
[7: 0] = HA [12: 9], VA [12: 9] and RA
M260, 262, 264, 266 are output to the address. The RAMs 260, 262, 264, and 266 store gradation data (C2, M2, Y) according to the input patch address.
, K2) is returned to the test print control unit 24.
The data is transferred to the F correction unit 32. The output data is set by the CPU 34 so as to pass through the MTF correction unit 32,
The TF correction unit 32 sends C2, M2, Y2, and K2 as they are to the print engine unit as C3, M3, Y3, and K3.

In the above-described embodiment, in the normal print mode, the shared memory 26
2, but is not limited to this block. Also, the blocks written in the FPGA in the print mode are from the density conversion unit 22 to the under color removal / black printing unit 30, but the invention is not limited to this. The HVC conversion unit 18, the scaling unit 18, and the like located upstream may be used as targets.

[0014]

As described above, in the image processing apparatus, blocks not used at the same time are shared by one block, so that the size and cost of the substrate can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a color image processing apparatus.

FIG. 2 is a block diagram of a shared RAM;

FIG. 3 is a diagram showing blocks written to an FPGA in a normal print mode.

FIG. 4 is a correlation diagram between an A3 document and a reference patch for automatic color selection determination.

FIG. 5 is a diagram showing blocks written to an FPGA in a test print mode.

[Explanation of symbols]

22, 28, 30 A part of the image processing unit, 24 test print control unit, 26 shared memory, 34 CPU,
36 ROM, 100, 102, 104, 10
6 selector, 260,262,264,266
memory.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideaki Mizuno 2-3-113 Azuchicho, Chuo-ku, Osaka-shi, Osaka Inside Osaka International Building Minolta Co., Ltd. (72) Inventor Nobuo Kamei Azuchi-cho, Chuo-ku, Osaka-shi, Osaka 2-3-13 Osaka International Building Minolta Co., Ltd. (72) Inventor Go Yoneyama 2-3-13 Azuchicho, Chuo-ku, Osaka City, Osaka Prefecture Osaka International Building Minolta Co., Ltd. F-term (reference) 2C087 AA15 BA03 BC05 BC07 BD24 BD35 BD36 CB04 DA02 5C062 AB22 AB43 AB46 AC04 AC21 AE03 BA02

Claims (3)

[Claims] 1. An image forming apparatus having a test printing mode, comprising: an image processing unit for processing image data; a test printing control unit for performing test printing; and a memory shared by the image processing unit and the test printing control unit. Switching means for connecting a test print control unit for controlling test printing to the memory during test printing, and connecting the image processing unit of the previous period to the memory during normal printing; An image processing apparatus comprising: storage means for storing test print data in a memory and storing conversion data for image processing in the memory during normal printing. 2. A test print control unit comprising a part of the image processing unit, the test print control unit, and a rewritable device. In the test print mode, the test print control unit is written in the device. The image processing apparatus according to claim 1, wherein a part of the image processing unit is written in the device. 3. The image processing unit according to claim 1, wherein a part of the image processing unit is a density conversion unit that converts image data into density data, and the memory stores conversion data for image data conversion. An image processing apparatus according to claim 1.