JP2001148430A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of improving charge holding characteristics without damaging the characteristics of the injection and extraction of electric charges. SOLUTION: An element isolation region 2 is formed on the surface of a semiconductor substrate 1 and N+ diffusion layers 7 are formed adjacently to the element isolation region 2 with an appropriate interval in an area sectioned by the element isolation region 2. A part between the N+ diffusion layers 7 is turned to a channel area and a tunnel oxidized film 3 is formed between the N+ diffusion layers 7 on the semiconductor substrate 1. A floating gate 4, an inter-gate insulation film 5 and a control gate 6 are successively laminated on the tunnel oxidized film 3, and a gate 10 is composed of the tunnel oxidized film 3, the floating gate 4, the inter-gate insulation film 5 and the control gate 6. For the tunnel oxidized film 3, the projection part 3b of a large film thickness is formed at a center and the thin parts 3a of small film thickness are formed at both ends. Data are written and erased at the thin parts 3a of the small film thickness on both sides.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a floating gate such as a flash memory cell, and more particularly to a nonvolatile semiconductor memory device having improved charge retention characteristics without impairing charge injection and extraction characteristics. The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, there is a flash memory device which is a kind of electrically rewritable and erasable nonvolatile memory element (EEPROM). FIG. 9 is a sectional view showing a conventional nonvolatile semiconductor memory device. In a conventional nonvolatile semiconductor memory device, an element isolation region 101 formed on a surface of a semiconductor substrate 100 is divided into element isolation regions 10.
1, a source region 102 (N ⁺ diffusion layer) and a drain region 103 (N ⁺ diffusion layer) are formed. On the semiconductor substrate 100, a tunnel oxide film 104 is formed over the source region 102 and the drain region 103. On the tunnel oxide film 104, a floating gate 105 made of polysilicon, an inter-gate insulating film 106, and a control gate 107 made of polysilicon are sequentially stacked. Note that a P-type well region 100a is formed between the source region 102 and the drain region 103.

In the above-described data writing and erasing in the nonvolatile semiconductor device, charge is injected between the floating gate 105 and the semiconductor substrate 100 via the tunnel oxide film 104 or
Or it is done by pulling out.

As a method of injecting and extracting electric charges (writing and erasing of data), there are a method in which the charge is applied from the entire surface of the semiconductor substrate 100 and a method in which the charge is inserted from the drain region 103 or the source region 102. When injecting and extracting charges from the entire surface of the semiconductor substrate 100, a potential difference is applied between the control gate 107 and the P-type well region 100a. Depending on the magnitude of this potential difference, charges are injected into the floating gate 105 or charges are drawn out into the semiconductor substrate 100.

When charge is injected or extracted from the drain region 103 or the source region 102, a potential difference is generated between the control gate 107 and the drain region 103 that extends (overlaps) immediately below the floating gate 105. By the application, charges are injected into the floating gate 105. Also, the source region 102 and the control gate 10
7, the potential difference between the floating gate 10
5 are extracted. These methods are selected depending on the use of the storage element or the circuit type. In any case, the thickness of the tunnel oxide film 104 is generally uniform immediately below the floating gate 105.

By the way, in order to facilitate injection and extraction of electric charges, that is, to lower the data writing and erasing voltage or to shorten the data writing and erasing time, a tunnel oxide film is required. It is desirable that the film thickness of 104 is as small as possible. However, from the viewpoint of data retention, that is, retention of charges accumulated in the floating gate 105, when the thickness of the tunnel oxide film 104 is small, the charges accumulated in the floating gate 105 are
04 easily leaks into the semiconductor substrate 100 through the semiconductor device 100, which is a fatal defect as a memory element. In general, when a floating gate holds electric charge, an electric field (self-electric field) is generated between the electric charge itself and other parts such as a semiconductor substrate, and the electric charge easily leaks in a part with poor insulation. Are known. When the floating gate holds electric charge, there is also a circuit operation as a storage element other than a write and erase operation such as data reading. At this time, a potential difference is generated to such an extent that data writing and erasing do not occur in the memory cell. The electric charge in the floating gate 105 easily leaks to the semiconductor substrate 100 due to the potential difference. Therefore, from the viewpoint of data retention, it is desirable that the tunnel oxide film be thick. Therefore, the thickness of the tunnel oxide film 104 is determined based on the conditions for writing and erasing data, the data holding characteristics, the transistor operating characteristics of the memory cell, and the like. Recently, the thickness of the tunnel oxide film 104 is generally around 10 nm.

However, recently, in nonvolatile semiconductor memory devices, there has been an increasing demand for lower operating voltage and higher speed of data writing and erasing. For this reason, the tunnel oxide film is required to be thinner, and is required to have good data retention characteristics and high reliability. Obtaining such a tunnel oxide film is a major issue.

Under such a background, Japanese Patent Laid-Open No. 9-92
No. 737 proposes a nonvolatile memory device in which a tunnel oxide film above a drain diffusion layer is locally thickened in order to prevent erroneous erasure due to a drain voltage. In this non-volatile memory device, since the upper portion of the drain diffusion layer is covered by the thick portion of the tunnel oxide film, the tunnel current from the floating gate electrode to the drain due to the drain voltage in the unselected cells can be suppressed, Erroneous electron extraction, that is, erroneous erasure can be prevented. This is because, in this prior art, when erasing, a tunnel current flows from the floating gate electrode to the source diffusion layer to extract electrons. Therefore, the thickness of the tunnel oxide film cannot be set large. Since the injection is performed by the hot electron injection generated by the formation, the injection position is in the channel portion near the drain diffusion layer, and the injection of the hot electrons does not significantly reduce the injection efficiency even if the tunnel oxide film is somewhat thick. Is described in the above publication.

[0009]

However, in the conventional nonvolatile semiconductor memory device described in the above-mentioned Japanese Patent Application Laid-Open No. 9-92737, there is a possibility that charges leak from the floating gate to the channel region. For this reason, this conventional technique has a problem that the data retention characteristics are low.

The present invention has been made in view of the above problems, and provides a nonvolatile semiconductor memory device capable of improving charge retention characteristics without impairing charge injection and extraction characteristics. With the goal.

[0011]

According to the present invention, there is provided a nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a pair of diffusion layer regions formed on the surface of the semiconductor substrate at an appropriate interval from each other; A first insulating film formed on the semiconductor substrate between the diffusion layer regions, a floating gate formed on the first insulating film, and a second insulating film formed on the floating gate; , A control gate formed on the second insulating film, at least one end of the first insulating film extends above the diffusion layer region, and the first insulating film has It is characterized in that the thickness of the other portion is thicker than the thickness of the portion on the diffusion layer region.

In the present invention, since the charge is injected and extracted from the diffusion layer region to the floating gate through the thin portion at the end of the first insulating film, the speed of data writing and erasing does not decrease. On the other hand, since the other portion of the first insulating film is thick, when a potential difference occurs between the semiconductor substrate and the control gate, leakage of electric charge in the floating gate can be suppressed extremely small. Therefore, the charge retention characteristics of the floating gate are improved. Therefore, data retention characteristics can be improved without affecting data writing and erasing.

In this case, both ends of the first insulating film extend above the diffusion layer region, and the thickness of the first insulating film at the central portion is larger than that at both ends. It can be configured to be thick. Accordingly, charge injection and extraction to the floating gate can be performed through both ends of the first insulating film. In this case, data can be written to one of the thin portions at both ends of the first insulating film and erased to the other. Further, the positions of data writing and erasing can be reversed.

When only one end of the first insulating film extends above the diffusion layer region, data is written and erased at a thin portion at the one end.

Further, the thin portion at the one end of the first insulating film has its gate-side end located closer to the gate center than the gate-center end of the diffusion layer region. Is preferred. Thus, it is possible to prevent the speed of injecting and extracting charges into and from the floating gate from decreasing.

Further, in the present invention, for example, the thickness of the first insulating film between the thick portion and the thin portion is continuously changed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 is a schematic sectional view showing the operation of the present embodiment. FIGS. 3A to 3C are cross-sectional views illustrating the steps of a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIGS. 4A and 4B are cross-sectional views of FIGS. FIGS. 4A to 4C are cross-sectional views showing the order of steps following the steps shown in FIGS.

In this embodiment, an element isolation region 2 is formed on the surface of a semiconductor substrate 1. This element isolation region 2
N ⁺ diffusion layers 7 (corresponding to a source region or a drain region) are formed adjacent to the element isolation region 2 at appropriate intervals. The space between the N ⁺ diffusion layers 7 becomes a channel region. A tunnel oxide film 3 is formed on the channel region, and both ends of the tunnel oxide film 3 extend on the N ⁺ diffusion layer 7. On this tunnel oxide film 3, a floating gate 4,
The inter-gate insulating film 5 and the control gate 6 are sequentially stacked. A gate portion 10 is formed by the tunnel oxide film 3, the floating gate 4, the inter-gate insulating film 5, and the control gate 6.

The tunnel oxide film 3 has a thick protrusion 3b formed at the center and a thin film 3a at both ends.
Are formed. The thickness of the projection 3b on the channel region is formed to be larger than the thickness of the end overlapping the N ⁺ diffusion layer 7. That is, in the vertical cross section of the semiconductor substrate 1, the semiconductor substrate 1 is formed in a convex shape with the channel region as a center. The thickness of the thin portion 3a is, for example, 9 nm, and the thickness of the projection 3b is, for example, about 15 nm. An inclined surface is formed between the thin portion 3a and the convex portion 3b.

The floating gate 4 and the control gate 6 are made of, for example, polysilicon and have a thickness of, for example, about 200 nm. The inter-gate insulating film 5 is made of, for example, a silicon oxide film and has a thickness of, for example, 2 in terms of a silicon oxide film.
It is about 0 nm. The N ⁺ diffusion layer 7 is formed immediately below the floating gate 4 by, for example, being diffused by about 150 nm in the thickness direction of the semiconductor substrate 1. The end of the N ⁺ diffusion layer 7 on the gate center side substantially coincides with the end of the thin portion 3a of the tunnel oxide film 3 on the gate center side. That is, the overlapping dimension of the N ⁺ diffusion layer 7 and the floating gate 4 is the thickness of the thin portion 3 of the tunnel oxide film 3.
a substantially coincides with the length of the semiconductor substrate 1 in the channel length direction. It is preferable that the end of the thin portion 3a of the tunnel oxide film 3 on the gate center side coincides with the end of the N ⁺ diffusion layer 7 on the gate center side or on the gate center side. That is, the length of the thin portion 3a of the tunnel oxide film 3 in the channel length direction of the semiconductor substrate 1 is preferably set to a dimension at which the N ⁺ diffusion layer 7 and the floating gate 4 overlap or longer. Thereby, the data writing speed and the data erasing speed can be maintained at high speed.

In this embodiment, the injection and extraction of charges into and from the floating gate 4 are performed not on the entire surface of the semiconductor substrate 1 but on the
It is assumed that the process is performed from the N ⁺ diffusion layer 7 corresponding to the drain region or the source region. That is, as shown in FIG. 2, charge injection and extraction from the N ⁺ diffusion layer 7 to the floating gate 4 through the thin portion 3a of the tunnel oxide film 3 are performed.
Therefore, the thin portion 3a of the tunnel oxide film 3 may have a thickness suitable for writing and erasing data. For this reason, the data writing and erasing speeds do not decrease as compared with the conventional nonvolatile semiconductor memory device. However, in other portions that do not contribute to the injection and extraction of charges, the thickness of the tunnel oxide film 3 is increased. Therefore, when a potential difference occurs between the P-type well region 2 and the control gate 6, Leakage of charges in the floating gate 4 can be suppressed to a very small level.
For this reason, the charge retention characteristics of the floating gate 4 are improved.
Therefore, the data retention characteristics can be improved without affecting the data writing and erasing speeds. When the thickness of the tunnel oxide film 3 is the same under the floating gate 4 and the ratio of the convex portions 3b of the tunnel oxide film 3 is half of the gate area, the amount of charge leakage is also almost half. Data retention time is doubled.

Next, the manufacturing method of this embodiment will be described with reference to FIG.
This will be described with reference to FIGS. 4A to 4C, FIGS. 4A and 4B, and FIG.

First, an element isolation region 2 is formed on a surface of a semiconductor substrate 1 made of, for example, silicon. Element isolation region 2
Is, for example, a silicon oxide film. This element isolation region 2
A P-type well region 1a is formed in a region defined by the above. A silicon oxide film 9 is formed on the surface of the partitioned region by, for example, a thermal oxidation method. The thickness of the silicon oxide film 9 is, for example, 20 nm. Note that the element isolation region 2, P
The method of forming the mold well region 1a and the silicon oxide film 9 is the same as that of a general transistor.

Next, as shown in FIG. 3B, a resist film 8 is formed on the semiconductor substrate 1, and the floating gate is narrowed, for example, by about 15 nm on one side, from the width of the semiconductor substrate 1 in the channel length direction. Pattern the resist film 8,
Using this as a mask, an impurity such as nitrogen is ion-implanted at an acceleration voltage of 20 keV and about 5 × 10 ¹⁴ cm ⁻² . At this time, as a through oxide film for ion implantation,
Using the silicon oxide film 9 left in the previous step, nitrogen is implanted through the silicon oxide film 9 into the semiconductor substrate 1 (silicon element) region not masked by the resist film 8. This makes it possible to change the oxidation rate of silicon between a portion where nitrogen is injected and a portion where nitrogen is not injected.

Next, as shown in FIG. 3C, after removing the silicon oxide film, a tunnel oxide film 3 is formed by, for example, a thermal oxidation method. The growth rate of the tunnel oxide film 3 is different between the region into which nitrogen is implanted and the region into which nitrogen is not implanted. In the region into which nitrogen is implanted, the growth speed of the oxide film is low, and the region into which nitrogen is not implanted. In this case, the growth rate of the oxide film is high. For this reason, the tunnel oxide film 3 grows in a convex shape in which the film thickness at the center of the partition region is large. When the central projection 3b is grown to a thickness of, for example, about 15 nm, the thickness of the thin sections 3a at both ends grows to about 9 nm. The injected nitrogen is taken into the tunnel oxide film 3, but it is known that there is almost no difference in the leak current characteristics.

Next, as shown in FIG. 4A, a first conductive film 40 serving as a floating gate is formed on the semiconductor substrate 1 so as to cover the tunnel oxide film 3. The first conductive film 40
For example, it is made of polysilicon, and its film thickness is, for example, 20
0 nm. Then, an insulating film 50 serving as an inter-gate insulating film is formed over the first conductive film 40. The insulating film 50 is, for example, a silicon oxide film. Further, a second conductive film 60 serving as a control gate is formed on the insulating film 50. The second conductive film 60 is made of, for example, polysilicon, and has a thickness of, for example, 200 nm.

In the present invention, the shape of the floating gate 4 may be different depending on the type of the memory cell. In this case, the floating gate 4 and the control gate 6 have a cross section as shown in FIG. In the figure, both gates appear to be patterned simultaneously, but in different shapes. However, in FIG. 4A, the difference in shape between the floating gate 4 and the control gate 6 is omitted. In such a case, when etching is performed for each gate, a different mask pattern is used. Therefore, after the floating gate 4 is patterned into a desired shape, an inter-gate insulating film 5 is formed on the floating gate 4, and a control gate 6 is formed on the inter-gate insulating film 5.

After the conductive film is formed, the floating gate and the control gate are appropriately doped by, for example, ion implantation or the like, and impurities are implanted.

Next, as shown in FIG. 4B, a resist film (not shown) is formed on the second conductive film, the resist film is patterned, and the second conductive film is masked. The film, the insulating film, the first conductive film, and the tunnel insulating film are sequentially dry-etched. By this step, a gate portion 10 is formed in the partitioned region, in which the tunnel oxide film 3, the floating gate 4, the inter-gate insulating film 5, and the control gate 6 are stacked in the same shape from the surface side of the semiconductor substrate 1. In this step, the etching may be performed continuously or in the same etching apparatus. Further, the etching apparatus can be changed between the etching of the first and second conductive films and the etching of the insulating film. The pattern of the tunnel oxide film 3 having a thickness partially different from that of the floating gate 4 does not match in a self-aligning manner, and a shift occurs due to a pattern conversion difference when the pattern of the floating gate 4 is formed. However, in a photolithography exposure apparatus generally used at present, a pattern can be adjusted with a shift amount of, for example, 50 nm or less, so that there is no practical problem in alignment.

Next, for example, phosphorus or arsenic is ion-implanted as an impurity into the surface of the semiconductor substrate 1 between the element isolation region 2 and the gate 10, and the impurity is injected in the horizontal direction of the semiconductor substrate 1 by, for example, a thermal diffusion method. To spread. By this step, the N ⁺ diffusion layer 7 is formed right below the thin portion 3a of the tunnel oxide film 3. Subsequent steps are the same as those of a general MOS transistor. Thus, a nonvolatile semiconductor memory device as shown in FIG. 1 is formed.

In this embodiment, since the impurities are diffused by the thermal diffusion method after the impurities are ion-implanted, the interface between the tunnel oxide film 3 and the N ⁺ diffusion layer 7 is not disturbed.

Next, a second embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 5 is a sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention,
6A to 6C are cross-sectional views showing the steps of a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment in the order of steps, and FIGS. 7A and 7B are sectional views of FIGS. 6A to 6C. FIGS. 8A and 8B are cross-sectional views showing the order of steps in the next step of FIGS. 7A and 7B. In addition,
The same components as those in the first embodiment shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0033] In this embodiment, as compared with the first embodiment, different sizes of N ⁺ diffusion layer 7a, 7b, N ⁺ diffusion layer 7a, the size of 7b is asymmetrical. N ⁺ small in towards the diffusion layer 7a, N ⁺ on the diffusion layer 7a is not formed tunnel oxide film 3. On the other hand, N ⁺ larger than the diffusion layer 7b, N ⁺ diffusion layer 7b thin portion 30a formed at one end of the tunnel oxide film 30 on the overlap. The difference is that the thickness of the portion not overlapping with the N ⁺ diffusion layer 7b is larger than the thickness of the thin portion 30a, and the other configuration is the same as that of the first embodiment. The end of the thin portion 30a on the gate center side coincides with the end of the N ⁺ diffusion layer 7a on the gate center side.

In this embodiment, the injection and extraction of the electric charge into and from the floating gate 4 is performed by using N
^{+ The} diffusion is performed via the thin portion 30a of the tunnel oxide film 30 on the diffusion layer 7b side. Therefore, the data writing and erasing speeds do not decrease as compared with the conventional one. Further, as compared with the first embodiment, it is possible to eliminate a useless gate area which does not improve the data holding characteristic. That is, since the area ratio of the thin portion 30a of the tunnel oxide film 30 to the gate area can be reduced, the area of the protrusion 30b increases, and the data retention characteristics can be further improved.

Further, the size of the N ⁺ diffusion layer 7a which is not involved in charge injection and extraction can be reduced. Therefore, the degree of integration can be increased. Further, the slope between the thin portion 30a and the convex portion 30b changes continuously to form a slope. Note that the end of the thin portion 30a on the gate center side is preferably closer to the gate center than the end of the N ⁺ diffusion layer 7a on the gate center side. As a result, the thickness of the tunnel oxide film 30 on the N ⁺ diffusion layer 7b is reduced, and the data writing and erasing speed can be maintained at a high speed.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS.
This will be described with reference to (a) and (b), FIGS. 8 (a) and (b), and FIG.

In the manufacturing method of this embodiment, since the process shown in FIG. 6A is the same as that of the first embodiment, a detailed description thereof will be omitted, and FIG. The process will be described from step (1). First, a resist film 8 is formed on a semiconductor substrate 1.
Then, the resist film 80 is patterned on one side, for example, about 15 nm narrower than the width dimension of the floating gate 4 in the channel length direction of the semiconductor substrate 1, and using this as a mask, an acceleration voltage of 20 keV, for example, nitrogen is used as an impurity. ^Implant ions of about 5 × 10 ¹⁴ cm ⁻² . Through this step, nitrogen is injected into a region which is one end of the floating gate, and the growth rate of the oxide film is changed.

Next, as shown in FIG. 6C, after removing the silicon oxide film, a tunnel oxide film 30 is formed by, for example, a thermal oxidation method. This tunnel oxide film 30 is thicker in a region where nitrogen is not implanted than in other portions. In the previous step, when the portion into which nitrogen is not implanted, that is, the protrusion 30b of the tunnel oxide film 30 is grown to a thickness of about 15 nm, for example, the portion into which nitrogen is implanted, that is, the thin portion of the tunnel oxide film 30 is formed. 30a grows to a thickness of about 9 nm.

Next, as shown in FIG. 7A, a first conductive film 40 serving as a floating gate is formed on the semiconductor substrate 1 so as to cover the tunnel oxide film 30. First conductive film 40
Is made of, for example, polysilicon, and its film thickness is, for example, 200 nm. Then, an insulating film 50 serving as an inter-gate insulating film is formed over the first conductive film 40. Insulating film 50
Is, for example, a silicon oxide film. Further, the insulating film 5
A second conductive film 60 serving as a control gate is formed on the gate electrode 0.
The second conductive film 60 is made of, for example, polysilicon, and has a thickness of, for example, 200 nm. After the conductive film is formed, the floating gate and the control gate are appropriately doped by, for example, ion implantation, and impurities are implanted.

Next, as shown in FIG. 7B, a resist film (not shown) is formed on the second conductive film, the resist film is patterned, and the second conductive film is The film, the insulating film, the first conductive film, and the tunnel insulating film are sequentially dry-etched. Through this step, the gate section 10 is formed.

Next, as shown in FIG. 8A, a resist film 81 is formed on the semiconductor substrate 1 so as to cover the gate portion 10, and one half of the tunnel oxide film 30 on the side of the convex portion 30b is formed of resist. Patterning so as to be covered with the film 81,
Using this resist film 81 as a mask, tunnel oxide film 3
As an impurity, for example, phosphorus or arsenic is ion-implanted into the exposed surface of the semiconductor substrate 1 on the side of the thin portion 30a, and the impurity is diffused in the horizontal direction of the semiconductor substrate 1 by, for example, a thermal diffusion method. By this step, N ⁺ diffusion layer 7 is formed right below thin portion 30a of tunnel oxide film 30.

Next, as shown in FIG. 8B, a resist film 82 is formed on the semiconductor substrate 1 so as to cover the gate portion 10, and one half of the N ⁺ diffusion layer 7a side
2 so as to be covered with the resist film 8
Using mask 2 as a mask, an impurity such as phosphorus or arsenic is ion-implanted into the exposed surface of semiconductor substrate 1 on the side of convex portion 30b of tunnel oxide film 30 to form N ⁺ diffusion layer 7b. In this case, in this embodiment, charge injection and extraction are not performed in the N ⁺ diffusion layer 7b, so that the N ⁺ diffusion layer 7b does not need to be formed immediately below the tunnel oxide film 30. Therefore, it is not necessary to diffuse the N ⁺ diffusion layer 7b in the horizontal direction of the semiconductor substrate 1. In this way, as shown in FIG. 5, the N ⁺ diffusion layers 7a and 7b are formed asymmetrically.

In this embodiment, the tunnel oxide film 30
After forming the, N ⁺ diffusion layer 7a, since the form 7b, never tunnel oxide film 30 and the N ⁺ diffusion layer 7a, the interface between 7b disturbed. Further, when the N ⁺ diffusion layer 7b is formed, the number of steps can be reduced because the diffusion of impurities becomes unnecessary.

[0044]

As described above in detail, according to the present invention, charge injection and extraction from the diffusion layer region to the floating gate through the thin portion at the end of the first insulating film are performed, so that data can be transferred. The speed of writing and erasing does not decrease. On the other hand, since the other portion of the first insulating film is thick, when a potential difference occurs between the semiconductor substrate and the control gate, leakage of electric charge in the floating gate can be suppressed extremely small. For this reason,
The charge retention characteristics of the floating gate are improved. Therefore, data retention characteristics can be improved without affecting data writing and erasing.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing the operation of the present embodiment.

FIGS. 3A to 3C are cross-sectional views illustrating a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention in the order of steps.

FIGS. 4A and 4B are cross-sectional views showing the next process of FIGS. 3A to 3C in the order of processes.

FIG. 5 is a sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIGS. 6A to 6C are cross-sectional views illustrating a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment in the order of steps.

FIGS. 7A and 7B are cross-sectional views showing the steps next to FIGS. 6A to 6C in the order of steps.

FIGS. 8A and 8B are cross-sectional views showing the steps next to FIGS. 7A and 7B in the order of the steps.

FIG. 9 is a cross-sectional view showing a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

1, 100; semiconductor substrate 1a, 100a; P-type well region 2, 101; element isolation region 3, 30, 104; tunnel oxide film 3a, 30a; thin portion 3b, 30b; convex portion 4, 105; floating gate 5, 106; inter-gate insulating films 6, 107; control gates 7, 7a, 7b; N ⁺ diffusion layers 8, 80, 81, 82; resist film 9; silicon oxide film 10; gate portion 40; Insulating film 60; second conductive film 102; source region 103; drain region

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BH09

Claims (6)

[Claims] 1. A semiconductor substrate, a pair of diffusion layer regions formed at an appropriate distance from each other on a surface of the semiconductor substrate, and a pair of diffusion layer regions formed on the semiconductor substrate between the diffusion layer regions. An insulating film, a floating gate formed on the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film. Wherein the first insulating film has at least one end thereof extending above the diffusion layer region, and the first insulating film has a portion other than a film thickness of a portion on the diffusion layer region. A non-volatile semiconductor storage device, characterized in that the film thickness is larger. 2. The first insulating film has both end portions extending above the diffusion layer region, and the first insulating film has a thickness at a central portion thereof larger than a thickness at both end portions thereof. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is thick. 3. The thin portion of at least one end of the first insulating film is such that the end on the gate center side is located closer to the gate center than the end of the diffusion layer region on the gate center side. The nonvolatile semiconductor memory device according to claim 1, wherein: 4. The method according to claim 1, wherein the thickness of the first insulating film is continuously changed between the thick portion and the thin portion.
4. The nonvolatile semiconductor memory device according to claim 1. 5. The nonvolatile semiconductor memory device according to claim 2, wherein data is written in one of thin portions at both ends of the first insulating film and data is erased in the other thin portion. 6. A method according to claim 1, wherein only one end of said first insulating film extends above said diffusion layer region, and data is written and erased in a thin portion of said one end. The non-volatile semiconductor storage device according to claim 1.