JP2001147864A - Data management device for flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data managing device of a flash memory suitable for preventing the deterioration of the life of a flash memory, and for quickly realizing the rewriting of data, and for realizing the update of the data with high reliability. SOLUTION: At the time of updating packet data, a new packet for storing data to be updated is generated in a packet part 72, and at the time of starting data writing, the state information of the packet is set in a third state, and the state information of a new packet is set in a first state, and the data to be updated are written in a new packet data part 82, and at the time of completing the data writing, the state information of the new packet is set in a second state, and the state information of the packet is set in a fourth state. Then, the packet whose state information is the second state or the third state is decided as a valid packet, and the packet whose state information is the first state or the fourth state is decided as an invalid packet.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for storing data in a storage area of a flash memory in units of packets, and more particularly to an apparatus for storing data in a storage area of a flash memory in units of data initialization in units of variable length packets. Related to a storage device. More specifically, a flash memory that is suitable for reducing the number of times of initialization of the flash memory, preventing a reduction in the life of the flash memory, performing high-speed data rewriting, and performing data updating with high reliability is provided. It relates to a data management device.

[0002]

2. Description of the Related Art Conventionally, as an apparatus for storing data in a storage area of a flash memory in packet units, for example,
There is a method of using a flash memory disclosed in Japanese Patent Application Laid-Open No. Hei 5-233426. In this method, a flash memory is divided into a plurality of sectors, a logical address portion, an erase management display portion, and a data portion are provided in each sector, and a sector is searched by a logical address. Then, when updating, the erasure enable flag in the erasure management display portion of the sector is turned on, the logical address is added to the empty sector, and the update data is written.

[0003] As a result, data is erased from the flash memory by setting an invalid flag indicating that the data is invalid in the erase manager of the sector storing the data to be erased. In addition, the number of times of initialization of the flash memory is reduced, and the life of the flash memory is prevented from being shortened, and data can be rewritten at high speed.

[0004]

However, in the conventional method of using a flash memory, when updating data in a sector, the data to be updated is written into a new sector, and the sector before updating is erased. In order to set an invalid flag in the management unit, for example, if a power failure, a system hang or a reset switch is accidentally turned on during data update, the erase management unit of the sector before update and the new sector Updating of the data is interrupted with the valid flag indicating that the data is valid, and there is a problem that it is difficult to identify which is the correct data.

[0005] In order to cope with such a problem, a block to which a sector before update belongs is once initialized, and then,
The data to be updated must be written to a new sector, and as a result, the number of times of initialization of the flash memory cannot be reduced. In this case,
It is necessary to rewrite the initialized block other than the sector before the update to the original state.

Accordingly, the present invention has been made in view of such an unsolved problem of the conventional technology, and has been made to reduce the number of times of initialization of the flash memory to reduce the life of the flash memory. It is an object of the present invention to provide a flash memory data management device suitable for preventing and rewriting data at a high speed and updating data with high reliability.

[0007]

According to a first aspect of the present invention, there is provided a flash memory data management device for storing data in a storage area of a flash memory in packet units. The packet includes a management unit for storing management data relating to management of the packet, and a data unit for storing data to be stored. The management unit includes the packet as the management data. State information indicating two different states can be stored. When storing data, a packet for storing data to be stored is generated in the storage area, and when the data writing is started, the packet is stored in the storage area. The state information is set to a first state indicating that new data is being written, the data to be stored is written in the data portion of the packet, and the data is written. When the data writing is completed, the status information of the packet is set to a second status indicating that the new writing of data is completed, and the packet whose status information is the second status is determined to be a valid packet. Then, the packet whose status information is in the first status is determined to be an invalid packet.

With such a configuration, when storing data, first, a packet for storing the data to be stored is generated in the storage area.
The state information of the packet is set to the first state. Then, data to be stored is written in the data portion of the packet, and when the data writing is completed, the status information of the packet is stored in the second portion.
Is set to the state.

For example, when data writing is interrupted for some reason, a packet whose status information is in the second state is determined to be a valid packet, and a packet whose status information is in the first state is determined. It is determined that the packet is invalid.

Therefore, the data is not identified as a valid packet until data writing is completed. For example, when updating data, the data to be updated is written in a new packet, but the new packet is not identified as a valid packet until the data writing is completed. Even if the data writing is interrupted for some reason until the completion, the packet before the update is identified as the correct data.

Here, the packet may have any data length, may have a fixed length, or may have a variable length.

Further, according to a second aspect of the present invention, in the data management apparatus for a flash memory according to the first aspect, the status information indicates two further different states of the packet. When updating the data of the packet, a new packet for storing the data to be updated is generated in the storage area, and the state information of the packet is updated at the start of data writing. The third to indicate that
And the state information of the new packet is stored in the first
And writing the data to be updated in the data portion of the new packet. When the data writing is completed, the state information of the new packet is set to the second state and the state information of the packet is set to the data state. A fourth state indicating that the update has been completed is set, the state information determines that the packet in the second state or the third state is a valid packet, and the state information indicates the first state. Or the packet in the fourth state is determined to be an invalid packet.

With this configuration, when updating the data of a packet, a new packet for storing the data to be updated is first generated in the storage area. The state information of the packet is set to the third state, and the state information of the new packet is set to the first state. Then, the data to be updated is written to the data portion of the new packet, and when the data writing is completed, the status information of the new packet is set to the second status and the status information of the packet before the update is set to the fourth status. Is done.

For example, if the update of data is interrupted for some reason, the status information is changed to the second status or the third status.
Is determined to be a valid packet, and a packet whose status information is the first state or the fourth state is determined to be an invalid packet.

Therefore, a new packet is not identified as a valid packet until the data update is completed.

Here, the state information of the new packet is
The order in which the state information of the packet before the update and the state information of the packet before the update are set to the fourth state may be any order, but the state information of the new packet is set to the second state before the state before the update. It is more preferable to set the state information of the packet in the fourth state. This is a case where the packet before the update is a valid packet even if the data update is interrupted for some reason after the state information of the new packet is changed and before the state information of the packet before the update is changed. Is determined.

The order in which the state information of the packet is set to the third state indicating that the data is being updated and the state information of the new packet is set to the first state may be any order.

Furthermore, a flash memory data management device according to a third aspect of the present invention is the flash memory data management device according to any one of the first and second aspects, wherein the packet has a variable length; The management unit can store, as the management data, data length information indicating a data length of the packet, and specify a storage position of the packet based on the data length information. .

With such a configuration, the storage area includes:
A variable length packet is stored, and the storage position of the packet is
It is specified based on the data length information.

According to a fourth aspect of the present invention, there is provided a data management apparatus for a flash memory, wherein the data management apparatus for a flash memory according to any one of the first to third aspects stores data in the storage area in packet units. An apparatus for updating the storage area using another storage area different from the storage area, wherein the storage area includes an area management unit for storing area management data related to management of the storage area, A packet section for storing a packet, wherein the area management section can store, as the area management data, area state information indicating four different states of the storage area; When updating, the area status information of the storage area at the start of data writing is set to a third state indicating that data is being updated, and the other storage area is not updated. The area status information is set to a first state indicating that new data is being written, and data of a valid packet in the storage area is written to a packet portion of the another storage area. The area state information of another storage area is set to a second state indicating that new writing of data is completed, and the area state information of the storage area is set to a fourth state indicating that updating of data is completed. Determining that the storage area in which the area state information is the second state or the third state is a valid storage area, and the area state information is the first state or the fourth state. The storage area is determined to be an invalid storage area.

With this configuration, when updating the storage area due to the lack of an area for writing data in the storage area, the area state information of the storage area before the update is set at the start of data writing. The area state information of another storage area to be updated in the third state is set to the first state. Then, the data of the valid packet in the storage area before the update is written into the packet portion of the other storage area, and when the data writing is completed, the area state information of the other storage area is changed to the second state and the storage state before the update is stored. The area state information of the area is set to the fourth state.

For example, if the update of the storage area is interrupted for some reason, the storage area whose status information is in the second state or the third state is determined to be a valid storage area, and the status information is stored in the second state. It is determined that the storage area in the first state or the fourth state is an invalid packet.

Therefore, until the storage area is completely updated, another storage area to be updated is not identified as a valid storage area.

Here, when the flash memory is composed of a plurality of storage areas, another storage area to be updated only needs to be the number of the storage areas at which the storage areas are updated simultaneously. The number of simultaneous updates of the storage area depends on the design of the system, but in general, a plurality of storage areas are not updated at the same time.
One of the storage areas of the flash memory is sufficient.

When updating a storage area, data of a valid packet in the storage area is written into a packet portion of another storage area. However, from the viewpoint of effectively using another storage area. It is preferable that the data of the effective packet in the storage area is written in the packet portion of another storage area so that the arrangement position is ordered.

Here, the order in which the area state information of another storage area is set to the second state and the area state information of the storage area is set to the fourth state may be any order. In addition, the order in which the area state information of the storage area is set to the third state and the area state information of another storage area is set to the first state may be any order.

According to a fifth aspect of the present invention, in the data management apparatus for a flash memory according to the fourth aspect of the present invention, the area status information is the first status or the fourth status. The storage area in the state is used as the another storage area.

With this configuration, after the storage area is updated at least once, the storage area whose area state information is in the first state or the fourth state is used as another storage area. .

According to a sixth aspect of the present invention, there is provided a data management apparatus for a flash memory according to any one of the fourth and fifth aspects, wherein the area status information of the storage area and A process for the storage area or the another storage area is executed by referring to a processing definition table to which a processing for the storage area or the another storage area is assigned according to a state of the area state information of another storage area. It has become.

With such a configuration, the processing for the storage area before the update or another storage area to be the update destination is executed with reference to the processing definition table.

Here, the contents of the process definition table are specifically as follows. When the area state information of the storage area before the update is in the fourth state and the area state information of another storage area to be updated is in the first state, the data of the valid packet in the storage area before the update Is written to the packet portion of another storage area. The area status information of the storage area before the update is the fourth
In this state, and the area state information of another storage area is the second state, the storage area before updating is initialized. When the area state information of the storage area before the update is opposite to the area state information of another storage area, the processing for the storage area or another storage area is also reversed.

Although the area state information indicates four different states of the storage area, the fifth state indicates that the storage area is not initialized, that is, the fifth state indicates that the storage area is not initialized. And the sixth state indicating that the storage area has been initialized, the contents of the process definition table are specifically as follows.

If the area state information of the storage area before the update is in the third state and the area state information of another storage area to be updated is in the first state, another storage area is initialized. . When the area state information of the storage area before the update is in the fourth state and the area state information of another storage area is in the second state, the storage area before the update is initialized. When the area state information of the storage area before the update is in the third state and the area state information of another storage area is in the fifth state, another storage area is initialized. When the area state information of the storage area before the update is in the third state and the area state information of another storage area is in the sixth state, the valid packet data of the storage area before the update is stored in another storage area. Write to the packet part of the area.
When the area state information of the storage area before the update is opposite to the area state information of another storage area, the processing for the storage area or another storage area is also reversed.

With such a configuration, even if the processing is interrupted during initialization of the storage area before update, update of another storage area, or writing data to another storage area. When the system is restarted, processing to be performed from the time of interruption is executed, so that the storage area is appropriately updated. Therefore, data can be updated with higher reliability.

According to a seventh aspect of the present invention, there is provided the data management apparatus for a flash memory according to any one of the first to sixth aspects, wherein the storage area is a data storage device for the flash memory. It consists of an initialization unit.

With this configuration, when data is stored and updated in the storage area of the flash memory in packet units, the data is stored in the storage area composed of data initialization units. When the storage area is updated, the update is performed for each storage area composed of data initialization units.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 13 are diagrams showing an embodiment of a data management device for a flash memory according to the present invention.

In this embodiment, as shown in FIG. 1, the flash memory data management device according to the present invention is required for setting the computer 100 in a block consisting of a data initialization unit of a flash ROM 52 as a flash memory. Data (for example, IP address, URL of the WWW (World Wide Web) server to be accessed (Universa
l Resource Locater)) is applied to the case where data is stored in units of variable-length packets.

First, the configuration of a computer to which the data management device for flash memory according to the present invention is applied will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of the computer 100.

As shown in FIG. 2, the computer 100 has a CPU 50 for controlling the operation and the entire system based on the control program, and a CPU in a predetermined area in advance.
Flash RO storing 50 control programs, etc.
An M52, a RAM 54 for storing data read from the flash ROM 52 and the like, and a calculation result required in a calculation process of the CPU 50, a graphic chip 56 for converting data stored in the VRAM 55 into an image signal and outputting the image signal, I that mediates data input / output to / from the device
/ F 58, which are connected to each other and capable of exchanging data via a bus 59 which is a signal line for transferring data.

The I / F 58 has, as an external device, an LCD (Liquid Cry) capable of inputting data as a human interface and displaying a screen based on image signals.
A touch panel 60 made of stalDisplay) is connected. In addition, although not shown, a speaker for outputting sound, a signal line for connecting to the Internet, and the like are connected.

The graphic chip 56 includes a VRAM 55
Are sequentially read at a predetermined cycle from the head address, and the read display data is converted into an image signal and output to the touch panel 64.

Next, the configuration of the flash ROM 52 is shown in FIG.
This will be described with reference to FIG. FIG. 2 is a diagram showing the data structure of blocks A and B.

The flash ROM 52 is composed of a data rewritable nonvolatile storage element. As shown in FIG. 2, the storage area is logically divided into a plurality of blocks each composed of a data initialization unit. The two blocks A and B are used as a data write area for writing data and a data update area used when updating a block. In the flash ROM 52, for example, in an initialized state (a state in which data is written after being initialized), the data bit of the storage area is “1”.

Each of the blocks A and B comprises an area management section 70 for storing area management data relating to block management, and a packet section 72 for storing packets. When the area is a data update area, the other area is a data update area, and when the other area is a data write area, one area is a data update area. Data writing is performed on a block that is to be a data writing area. On the other hand, the update of the block is performed by the packet unit 7 of the block serving as the data write area.
2 is performed when the area for writing data is insufficient, and the valid packet data of the packet section 72 of the block serving as the data write area is arranged in order such that its arrangement position is ordered. This is performed by writing to the packet section 72 of the block that is to be the data update area. And
When the data writing to the packet section 72 is completed, the block serving as the data update area is set as the data write area, and the block serving as the data write area is set as the data update area.

As shown in FIG. 3, the area management section 70 stores an area 70a for storing initialization number information indicating the number of block initializations and area state information 1 to 5 indicating five different states of the block. Areas 70b to 70f, and the areas 70a to 70f
It has a storage capacity of two data read units (for example, 4 bytes (32 bits)). FIG. 3 shows the area management unit 7.
It is a figure showing the data structure of 0.

Each of the area status information 1 to 5 is configured as shown in FIG. FIG. 4 is a diagram showing the contents of the area state information.

The area state information 1 is information indicating that the block has been initialized (initialization completed state), as shown in the first column of FIG. Is written in the area 70b.
The area state information 2 is information indicating that data is being written to the block (data writing state), as shown in the second item in the upper part of FIG. 4, and is referred to as “STUP”. The data is written to the area 70c as 4-byte write information.
As shown in the third item in the upper part of FIG. 4, the area state information 3 indicates that data writing to the block has been completed, and that data can be additionally written to the packet portion 72 of the block (data writing). Information indicating the status of “NOR”
M "is written to the area 70d as 4-byte write information.

The area state information 4 is information indicating that data is being moved from the block (data is being moved) in order to update the data of the block, as shown in the fourth item in the upper part of FIG. Then, it is written into the area 70e as 4-byte write information "MOVE". The area state information 5 is information indicating that data movement from the block has been completed (data movement completed state), as shown in the fifth item in the upper part of FIG. Is written in the area 70f.

The area status information 1 to 5 are written in the respective areas 70b to 70f in that order. Therefore, for example, the area state information 3 is not written when the area state information 1 and 2 are not written, and is not written even when the area state information 4 and 5 are written. A state in which none of the area state information 1 to 5 has been written or a state in which the area state information 1 to 5 has not been written in that order means that the block has never been initialized (uninitialized). State)
handle.

The packet section 72 includes a flash ROM 52
Has a storage area of a predetermined capacity which is a multiple of a data read unit (for example, 4 bytes), and as shown in FIG. 5, can store a plurality of packets P _{1 to} P _n of variable length. Each of the packets P _{1 to} P _n includes a management unit 80 for storing management data relating to packet management, and a data unit 82 for storing data to be stored.
2 are sequentially generated from the start address to the end address. FIG. 5 is a diagram illustrating a data structure of the packet unit 72.

As shown in FIG. 6, the management unit 80 stores an area 8 for storing state information indicating five different states of the packet.
0a, an area 80b for storing ID information indicating an ID for identifying a packet, and an area 80c for storing serial number information indicating a serial number assigned in the order in which the packets were generated.
And an area 80d for storing data length information indicating the data length of the data section 82. Each of the areas 80a to 80d includes
The management section 80 as a whole has a storage capacity of a data read unit (for example, 4 bytes (32 bits)) of the flash ROM 52. FIG. 6 is a diagram illustrating a data structure of the management unit 80.

The state information is different from the area state information.
It shows five different states of the packet by one data stored in the area 80a, and is configured as shown in FIG. FIG. 7 is a diagram showing the contents of the state information.

The state information indicates, as the first state, that data is being written to the packet (data writing state). In this case, the 1-byte write information “7FH” is stored in the area 80a. Written. The second state indicates that data writing to the packet has been completed (data write completed state). In this case, the most significant bit of “1” in the write information indicating the first state is “2”. "3F" set to "0"
"H" is written in the area 80a as 1-byte write information. The third state indicates that the data of the packet is being updated (data updating state). In this case, the most significant bit of “1” of the write information indicating the second state is set to “0”. The data is written to the area 80a as the set 1-byte write information “1FH”.

The state information indicates, as the fourth state, that the data update of the packet has been completed (data update completed state). In this case, the most significant bit of “1” of the write information indicating the third state Is set to “0” and is written to the area 80a as 1-byte write information of “0FH”. In addition, the fifth state indicates that the packet is unused (unused state). In this case, 1 is referred to as “FFH”.
The data is written to the area 80a as byte write information (that is, in the initialized state).

The state information is stored in the area 8 in the order of the fifth state, the first state, the second state, the third state, and the fourth state.
0a. So, for example,
When the state information is the third state, the state does not change to the first state or the second state unless the block to which the packet belongs is initialized.

As shown in FIG. 8, the flash ROM 52 stores a process definition table in which processes for the blocks A and B are assigned according to the state of the area state information of the blocks A and B. FIG. 8 is a diagram illustrating a data structure of the process definition table.

The process definition table is configured as shown in FIG.

If the state of the block A is in data movement and the state of the block B is not initialized or data is being written, the block B is initialized. When the state of the block A is moving data and the state of the block B is initialization completed, the data of the valid packet of the block A is written into the packet section 72 of the block B,
Update block A to block B. When the state of the block A is writing data and the state of the block B is uninitialized or the initialization is completed, the state of the block A is data moving and the state of the block B is data writing completed. At this time, or when the state of the block A is data movement completed and the state of the block B is uninitialized, initialization completed, data writing or data writing completed, the block A is initialized. When the state of the block A is data writing completed and the state of the block B is uninitialized, initialization completed, or data writing is being performed, the block A is used as a data writing area.

If the state of the block B is data movement and the state of the block A is not initialized or data is being written, the block A is initialized. Block B
Is in a data transfer state and the state of block A is initialization completed, the block B is updated to block A by writing valid packet data of block B into the packet section 72 of block A. . Block B
Is in data writing and the state of block A is uninitialized or initialization completed, when the state of block B is data movement and the state of block A is data writing completed, Alternatively, when the state of the block B is the data movement completion and the state of the block A is uninitialized, initialization completed, data writing or data writing completed, the block B is initialized. The state of block B is data write completed and the state of block A is uninitialized,
When the initialization is completed or data is being written, block B is used as a data writing area.

When the state of the block A is uninitialized or the initialization is completed and the state of the block B is uninitialized or the initialization is completed, the initialization processing for the blocks A and B is performed.

Returning to FIG. 1, the CPU 50 comprises a microprocessing unit MPU or the like, activates a predetermined program stored in a predetermined area of the flash ROM 52, and executes the data writing of FIGS. Read processing, data read processing, and block update processing are performed in parallel.

First, the data writing process will be described with reference to FIG. FIG. 9 is a flowchart showing the data writing process.

The data write process is executed when new data is written or updated in blocks A and B in units of packets. In the initial state, block A is used as a data write area. After that, the data is written into a block that becomes a data writing area according to the processing.
When executed in, as shown in FIG. 9, the process first proceeds to step S100.

In step S100, the flash ROM
The data write request from another process (other than the processes shown in the flowcharts of FIGS. 9 to 13) for writing data to the data 52 is a new data write request or the data of the packet. Judge whether it is an update request of
When it is determined that the request is a new data write request (Yes),
The process proceeds to step S101 to determine whether or not the block update has been completed. When it is determined that the block update has been completed (Yes), the process proceeds to step S102, but when it is determined that the block update has not been completed. (No), the process stands by in step S101 until the block update is completed.

In step S102, it is determined whether or not an area for generating a packet for storing data to be stored is insufficient in the packet section 72. If it is determined that it is at 72 (No), the process moves to step S104.

In step S104, a packet for storing data to be stored is generated in the packet unit 72,
Move to step S108. In step S104, specifically, when no packet is generated in the packet section 72, a packet is generated from the head address of the packet section 72, and when a packet is already generated in the packet section 72, The packet is generated from the address next to the end address of the packet at the end counted from the start address of the packet section 72. When a packet is generated, ID information indicating an ID different from the ID given to another packet, a serial number indicating the order in which the packet is generated, and data length information indicating the data length of data to be stored Are written into the management unit 80, and the state information is set to the first state.

In step S108, the data to be stored is written in the data section 82 of the generated packet, and the flow shifts to step S110 to set the state information of the generated packet to the second state, and ends a series of processing. I do.

On the other hand, if it is determined in step S100 that the data write request from the above other processing is a request to update the data of the packet (No), the flow shifts to step S113 to complete the update of the block. When it is determined that the update of the block has been completed (Yes), the process proceeds to step S114, but when it is determined that the update has not been completed (No), the process is performed until the update of the block is completed. Step S1
Wait at 13.

In step S114, it is determined whether or not an area for generating a packet for storing data to be updated is insufficient in packet section 72, and a sufficient area for generating the packet is determined in the packet section. If it is determined that it is at 72 (No), the process moves to step S116.

In step S116, a new packet for storing data to be updated is generated in the packet section 72, and the flow advances to step S118. This step S1
16, when the packet is generated, an ID indicating the same ID as the ID given to the packet before the update is used.
Information, a sequential number indicating the order in which this packet is generated,
Then, data length information indicating the data length of the data to be updated is written in the management unit 80, and the state information is set to the first state. Note that the location where the packet is generated
This is the same as step S104 described above.

In step S118, the state information of the packet before update is set to the third state, and the flow shifts to step S122 to write the data to be updated in the data portion 82 of the new packet, and shifts to step S124. Then, the state information of the new packet is set to the second state, and the process proceeds to step S126, where the state information of the packet before update is set to the fourth state, and a series of processing ends.

On the other hand, when it is determined in step S114 that an area for generating a packet for storing data to be updated is insufficient in packet section 72 (Yes).
Shifts to step S132, outputs a block update request for updating the block, shifts to step S134, determines whether the block update is completed, and determines that the block update is completed. If (Yes), the process proceeds to step S116. If not (No), the process proceeds to step S116 until the block update is completed.
Wait at 134.

On the other hand, when it is determined in step S102 that the area for generating the packet for storing the data to be stored is insufficient in the packet section 72 (Yes).
Shifts to step S128, outputs a block update request to update the block, shifts to step S130, determines whether the block update is completed, and determines that the block update is completed. If the update is performed (Yes), the process proceeds to step S104. If not (No), the process proceeds to step S104 until the block update is completed.
Wait at 130.

Next, the data reading process will be described with reference to FIG. FIG. 10 is a flowchart showing the data reading process.

The data reading process is a process executed when data is read from the blocks A and B in packet units.
As shown by 0, the process first proceeds to step S200.

In step S200, data length information is obtained from the packet management unit 80, and the flow advances to step S202 to execute another data read operation to the flash ROM 52 based on the obtained data length information. The storage position of the packet having the ID information matching the ID information given from the processing (other than the processing shown in the flowcharts of FIGS. 9 to 13) is specified, and step S204 is performed.
Move to

In step S204, it is determined whether or not the packet whose storage position is specified is valid. If it is determined that the packet is valid (Yes), step S206 is performed.
Move to In this step S204, the validity / invalidity of the packet is determined as follows. When the state information of the packet is the second state or the third state, it is determined that the packet is valid. When the state information of the packet is the first state or the fourth state, the packet is determined to be valid. Is determined to be invalid.

In step S206, data is read from the data portion 82 of the packet whose storage position has been specified, and the process proceeds to step S208, where the packet whose storage position has been specified is the last packet counted from the start address of the packet portion 72. If it is determined that the packet is not the last one (No), the process proceeds to step S200, but if not (Yes), a series of processes is terminated.

On the other hand, if it is determined in step S204 that the packet whose storage position is specified is invalid (No),
Move to step S208.

Next, the block update processing will be described with reference to FIG. FIG. 11 is a flowchart showing the block update processing.

The block update processing is performed in step S12
In response to the block update request output in step 8, block A,
B is a process for updating B, and when executed by the CPU 50, first, as shown in FIG.
Move to

In step S300, the processing for blocks A and B is executed with reference to the processing definition table shown in FIG.
128 to determine whether there is a block update request,
When it is determined that there is a block update request (Yes), the process proceeds to step S304.

In step S304, it is determined whether or not block A is valid. If it is determined that block A is valid (Yes), the process proceeds to step S306. In this step S304, the validity / invalidity of the block is determined as follows. When the area status information 3 and 4 are stored in the area management unit 70 of the block, it is determined that the block is valid, and the area status information 1, 2, and 5 is stored in the area management unit 70 of the block. When the block is present or when the state of the block is not initialized, it is determined that the block is invalid.

In the step S306, the area status information 4 is written in the area management section 70 of the block A, and in the step S3
Move to 00.

On the other hand, when it is determined in step S304 that block A is invalid (No) (in this case, since block B should be valid, that is, when block B is determined to be valid), Then, the process shifts to step S308 to write the area state information 4 to the area management unit 70 of the block B, and shifts to step S300.

On the other hand, when it is determined in step S302 that there is no block update request in step S128 (No), the process proceeds to step S300.

Next, the processing based on the processing definition table in step S300 will be described with reference to FIGS. FIG. 12 and FIG.
9 is a flowchart showing processing based on the processing definition table.

When the process based on the process definition table in step S300 is executed in step S300, the process first proceeds to step S400 as shown in FIG.

In step S400, the area state information of blocks A and B is obtained, and the flow proceeds to step S402.
Referring to the processing definition table shown in FIG. 8, the processing for blocks A and B is selected from the acquired area state information.

As a result of the selection in step S402, when the processing for initializing the block A is selected (), the process proceeds to step S404 to initialize the block A, and then proceeds to step S406 to initialize the block A. "1"
The addition is performed and the initialization number information is written to the area management unit 70 of the block A, and the process proceeds to step S408, where the area state information 1 is written to the area management unit 70 of the block A, and a series of processing is ended.

On the other hand, when the process of initializing the block B is selected as a result of the selection in the step S402 (), the process shifts to the step S410 to initialize the block B, shifts to the step S412, and shifts to the step S412. Is added to the initialization number of the block B, and the initialization number information is written to the area management unit 70 of the block B, and the process proceeds to step S414.
The area state information 1 is written in the area management unit 70 of the block B, and a series of processing ends.

On the other hand, when the process of updating block B to block A is selected as a result of the selection in step S402
() Moves to step S416, writes the area state information 2 to the area management unit 70 of block A, and executes step S416.
The process proceeds to 418, where the data of the valid packet of block B is written to the packet section 72 of block A so that its storage position is ordered, and the procedure proceeds to step S420, where the area management section 70 of block A is written. Is written in the area management unit 70 of the block B, and the series of processes is completed.

On the other hand, when the process of updating block A to block B is selected as a result of the selection in step S402
() Moves to step S424, writes the area state information 2 to the area management unit 70 of block B, and proceeds to step S424.
The flow shifts to 426, where the valid packet data of block A is written to the packet section 72 of block B such that the storage positions are ordered, and the flow shifts to step S428, where the area management section 70 of block B is written. Is written to the area management unit 70 of the block A, and the series of processes is completed.

On the other hand, as a result of the selection in step S402, if the process of using block A as the data write area is selected (), the flow shifts to step S432 to set block A as the data write area, and proceeds to step S433. Then, the block update request is released, and a series of processing ends.

On the other hand, as a result of the selection in step S402, when the process of using the block B as the data write area is selected (), the flow shifts to step S434, where the block B is set as the data write area, and in step S435. Then, the block update request is released, and a series of processing ends.

On the other hand, as a result of the selection in step S402, when the processing for performing the initialization processing on the blocks A and B is selected (), the flow shifts to step S436 to initialize the blocks A and B, and then proceeds to step S438. Then, the area state information 1 is written to the area management unit 70 of the block A,
A series of processing ends.

On the other hand, if none of the above processes is selected (×) as a result of the selection in step S402, a series of processes is terminated.

Next, the operation of the above embodiment will be described with reference to the drawings.

First, a case where new writing of data to blocks A and B is performed in packet units will be described.

In the initial state, block A is used as a data write area, and data is written to block A. When a new data write request is received from another process that attempts to write data to the flash ROM 52,
New writing of data to block A, which is a data writing area, is started. At this time, data to be stored and ID information are given together with the new data write request.

The new writing of data is performed as follows. Steps S100 to S by the CPU 50
Through 110, a packet for storing data to be stored is generated in the packet section 72 of the block A. At this time, the acquired ID information, a serial number indicating the order in which the packets are generated, and data length information indicating the data length of the data to be stored are written in the management unit 80, and the state information is stored in the first state. (During data writing). Then, the data to be stored is written in the data portion 82 of the generated packet, and the state information of the generated packet is set to the second state (data writing completed).

In a normal state in which data writing is not interrupted, data is written as a packet in the packet section 72 of the block A as described above. For example, when data writing is interrupted for some reason, It operates as follows.

When the data writing is interrupted, after the system is restarted, if a data read request is received from another process for reading data from the flash ROM 52, the block A is still in the state. Since the area is a data write area, data reading for block A is started. At this time, it is assumed that the same ID information has been given from the other processing together with the data reading request.

Reading of data is performed as follows. C
Through steps S200 and S202 by the PU 50,
Data length information is acquired from the packet management unit 80, and a storage position of a packet having ID information that matches the ID information given from the other processing is specified based on the acquired data length information. At this time, the writing of the data of the packet whose storage position is specified has been interrupted, and the state information thereof is in the first state.
After S4, S208, it is determined that the packet is invalid, and the data is not read.

If the data writing is not interrupted and the data writing is completed normally and a data read request is received, the data length information is sent from the packet management unit 80 via steps S200 and S202. Based on the acquired and acquired data length information, I
The storage position of the packet having the ID information matching the D information is specified. At this time, since the state information of the packet whose storage position is specified is in the second state, it is determined as a valid packet through steps S204 and S206, and the packet whose storage position is specified is Data is read from the data section 82.

In the above description, the case where data is newly written to the block A has been described. However, the case where data is newly written to the block B operates in the same manner as described above.

Next, a case will be described in which data is updated for blocks A and B in packet units. It should be noted that some packets have already been generated in the block A, and here, any data of those packets is updated.

In the initial state, block A is used as a data write area, and data is written to block A. When a data update request is received from another process that attempts to update data in the flash ROM 52, data update is started for the block A that is a data write area. At this time, along with the data update request, data to be updated and ID information of a packet to be updated are provided.

The data is updated as follows. C
Steps S112 to S126 by the PU 50
, A new packet for storing the data to be updated is generated in the packet unit 72 of the block A. At this time, the acquired ID information, a serial number indicating the order in which the packets are generated, and data length information indicating the data length of the data to be updated are written in the management unit 80, and the state information is stored in the first state. (During data writing). Then, the state information of the packet before update is set to the third state (data is being updated), the data to be updated is written to the data part 82 of the new packet, and the state information of the new packet is set to the second state. (Data writing completed) and the state information of the packet before updating is set to the fourth state (data updating completed).

In the normal state where the data update is not interrupted, the data is written and updated in the packet section 72 of the block A as described above. For example, if the data update is interrupted for some reason, It operates as follows.

When the data update is interrupted, after the system is restarted and a data read request is received from another process for reading data from the flash ROM 52, the block A is still in the data state. Since the area is a write area, data reading from the block A is started. At this time, it is assumed that the same ID information has been given from the other processing together with the data reading request.

Reading of data is performed as follows. C
Through steps S200 and S202 by the PU 50,
Data length information is acquired from the packet management unit 80, and a storage position of a packet having ID information that matches the ID information given from the other processing is specified based on the acquired data length information. At this time, since the packet before update is stored at the start address side of the packet unit 72 than the new packet, the storage position of the packet before update is specified first. Since the update of the data has been interrupted and the state information is in the third state, it is determined that the packet is a valid packet through steps S204 and S206, and the data is read from the data section 82 of the packet. . On the other hand, since data to be updated is written only halfway in the new packet, no data is read from the data portion 82 of the new packet.

When the data update is not interrupted and the data update is completed normally, upon receiving a data read request, data length information is obtained from the packet management unit 80 via steps S200 and S202. , Based on the acquired data length information,
The storage position of the packet having the ID information matching the D information is specified. At this time, since the packet before update is stored at the start address side of the packet unit 72 than the new packet, the storage position of the packet before update is specified first. Since the state information is in the fourth state, steps S204 and S204
After 208, it is determined that the packet is invalid, and the data is not read.

Next, the storage location of the next packet having ID information that matches the ID information given from another process is specified. At this time, the storage position of the new packet is specified. Since the state information of the new packet is in the second state, steps S204 and S20 are performed.
After 6, the packet is determined to be a valid packet, and data is read from the data section 82 of the packet.

In the above description, the case where data is updated for the block A has been described. However, the case where data is updated for the block B operates in the same manner as described above.

Next, a case where the blocks A and B are updated will be described with reference to FIG. FIG. 14 is a diagram for explaining a case where block A is updated to block B.

When data writing / updating to block A is continued with block A as a data writing area,
As shown in FIG. 14, the packet unit 72 of the block A
Valid packets and invalid packets are mixed. In the example of FIG. 14, between a valid packet having an ID of “01” and a valid packet having an ID of “03”, there are two packets that have become invalid due to data update. If a large number of invalid packets exist in the packet section 72 of the block A, new writing / updating of data cannot be performed.

Therefore, when a new data write request or a data update request is received from another process for updating data in the flash ROM 52, a packet for storing data to be stored / updated is generated. If there is not enough space in the packet section 72 of the block A, a block update request is output in step S128. Upon receiving the block update request, the update from block A to block B is started. Block B
Has already been initialized, that is, the area state information 1 (initialization completed) has been written in the area management unit 70 of the block B.

Updating of a block from block A to block B is performed as follows. Through steps S300 to S304, the CPU 50 refers to the processing definition table to execute processing for blocks A and B, and determines whether block A is valid. At this time, since the block A is valid, the area state information 4 (data is being moved) is written to the area management unit 70 of the block A in step S306.

Next, when the area state information 4 is written in the area management section 70 of the block A and the area state information 1 is written in the area management section 70 of the block B, steps S300 and S40 are performed.
0, S402, and S424 to S430, the process definition table is referred to, the area status information 2 (data is being written) is written in the area management unit 70 of the block B, and as shown in FIG. Valid packet data is
The data is written in the packet section 72 of the block B so that the storage positions are arranged in order, the area state information 3 (data writing completed) is written in the area management section 70 of the block B, and the area management section 70 of the block A is written. Is written in the area status information 5 (data transfer completed). When the update of the block is completed in this way, the block A becomes a data update area, and instead of the block A, the block B becomes a data write area.

When the area state information 5 is written in the area management section 70 of the block A and the area state information 3 is written in the area management section 70 of the block B, steps S300 and S40 are performed.
0, through steps S402 to S408, the processing definition table is referred to, the block A is initialized, the number of initializations of the block A is incremented by "1", and the area management unit 70 of the block A is added.
The initialization count information is written in the area management unit 70, and the area state information 1 is written in the area management unit 70 of the block A.

In a normal state where the updating of the block is not interrupted, the data of the valid packet of the block A is written in the packet section 72 of the block B in this way. For example, the updating of the block is interrupted for some reason. In this case, the following operation is performed.

First, if the update of data is interrupted while data is being written to block B, when the system is restarted, the area status information 4 of the area management unit 70 of block A is updated to the Since the area state information 2 has been written in the area management unit 70, steps S300 and S300
400, S402, S410 to S414, the processing definition table is referred to, the block B is initialized, the number of initializations of the block B is added by “1”, and the number of initializations is added to the area management unit 70 of the block B. The information is written, and the area state information 1 is written to the area management unit 70 of the block B.

When the area state information 4 is written in the area management section 70 of the block A and the area state information 1 is written in the area management section 70 of the block B, steps S300 and S40 are performed.
0, S402, and S424 to S430, the process definition table is referred to, the area status information 2 is written in the area management unit 70 of the block B, and as shown in FIG. Is rewritten into the packet section 72 of the block B so that the storage positions are rearranged, the area state information 3 is written in the area management section 70 of the block B, and the area management section 70 of the block A is written.
Area state information 5 is written to Thereafter, the block A is initialized, and the area state information 1 is written to the area management unit 70 of the block A.

Next, if the update of the data is interrupted while the block A is being initialized, the system is restarted and the area status information 5 of the block A is stored in the area management unit 70 of the block A. Since the area state information 3 has been written in the area management unit 70, steps S300, S400,
After S402 to S408, the processing definition table is referred to, the block A is re-initialized, the number of initializations of the block A is incremented by “1”, and the area management unit 70 of the block A is added.
The initialization count information is written in the area management unit 70, and the area state information 1 is written in the area management unit 70 of the block A.

In the above description, the case where the update from the block A to the block B is performed has been described. However, the operation when the update from the block B to the block A is performed in the same manner as described above.

As described above, in the present embodiment, when storing data, a packet for storing the data to be stored is generated in the packet section 72 of the block, and the state information of the packet is written at the start of data writing. Is set to the first state, data to be stored is written in the data portion 82 of the packet, and when the data writing is completed, the state information of the packet is set to the second state. Is determined to be a valid packet, and a packet whose status information is in the first state is determined to be an invalid packet.

As a result, the packet is not identified as a valid packet until the data writing is completed. Therefore, even if the data writing is interrupted for some reason until the data writing is completed, the data writing is not performed. The data of the packet being loaded is not treated as correct data. In addition, since the erasure of data on the flash ROM 52 may be performed by setting the state information of the packet storing the data to be erased to the first state, the number of times of initialization of the flash ROM 52 is reduced. . Therefore, as compared with the related art, the life of the flash ROM 52 can be prevented from being shortened, data can be rewritten at high speed, and data can be written with high reliability.

Further, in the present embodiment, when updating the data of a packet, a new packet for storing the data to be updated is generated in the packet section 72 of the block, and the state of the packet at the start of data writing is changed. The information is set to the third state and the state information of the new packet is set to the first state.
, The data to be updated is written to the data portion 82 of the new packet, and when the data writing is completed, the status information of the new packet is set to the second status and the status information of the packet is set to the fourth status. And the status information is
Or the third state packet is determined to be a valid packet, and the packet whose state information is the first state or the fourth state is determined to be an invalid packet.

As a result, a new packet is not identified as a valid packet until the data update is completed. Therefore, even if the data update is interrupted for some reason until the data update is completed, Data of a new packet during data writing is not handled as correct data. In this case, the data of the packet before the update is handled as correct data. Therefore, data can be updated with higher reliability than before.

Further, in the present embodiment, the storage position of the packet is specified based on the data length information.

As a result, data of an arbitrary data length not exceeding the storage capacity of the packet section 72 can be stored as one packet in the packet section 72 of the block without division, so that variable-length data can be managed. It will be easier.

Furthermore, in this embodiment, when updating a block, the area status information 4 is written into the area management unit 70 of one of the blocks A and B at the start of data writing, and the area of the other block is written. The area status information 2 is written to the management unit 70, the valid packet data of the packet unit 72 of one block is written to the packet unit 72 of the other block, and the data is written to the area management unit 70 of one block when the data writing is completed. The state information 5 is written and the area state information 3 is stored in the area management unit 70 of the other block.
Is written, and the block in which the area status information 3, 4 is written in the area management unit 70 is determined to be a valid block. It is now determined that the block is invalid.

As a result, the block to be updated is not identified as a valid block until the update of the block is completed. Therefore, the update of the block is interrupted for some reason until the update of the block is completed. Even if the data is written, the data of the other block in the middle of data writing is not treated as correct data. in this case,
The data of one block before the update is handled as correct data. Therefore, data can be updated with higher reliability.

Further, in the present embodiment, the area management unit 7
The block in which the area status information 1, 2, 5 is written to 0 is used as a data update area.

Thus, a new block does not become a data update area each time a block is updated, so that the storage area of the flash ROM 52 can be effectively used.

Further, in the present embodiment, blocks A,
The processing for the blocks A and B is executed by referring to the processing definition table to which the processing for the blocks A and B is assigned according to the state of the area state information of B.

As a result, it is not necessary to determine the processing for the blocks A and B sequentially according to the state of the area state information of the blocks A and B, so that the processing relating to data rewriting can be simplified.

Further, in the present embodiment, the blocks are:
It consists of a data initialization unit of the flash ROM 52.

Thus, the number of times of initialization of the flash ROM 52 can be minimized.

Further, in this embodiment, the area management information 4 is written in the area management section 70 of one block, and the area management information 2 is written in the area management section 70 of the other block.
When is written, the other block is initialized.

Thus, if data is interrupted while data is being written to the packet section 72 of the other block for some reason, when the system is restarted, the other block is initialized and the packet of the other block is initialized. Part 7
2, the data is rewritten, so that the data can be updated with higher reliability.

Further, in this embodiment, the area management information 5 is written in the area management unit 70 of one block, and the area management information 1, 2, 3 is written in the area management unit 70 of the other block. , One of the blocks is initialized.

Thus, if the update of data is interrupted during the initialization of one block for some reason, when the system is restarted, one block is re-initialized. Can be performed with higher reliability.

In the above embodiment, blocks A and B
Corresponds to the storage area according to claims 1, 2, 4 to 7, the area state information 2 corresponds to the first state according to claim 4 or 5, and the area state information 3 corresponds to claim 4. Second
The area state information 4 corresponds to the third state described in claim 4, and the area state information 5 corresponds to the fourth state described in claim 4 or 5.

In the above embodiment, the block is constituted by the data initialization unit of the flash ROM 52. However, the present invention is not limited to this, and the block may be constituted by combining two or more data initialization units. Even with such a configuration, the number of times of initialization of the flash ROM 52 can be minimized.

Further, in the above embodiment, the case where the data update is interrupted during the transition from step S116 to step S118 has not been particularly described. , 3
When a packet having the status information of the second state and a packet having the status information of the first state coexist, the packet having the status information of the second or third state may be determined to be a valid packet. .

Further, in the above embodiment, the case where the data update is interrupted during the transition from step S124 to step S126 has not been particularly described. When a packet having the status information of the second state and a packet having the status information of the second state coexist, the packet having the status information of the second state may be determined to be a valid packet.

Further, in the above embodiment, the case where the update of the block is interrupted during the transition from step S306 to step S424 or the transition from step S308 to step S416 is not particularly described. To cope with the case, the area management unit 7
When a block in which the area state information 4 is written in the area management unit 0 and a block in which the area state information 1 is written in the area management unit 70 coexist, the block in which the area state information 4 is written in the area management unit 70 is determined. You may comprise so that it may be determined that it is a valid block.

Further, in the above embodiment, the case where the update of the block is interrupted during the transition from step S428 to step S430 or the transition from step S420 to step S422 is not particularly described. To cope with the case, the area management unit 7
When the block in which the area state information 3 is written in the area 0 and the block in which the area state information 4 is written in the area management unit 70 coexist, the block in which the area state information 3 is written in the area management unit 70 is set. You may comprise so that it may be determined that it is a valid block.

In the above-described embodiment, the block is used by using one block as the data writing area and one block as the data updating area.
However, the present invention is not limited to this.
Alternatively, a plurality of blocks as a data write area may be used. In this case, the condition is that a plurality of blocks are not updated at the same time. When a plurality of blocks are updated at the same time, blocks as data update areas may be prepared in a number equal to the number at which the storage area is updated at the same time.

Further, in the above-described embodiment, when executing the operation processing shown in the flow charts of FIGS. 9 to 13, the case where a program stored in advance in the flash ROM 52 is executed has been described, but the present invention is not limited to this. The program is stored in a RAM 54 from a recording medium on which the program showing these procedures is recorded.
May be read and executed.

Here, the storage medium includes semiconductor storage media such as RAM and ROM, magnetic storage media such as FD and HD, optical reading storage media such as CD, CDV, LD, DVD, and MO. It is a magnetic storage type / optical read type storage medium, and includes any storage medium that can be read by a computer regardless of an electronic, magnetic, optical or other read method.

Further, in the above embodiment, the data management device for a flash memory according to the present invention is divided into a block of the flash ROM 52 which is composed of data initialization units.
Although the present invention has been applied to the case where data necessary for setting the computer 100 is stored in units of variable-length packets, the present invention is not limited to this, and can be applied to other cases without departing from the gist of the present invention.

[0156]

As described above, according to the flash memory data management device according to the first to seventh aspects of the present invention, a data is not identified as a valid packet until data writing is completed. Even if the data writing is interrupted for some reason until the data writing is completed, the data of the packet being written is not handled as correct data. In addition, since the erasing of data in the flash memory may be performed by setting the state information of the packet storing the data to be erased to the first state, the number of times of initialization of the flash memory is reduced. . Therefore, as compared with the related art, it is possible to prevent the life of the flash memory from being shortened, to perform data rewriting at a high speed, and to perform data writing with high reliability.

Further, according to the flash memory data management device of the second aspect of the present invention, a new packet is not identified as a valid packet until the data update is completed. Even if the data update is interrupted for some reason until the completion, the data of the new packet being written is not treated as correct data. Therefore, an effect that data can be updated with higher reliability than before can be obtained.

Further, according to the flash memory data management device of the third aspect of the present invention, data of an arbitrary data length not exceeding the storage capacity of the storage area is divided into one packet in the storage area without being divided. Since the data can be stored, an effect that management of variable-length data is facilitated is also obtained.

Further, according to the flash memory data management device of the present invention, another storage area to be updated is identified as a valid storage area until the update of the storage area is completed. Therefore, even if the update of the storage area is interrupted for some reason until the update of the storage area is completed, the data of another storage area which is the update destination in the middle of data writing may not be treated as correct data. Absent. Therefore, an effect is obtained that data can be updated with higher reliability.

Further, according to the flash memory data management device of the present invention, a new storage area does not become another storage area every time a storage area is updated. The effect that the storage area can be used effectively can also be obtained.

Further, according to the data management device for a flash memory according to the sixth aspect of the present invention, the flash memory data is updated before the update in accordance with the state of the area status information of the storage area before the update and another storage area to be updated. This eliminates the need to sequentially determine the processing for the storage area and another storage area to be updated, so that the effect of simplifying the processing related to data rewriting can also be obtained.

Further, according to the flash memory data management device of the present invention, an effect is obtained that the number of times of initialization of the flash memory can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer 100.

FIG. 2 is a diagram showing a data structure of blocks A and B.

FIG. 3 is a diagram showing a data structure of an area management unit 70.

FIG. 4 is a diagram showing contents of area state information.

FIG. 5 is a diagram showing a data structure of a packet unit 72.

FIG. 6 is a diagram showing a data structure of a management unit 80.

FIG. 7 is a diagram showing the contents of state information.

FIG. 8 is a diagram showing a data structure of a process definition table.

FIG. 9 is a flowchart showing a data writing process.

FIG. 10 is a flowchart showing a data reading process.

FIG. 11 is a flowchart illustrating a block update process.

FIG. 12 is a flowchart illustrating a process based on a process definition table in step S300.

FIG. 13 is a flowchart showing processing based on the processing definition table in step S300.

FIG. 14 is a diagram for describing a case where data is updated for a block B.

[Explanation of symbols]

100 Computer 50 CPU 52 ROM 54 RAM 55 VRAM 56 graphic chip 57 RTC 58 I / F 59 bus 60 touch panel 70 area management unit 72 the packet 80 management unit 82 data portion P ₁ to P _n packets

Claims (7)

[Claims] 1. An apparatus for storing data in a storage area of a flash memory in packet units, wherein the packet stores a management unit for storing management data relating to management of the packet, and data to be stored. In the management unit, status information indicating two different statuses of the packet can be stored as the management data. When data is stored, data to be stored is stored in the management unit. A packet to be stored is generated in the storage area, and at the start of data writing, the state information of the packet is set to a first state indicating that new writing of data is being performed. Writing the data to be stored, and setting the status information of the packet to a second status indicating that the new writing of the data is completed when the data writing is completed; The state information determines that the packet in the second state is a valid packet, and the state information determines that the packet in the first state is an invalid packet. Flash memory data management device. 2. The packet according to claim 1, wherein the status information indicates two further different statuses of the packet. When updating the data of the packet, the status information stores the data to be updated. A new packet is generated in the storage area, and at the start of data writing, the state information of the packet is set to a third state indicating that data is being updated and the state information of the new packet is set to the first state. Set to
The data to be updated is written in the data portion of the new packet, and when the data writing is completed, the state information of the new packet is set to the second state and the update of the state information of the packet is completed. The state information is determined to be a valid packet if the state information is the second state or the third state, and the state information is determined to be the first state or the fourth state. A data management device for a flash memory, wherein a packet in the state of (1) is determined to be an invalid packet. 3. The packet according to claim 1, wherein the packet has a variable length, and the management unit can store data length information indicating a data length of the packet as the management data. A data management device for a flash memory, wherein a storage location of the packet is specified based on the data length information. 4. The flash memory data management device according to claim 1, wherein data is stored in the storage area in packet units, and the storage is performed using another storage area different from the storage area. An apparatus for updating an area, wherein the storage area includes an area management unit for storing area management data related to management of the storage area, and a packet unit for storing a packet. Can store, as the area management data, area state information indicating four different states of the storage area. When updating the storage area, the area state information of the storage area at the start of data writing Is set to a third state indicating that data is being updated, and the area state information of the another storage area is set to a first state indicating that new data is being written. A valid packet data of the storage area is written into the packet portion of the another storage area, and when the data writing is completed, the area state information of the another storage area is a second data indicating that the new writing of the data is completed. In the state, the area state information of the storage area is set to a fourth state indicating that the data update is completed, and the storage area whose area state information is the second state or the third state is valid. A flash memory, wherein the storage area is determined to be an invalid storage area, and the storage area in which the area state information is in the first state or the fourth state is determined to be an invalid storage area. Memory data management device. 5. The flash memory according to claim 4, wherein a storage area whose area state information is in the first state or the fourth state is used as the another storage area. Data management device. 6. The storage area according to claim 4, wherein processing for the storage area or another storage area is assigned according to the state of the area state information of the storage area and the state of the area state information of the another storage area. A flash memory data management device configured to execute processing on the storage area or the another storage area with reference to the processing definition table. 7. The flash memory data management device according to claim 1, wherein the storage area includes a flash memory data initialization unit.