JP2002229847A - Data management device of flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data management device of a flash memory suitable for speed-up of access to a packet. SOLUTION: When updating data in the packet, state information of the packet is set in the third state and the state information of a packet to be renewed is set in the first state at the start time of data writing, and renewed data are written in a data part 82 of the packet to be renewed, and the state information of the packet to be renewed is set in the second state and the state information of the packet of a renewal source is set in the fourth state at the completion time of the data writing. The packet having the state information in the second or third state is determined as an effective one, and the packet having the state information in the first or fourth state is determined as an ineffective one. Tables 400, 420 wherein access information for accessing the effective packet is registered are generated at the start time, and access to the packet is executed by referring to the generated tables 400, 420.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for storing data in a storage area of a flash memory in packet units, and more particularly to a data management apparatus for a flash memory suitable for speeding up access to a packet.

[0002]

2. Description of the Related Art Conventionally, as an apparatus for storing data in a storage area of a flash memory in packet units, for example,
There is a method of using a flash memory disclosed in Japanese Patent Application Laid-Open No. Hei 5-233426. In this method, a flash memory is divided into a plurality of sectors, a logical address portion, an erase management display portion, and a data portion are provided in each sector, and a sector is searched by a logical address. Then, when updating, the erasure enable flag in the erasure management display portion of the sector is turned on, the logical address is added to the empty sector, and the update data is written.

[0003] As a result, data is erased from the flash memory by setting an invalid flag indicating that the data is invalid in the erase manager of the sector storing the data to be erased. In addition, the number of times of initialization of the flash memory is reduced, and the life of the flash memory is prevented from being shortened, and data can be rewritten at high speed.

[0004]

However, in the above conventional method of using a flash memory, when updating data in a sector, the updated data is written into a new sector, and the sector before the update is erased. In order to set an invalid flag in the management unit, for example, if a power failure, system hang-up, or erroneous turning on of the reset switch occurs during data update, the erase management unit of the sector before update and the new sector Updating of the data is interrupted with the valid flag indicating that the data is valid, and it is difficult to identify which is the correct data.

In order to deal with such a problem, a block to which a sector before update belongs is first initialized, and then,
It is necessary to write the updated data to a new sector, and as a result, the number of times of initialization of the flash memory cannot be reduced. In this case, of the initialized blocks other than the sector before the update,
It is necessary to rewrite to the original state.

Therefore, to reduce the number of times of initialization of the flash memory to prevent the life of the flash memory from being shortened, to rewrite data at high speed, and to update data with high reliability, for example, The following configuration is conceivable. This is a device that stores data in packet units in a storage area of a flash memory, and a packet includes a management unit for storing management data related to management of the packet and a data unit for storing data. The management unit can store state information indicating four different states of the packet as management data. Then, when updating the data of the packet,
An update source packet storing an update destination packet for storing data after update in a storage area, and at the time of starting data writing, updating the status information of the update destination packet to the first state and storing the data before update State information of the third state,
Writing the updated data in the data portion of the update destination packet; setting the status information of the update destination packet to the second status and the status information of the update source packet to the fourth status when the data writing is completed; Determines that a packet in the second state or the third state is a valid packet, and determines that a packet whose state information is the first state or the fourth state is an invalid packet. ing.

With such a configuration, when updating data of a packet, first, the state information of the packet is stored in the first state.
, And the packet management unit of the update destination in which information such as the packet length is set is written in the position next to the last packet, and the state information of the update source packet is set to the third state. Then, the updated data is written to the data portion of the update destination packet. When the data writing is completed, the status information of the update destination packet is set to the second state, and the status information of the update source packet is set to the fourth state. Is set.

For example, if the data update is interrupted for some reason, the status information is changed to the second status or the third status.
Is determined to be a valid packet, and a packet whose status information is the first state or the fourth state is determined to be an invalid packet. However, even with such a configuration, for example, after the state information of the update destination packet is set to the second state and before the state information of the update source packet is set to the fourth state, for example, for some reason, When the data update is interrupted, the state information of the update destination packet is in the second state, but the state information of the update source packet is still in the third state. It will be judged.

In this case, since the writing of the updated data has been completed, the update destination packet must be determined to be a valid packet, and the update source packet must be determined to be an invalid packet. More specifically, every time a packet is accessed, the entire area of the storage area where the packet is stored is scanned, all the state information is acquired for the packet having the same ID, and the state information is stored in the second area. When the state packet and the state information of the third state coexist, it is necessary to determine that the state information of the second state packet is a valid packet.

[0010] Therefore, every time the packet is accessed, the entire area of the storage area where the packet is stored is scanned, so that a problem that access to the packet takes time is expected. This is the same even when the state information of the update source packet is rewritten before that of the update destination packet. That is, after the state information of the update source packet is set to the fourth state and before the state information of the update destination packet is set to the second state,
For example, if the data update is interrupted for some reason, the status information of the update source packet will be in the fourth state, but the status information of the update destination packet will be in the first state. It is determined to be a packet.

In this case, since the writing of the updated data has been completed, the update destination packet must be determined to be a valid packet, and the update source packet must be determined to be an invalid packet. Therefore, a packet whose status information is in the first state is normally in the middle of data writing and is not a valid packet, but a packet whose status information is in the first state and a packet whose status information is in the fourth state coexist. If so, it is necessary to exceptionally determine that the packet whose status information is in the first state is a valid packet.

SUMMARY OF THE INVENTION The present invention has been made in view of such unresolved problems of the prior art, and is a data management apparatus for a flash memory suitable for speeding up access to a packet. It is intended to provide.

[0013]

According to a first aspect of the present invention, there is provided a data management apparatus for a flash memory which stores data in a storage area of the flash memory in packet units. The packet includes a management unit for storing management data relating to the management of the packet, and a data unit for storing data, and the management unit includes, as the management data,
State information indicating the state of the packet is storable, and when updating the data of the packet, an update destination packet for storing the updated data is generated in the storage area, and data writing is started. At the time, the status information of the update destination packet is set to the first status, and the status information of the update source packet storing the data before update is set to the third status, and the data portion of the update destination packet is set to the update status. After writing the data, when the data writing is completed, the status information of the update destination packet is set to the second status and the status information of the update source packet is set to the fourth status, and the status information is set to the second status. A packet in a state or the third state is determined to be a valid packet, and a packet in the state information in the first state or the fourth state is determined to be an invalid packet. In location, by referring to the access information management table registered access information for accessing the valid packet among the packets stored in said storage area, and performs the access to the packet.

With such a configuration, the access to the packet is performed with reference to the access information management table. Since access information for valid packets is registered in the access information management table, it is not necessary to determine whether a packet is valid or invalid each time a packet is accessed. When updating the packet data, first, the packet status information is set to the first state, and information such as the packet length is set. And the status information of the update source packet is set to the third status. Then, the updated data is written to the data portion of the update destination packet, and when the data writing is completed, the status information of the update destination packet is set to the second status and the status information of the update source packet is set to the fourth status. You.

For example, if the update of data is interrupted for some reason, the status information indicates the second status or the third status.
Is determined to be a valid packet, and a packet whose status information is the first state or the fourth state is determined to be an invalid packet. Therefore, the update destination packet is not identified as a valid packet until the data update is completed.

Here, the present apparatus may refer to an access information management table generated in advance, or generate an access information management table and refer to the generated access information management table. May be. In the latter case, the access information management table may be generated at any time. Further, the state information as the second state and the state information as the third state may indicate different states, respectively, or may indicate the same state. The same applies to the relationship between the state information in the first state and the state information in the fourth state.

The packet may have any data length, may have a fixed length, or may have a variable length. The order in which the state information of the update destination packet is set to the second state and the state information of the update source packet is set to the fourth state may be any order, but the state information of the update destination packet is set to the second state. It is more preferable to set the state information of the update source packet to the fourth state after setting the state to the fourth state. This is after changing the status information of the update destination packet and before changing the status information of the update source packet,
This is because, even if the data update is interrupted for some reason, the update destination packet is determined to be a valid packet.

The order in which the state information of the update destination packet is set to the first state and the state information of the update source packet is set to the third state may be any order. Further, a flash memory data management device according to a second aspect of the present invention is the flash memory data management device according to the first aspect, wherein the access information management table is generated at the time of startup.

With such a configuration, when activated, an access information management table is generated. After activation, access to the packet is performed with reference to the generated access information management table. Further, claim 3 according to the present invention.
The data management device for a flash memory according to claim 1,
3. The data management device for a flash memory according to claim 1, wherein the access information includes packet identification information for identifying the packet, and an address for specifying a storage position of the packet. ing.

With this configuration, when the packet identification information is provided, the access information management table is searched based on the provided packet identification information, and the access information corresponding to the packet identification information is found. . Then, access to the packet is performed based on the address included in the retrieved access information. According to a fourth aspect of the present invention, in the data management device for a flash memory according to the third aspect, the access information further includes the valid packet. .

With such a configuration, for example, data reading from a packet is performed from the access information management table. A flash memory data management device according to a fifth aspect of the present invention is the flash memory data management device according to any one of the first to fourth aspects, wherein the access information management table is used to hold data. Is stored in a storage medium that requires

With such a configuration, the access information management table is stored in a storage medium that requires power to hold data.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 18 are diagrams showing an embodiment of a data management device for a flash memory according to the present invention. In the present embodiment, as shown in FIG. 1, the data management device for a flash memory according to the present invention stores data necessary for setting of the computer 100 in a block composed of data initialization units of a flash ROM 52 as a flash memory. For example, an IP address, a URL of a WWW (World Wide Web) server to be accessed (Univer
sal Resource Locater)) is applied to the case of storing in variable-length packet units.

First, the configuration of the computer 100 will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of the computer 100. Computer 100
As shown in FIG. 1, a CPU 50 for controlling the arithmetic and the entire system based on a control program, a flash ROM 52 in which a control program for the CPU 50 is stored in a predetermined area in advance, data read from the flash ROM 52 and the like, A RAM 54 for storing a calculation result required in a calculation process, a graphic chip 56 for converting data stored in a VRAM 55 into an image signal and outputting the image signal, and an I / O for mediating data input / output to / from an external device. F58, which are connected to each other and capable of exchanging data via a bus 59, which is a signal line for transferring data.

The I / F 58 is an external device such as an LCD (Liquid Cry) which can input data as a human interface and displays a screen based on image signals.
The touch panel 60 is connected to the touch panel 60 and a speaker (not shown) for outputting sound, a signal line for connecting to the Internet, and the like.

The graphic chip 56 includes a VRAM 55
Are sequentially read from the head address at a predetermined cycle, and the read display data is converted into an image signal and output to the touch panel 60. Next, the configuration of the flash ROM 52 will be described in detail with reference to FIGS. FIG. 2 is a diagram showing the data structure of blocks A and B.

The flash ROM 52 is composed of a data rewritable nonvolatile storage element. As shown in FIG. 2, the storage area is logically divided into a plurality of blocks each composed of a data initialization unit. The two blocks A and B are used as a data write area for writing data and a data update area used when updating a block. In the flash ROM 52, for example, the data bits in the storage area are “1” in an initialized state (a state in which data is initialized and data is not written).

Each of the blocks A and B comprises an area management section 70 for storing area management data relating to block management and a packet section 72 for storing packets. When it is a data update area, the other is a data update area, and when the other is a data write area, one is a data update area. Data writing is performed on a block that is to be a data writing area. On the other hand, the update of the block is performed by the packet unit 7 of the block serving as the data write area.
2 is performed when an area for writing data is insufficient, and data of valid packets in the packet section 72 of a block serving as a data writing area are arranged in order such that their arrangement positions are ordered. This is performed by writing to the packet section 72 of the block that becomes the data update area. And
When the data writing to the packet unit 72 is completed, the block serving as the data update area is set as the data write area, and the block serving as the data write area is set as the data update area.

As shown in FIG. 3, the area management section 70 stores an area 70a for storing initialization number information indicating the number of initializations of a block, and area state information 1 to 5 indicating five different states of the block. Area 70b to 70f, and each area 70a to 70f
It has a storage capacity of two data read units (for example, 4 bytes (32 bits)). FIG. 3 shows the area management unit 7.
It is a figure showing the data structure of 0.

Each of the area status information 1 to 5 is configured as shown in FIG. FIG. 4 is a diagram showing the contents of the area state information. The area state information 1 is information indicating that the block has been initialized (initialization completed state), as shown in the first row of FIG.
It is written to the area 70b as byte write information. The area state information 2 is information indicating that data is being written to the block (data writing state), and is referred to as “STUP”, as shown in the second item in the upper part of FIG. 4
The data is written to the area 70c as byte write information. As shown in the upper third column of FIG. 4, the area state information 3 indicates that data writing to the block has been completed and that data can be additionally written to the packet portion 72 of the block (data writing). Information indicating the status of “NOR”
M ”is written to the area 70d as 4-byte write information.

The area state information 4 is information indicating that data is being moved from the block (data is being moved) in order to update the data of the block, as shown in the fourth column in FIG. Then, it is written into the area 70e as 4-byte write information "MOVE". The area state information 5 is information indicating that data movement from a block has been completed (data movement completed state), as shown in the fifth item in the upper part of FIG. Is written in the area 70f.

The area state information 1 to 5 are written in the respective areas 70b to 70f in that order. Therefore, for example, the area state information 3 is not written when the area state information 1 and 2 are not written, and is not written even when the area state information 4 and 5 are written. A state in which none of the area state information 1 to 5 has been written or a state in which the area state information 1 to 5 has not been written in that order means that the block has never been initialized (uninitialized). State)
handle.

The packet section 72 includes a flash ROM 52
5 has a storage area of a predetermined capacity which is a multiple of a data read unit (for example, 4 bytes), and as shown in FIG. 5, a plurality of packets P _{1 to} P _n of variable length can be stored. Each of the packets P _{1 to} P _n includes a management unit 80 for storing management data related to packet management, and a data unit 82 for storing data. The packets P _{1 to} P _n are sequentially arranged from the top address to the end address of the packet unit 72. Generated.
FIG. 5 is a diagram illustrating a data structure of the packet unit 72.

As shown in FIG. 6, the management unit 80 stores an area 8 for storing state information indicating five different states of the packet.
0a, an area 80b for storing ID information indicating an ID for identifying a packet, and an area 80c for storing serial number information indicating a serial number assigned in the order in which the packets were generated.
And an area 80d for storing data length information indicating the data length of the data section 82. Each of the areas 80a to 80d includes:
The management unit 80 as a whole has a storage capacity of a data read unit (for example, 4 bytes (32 bits)) of the flash ROM 52. FIG. 6 is a diagram illustrating a data structure of the management unit 80.

The state information is different from the area state information.
This shows five different states of the packet by one data stored in the area 80a, and is configured as shown in FIG. FIG. 7 is a diagram showing the contents of the state information. The status information indicates, as the first status, that data is being written to the packet (data writing status). In this case, the status information is written in the area 80a as 1-byte write information “7FH”. The second state indicates that data writing to the packet has been completed (data write completed state). In this case, the most significant bit of “1” in the write information indicating the first state is “2”. It is written to the area 80a as 1-byte write information of "3FH" set to "0". The third state indicates that the data of the packet is being updated (data updating state). In this case, the most significant bit of “1” of the write information indicating the second state is set to “0”. The data is written to the area 80a as the set 1-byte write information “1FH”.

The state information indicates, as the fourth state, that the data update of the packet has been completed (data update completed state). In this case, the most significant bit of “1” of the write information indicating the third state Is set to “0”, and is written to the area 80a as 1-byte write information “0FH”. Also, the fifth state indicates that the packet is unused (unused state), and in this case, “1” called “FFH”
It is written to the area 80a as byte write information (that is, in the initialized state).

The state information is stored in the area 8 in the order of the fifth state, the first state, the second state, the third state, and the fourth state.
0a. So, for example,
When the state information is the third state, the state does not change to the first state or the second state unless the block to which the packet belongs is initialized. Also, flash ROM
As shown in FIG. 8, the processing definition table 52 stores the processing definition to which the processing for the blocks A and B is assigned according to the state of the area state information of the blocks A and B. FIG.
It is a figure showing the data structure of a process definition table.

The processing definition table is configured as shown in FIG. 8, and the processing contents indicated by each element of the processing definition table specified by each state of the blocks A and B are as follows. . If the state of the block A is in data movement and the state of the block B is not initialized or data is being written, the block B is initialized. When the state of the block A is moving data and the state of the block B is initialization completed, the data of the valid packet of the block A is written into the packet section 72 of the block B, so that the block A is changed to the block B. Update. When the state of the block A is writing data and the state of the block B is uninitialized or the initialization is completed, the state of the block A is data moving and the state of the block B is data writing completed. At this time, or when the state of the block A is data movement completed and the state of the block B is uninitialized, initialization completed, data writing or data writing completed, the block A is initialized. When the state of the block A is data writing completed and the state of the block B is uninitialized, initialization completed, or data writing is being performed, the block A is used as a data writing area.

If the state of the block B is data movement and the state of the block A is not initialized or data is being written, the block A is initialized. Block B
Is in a data movement state and the state of the block A is initialization completed, the block B is updated to the block A by writing the data of the valid packet of the block B into the packet section 72 of the block A. . Block B
Is in data writing and the state of block A is uninitialized or initialization completed, when the state of block B is data movement and the state of block A is data writing completed, Alternatively, when the state of the block B is data transfer completed and the state of the block A is uninitialized, initialization completed, during data writing, or data writing completed, the block B is initialized. The state of block B is data write completed and the state of block A is uninitialized,
When initialization is completed or data writing is being performed, block B is used as a data writing area.

When the state of the block A is uninitialized or the initialization is completed, and the state of the block B is uninitialized or the initialization is completed, the initialization processing for the blocks A and B is performed. On the other hand, returning to FIG.
A predetermined program stored in a predetermined area of the flash ROM 52 is started by the micro processing unit MPU or the like, and the program shown in FIG.
12 is executed at the time of startup, and the packet access process and the block update process shown in the flowcharts of FIGS. 12 and 15 are respectively executed in a time-division manner.

First, the table generation processing will be described in detail with reference to FIG. FIG. 9 is a flowchart showing the table generation processing. The table generation process is a process of generating, on the RAM 54, a packet address management table 400 and an ID index conversion table 420 in which access information for accessing a valid packet among the packets stored in the packet unit 72 is registered. When executed by the CPU 50, the process first proceeds to step S10, as shown in FIG.

In step S10, a packet address management table 400 is generated on the RAM 54. The packet address management table 400 has a configuration as shown in FIG. FIG. 10 shows a data structure of the packet address management table 400. As shown in FIG. 10, one record is registered in the packet address management table 400 for each valid packet. Each record has a field 402 for registering a reference index for referring to the record, and a field 4 for registering an address on the flash ROM 52 of a valid packet.
04, a field 405 for registering the data length of the data portion 82 of the valid packet, and a field 406 for registering the contents of the data portion 82 of the valid packet. In the example of FIG. 10, some records are registered in the packet address management table 400. This indicates the result of the record registration after repeating steps S18 and S20. Then, an empty table in which no record is registered is generated.

Next, the process proceeds to step S16, where it is determined whether the packet is valid. If it is determined that the packet is valid (Yes), the process proceeds to step S18. Specifically, in step S16, the validity
Invalidity is determined as follows. If the packet status information is
When the state is the third state or the third state, it is determined that the packet is valid. When the state information of the packet is the first state or the fourth state, it is determined that the packet is invalid. In addition, when packets having the same ID information and packets having status information in the second state coexist with packets having status information in the third state, the packet having the status information in the second state coexists. Is determined to be a valid packet.

In step S18, data is read from the data portion 82 of the packet, and the flow advances to step S20 to generate a reference index, the generated reference index, the address of the packet on the flash ROM 52,
The data length and data contents of the data portion 82 of the packet are registered in the packet address management table 400, and the process proceeds to step S12.

In step S12, the packet management unit 8
Data length information is acquired from 0, and the process proceeds to step S14, where the storage location of the next packet is specified based on the acquired data length information, and the process proceeds to step S22. In step S22, it is determined whether or not the packet is the last one counted from the first address of the packet part 72. If it is determined that the packet is the last one (Yes), the process proceeds to step S24. If not (No)
Moves to step S12. The determination of whether or not the packet is the last one is specifically performed as follows. The status information of the management unit 80 is read, and when the read status information is the fifth status, it is determined that the immediately preceding packet is the last packet. The last address of the last packet is saved for use when writing a new packet.

In step S24, an ID index conversion table 420 for registering the ID information in association with the reference index is generated in the RAM 54, and a series of processing is completed to return to the original processing. The ID index conversion table 420 has a configuration as shown in FIG. FIG. 11 shows a data structure of the ID index conversion table.

As shown in FIG. 11, one record is registered in the ID index conversion table 420 for each piece of ID information. Each record includes a field 422 for registering ID information and a packet address management table 4
And a field 424 for registering a reference index of 00. In the example of FIG. 11, all ID information that is assumed to be used is registered in the ID index conversion table 420, and if the packet specified by the ID information exists as a valid packet, The corresponding reference index of the address management table 400 is registered, and when the packet specified by the ID information does not exist as a valid packet, for example, “−1” is used as a code indicating that it does not exist.
Register

On the other hand, if it is determined in step S16 that the packet is invalid (No), the process proceeds to step S12. Next, the packet access processing will be described in detail with reference to FIG. FIG. 12 is a flowchart showing the packet access processing. Packet access processing
A data read request from another process for reading or writing data to the flash ROM 52 (other than the processes shown in the flowcharts of FIGS. 9 and 12 to 17; hereinafter, referred to as a request source process) or This is a process of accessing a packet stored in the packet unit 72 in response to a data write request. When the process is executed by the CPU 50, first, as shown in FIG.
It is supposed to move to.

In step S50, it is determined whether or not there is a data read request to read data from the packet by the request source process, and when it is determined that there is a data read request.
(Yes) moves to step S52, acquires ID information for specifying a packet from which data is to be read from the request source process, and moves to step S54. Step S5
In 4, a reference index corresponding to the acquired ID information is acquired from the ID index conversion table 420, and the acquired value is a sign “−” indicating that the packet does not exist.
1 ”, and when the obtained value is not the code“ −1 ”indicating that the packet does not exist (Yes), the process proceeds to step S56, and the obtained reference index is changed. Originally, the data of the data portion 82 of the packet is acquired from the packet address management table 400 and passed to the request source process, and a series of processes is completed to return to the original process.

On the other hand, when it is determined in step S54 that the value obtained from ID index conversion table 420 is code "-1" indicating that no packet exists.
(No) moves on to step S58 and outputs an error,
A series of processes is terminated and the process returns to the original process. On the other hand, when it is determined in step S50 that there is no data read request by the request source process (No), the process proceeds to step S60,
The request source process determines whether or not there is a data write request to write data to the packet. If it is determined that there is a data write request (Yes), the process proceeds to step S62 and the packet to be written I to identify
The D information is obtained from the request source process, and the routine goes to Step S64.

In step S64, a reference index corresponding to the obtained ID information is obtained from the ID index conversion table 420, and it is determined whether or not the obtained value is a code "-1" indicating that no packet exists. And
If it is determined that the obtained value is the code “−1” indicating that the packet does not exist (No), the process proceeds to step S66.
Then, a new data write process is executed, a series of processes is completed, and the process returns to the original process.

On the other hand, the ID index conversion table 42
When it is determined that the value obtained from 0 is not the code “−1” indicating that the packet does not exist (Yes), the process proceeds to step S68 to execute the data update process, and terminate the series of processes. Return to the original processing. On the other hand, step S
At 60, when it is determined that there is no data write request by the request source process (No), a series of processes is terminated and the process returns to the original process.

Next, the new data writing process in step S66 will be described in detail with reference to FIG. FIG.
9 is a flowchart showing a data new writing process.
The new data write process is executed when new data is written to blocks A and B in packet units. In the initial state, block A is used as a data write area and data is written to block A. After that, as shown in FIG. 13, when the CPU 50 executes the processing, data is written into a block serving as a data writing area in accordance with the processing. The process proceeds to S100.

In step S100, it is determined whether or not the update of the block has been completed. If it is determined that the update of the block has been completed (Yes), the process proceeds to step S102. If it is determined that the update has not been completed (No) ) Waits in step S100 until the block update is completed. In step S102, it is determined whether an area for generating a packet for storing new data is insufficient in the packet section 72, and a sufficient area for generating a packet is determined in the packet section 7.
If it is determined that the number is 2 (No), the process proceeds to step S104.

In step S104, a packet for storing new data is generated in the packet section 72, and the flow advances to step S108. In step S104, specifically, if no packet has been generated in the packet section 72, a packet is generated from the start address of the packet section 72, and if a packet has already been generated in the packet section 72, the packet is generated. The packet is generated from the address next to the end address of the packet at the end counted from the start address of the unit 72. When a packet is generated, the ID information acquired from the request source process, a serial number indicating the order in which the packet is generated, and data length information indicating the data length of new data are written in the management unit 80, respectively.
Set the state information to the first state.

In step S108, the new data is written into the data portion 82 of the generated packet, and
Proceeding to 110, the state information of the generated packet is stored in the second
Then, the process proceeds to step S112 to generate a reference index. The generated reference index, the address of the packet whose storage position is specified on the flash ROM 52, the data length and the data content written in step S108 are stored in the packet. The information is registered in the address management table 400, and a series of processing is ended to return to the original processing.

On the other hand, in step S102, the area for generating a packet for storing new data is
If it is determined that there is a shortage in step 2 (Yes), step S
The process proceeds to 128, where a block update request for updating the block is output, and the process proceeds to step S100. next,
The data updating process in step S68 will be described in detail with reference to FIG. FIG. 14 is a flowchart showing the data update processing.

The data update process is executed when updating data for blocks A and B in packet units.
In the initial state, block A is used as a data write area, data is written into block A, and thereafter, data is written into a block that becomes a data write area according to processing. When executed by the CPU 50, first, as shown in FIG.
It is supposed to move to.

In step S113, it is determined whether or not the update of the block has been completed. If it is determined that the update of the block has been completed (Yes), the process proceeds to step S114. ) Waits in step S113 until the block update is completed. In step S114, it is determined whether or not an area for generating an update destination packet for storing the updated data is insufficient in the packet unit 72, and it is determined that the packet unit 72 has a sufficient area for generating the packet. (No), the step S
Move to 116.

In step S116, an update destination packet for storing the updated data is generated in the packet section 72, and the flow advances to step S118. In step S116, specifically, when a packet is generated, ID information indicating the same ID as the ID given to the update source packet storing the data before update, and a serial number indicating the order in which the packet is generated , And data length information indicating the data length of the updated data are written in the management unit 80, and the state information is set to the first state. The location where the packet is generated is the same as in step S104.

In step S118, the state information of the update source packet is set to the third state, and the flow shifts to step S122 to update the updated data in the data portion 8 of the update destination packet.
2 and the process proceeds to step S124, where the status information of the update destination packet is set to the second status, and the process proceeds to step S1.
Then, the process goes to step S26, where the status information of the update source packet is set to the fourth status, and a series of processes is ended to return to the original process.

On the other hand, if it is determined in step S114 that the area for generating the update destination packet for storing the updated data is insufficient in the packet section 72 (Yes),
The process shifts to step S132 to output a block update request to update the block, and shifts to step S113. Next, the block update processing will be described in detail with reference to FIG. FIG. 15 is a flowchart showing the block update processing.

The block updating process is performed in step S12
8. This is a process of updating blocks A and B in response to the block update request output in S132, and when executed by CPU 50, first, as shown in FIG. 15, the process proceeds to step S300. I have. Step S3
At 00, the processing for the blocks A and B is executed with reference to the processing definition table shown in FIG.
Then, it is determined whether there is a block update request in steps S128 and S132, and if it is determined that there is a block update request (Yes), the process proceeds to step S304.

In step S304, it is determined whether or not block A is valid. If it is determined that block A is valid (Yes), the process proceeds to step S306. In step S304, the validity / invalidity of the block is determined as follows. If the area status information 3, 4 is stored in the block area management unit 70, it is determined that the block is valid, and the area state information 1, 2, 5, 5 is stored in the block area management unit 70. When the block is present or when the state of the block is not initialized, it is determined that the block is invalid.

In step S306, the area status information 4 is written in the area management unit 70 of the block A, and in step S3
Move to 00. On the other hand, if it is determined in step S304 that block A is invalid (No) (in this case, block B should be valid, that is, if it is determined that block B is valid), the process proceeds to step S308. Then, the area state information 4 is written to the area management unit 70 of the block B, and the process shifts to step S300.

On the other hand, if it is determined in step S302 that there is no block update request in steps S128 and S132 (No), the process proceeds to step S300. Next, the process based on the process definition table in step S300 will be described in detail with reference to FIGS. FIGS. 16 and 17 are flowcharts showing processing based on the processing definition table.

When the process based on the process definition table is executed in step S300, as shown in FIGS. 16 and 17, the process first proceeds to step S400. In step S400, the area state information of the blocks A and B is acquired, and the process proceeds to step S402, and processing for the blocks A and B is selected from the acquired area state information with reference to the processing definition table shown in FIG. .

When the process for initializing the block A is selected as a result of the selection in the step S402 (), the process proceeds to step S404 to initialize the block A, and then proceeds to step S406 to initialize the block A. "1"
The addition is performed, and the initialization count information is written to the area management unit 70 of the block A, and the process proceeds to step S408, where the area state information 1 is written to the area management unit 70 of the block A. Return to processing.

On the other hand, when the process of initializing the block B is selected as a result of the selection in the step S402 (), the process shifts to the step S410 to initialize the block B, shifts to the step S412, and shifts to the step S412. Is added to the initialization number of the block B, the initialization number information is written to the area management unit 70 of the block B, and the process proceeds to step S414.
The area state information 1 is written in the area management unit 70 of the block B, and a series of processing is ended to return to the original processing.

On the other hand, when the process of updating block B to block A is selected as a result of the selection in step S402
() Moves to step S416, writes the area state information 2 to the area management unit 70 of block A, and proceeds to step S416.
The flow shifts to 418, where the valid packet data of block B is written to the packet section 72 of block A so that the storage positions are ordered, and the flow shifts to step S420. Specifically, in step S418, in order to obtain data of a valid packet of the block B, all the packets of the block B are accessed, and it is determined whether each packet is valid or invalid. Instead of acquiring the data, access is made only to valid packets by referring to the packet address management table 400, and the data is acquired. As a result, block B is converted to block A
Can be performed in a relatively short time. This is the same in step S426.

In the step S420, the area state information 3 is written in the area management section 70 of the block A, and in the step S4
Then, the process goes to 22 to write the area state information 5 to the area management unit 70 of the block B, to end a series of processing and return to the original processing. On the other hand, when the process of updating block A to block B is selected as a result of the selection in step S402
() Moves to step S424, writes the area state information 2 to the area management unit 70 of block B, and proceeds to step S424.
The flow shifts to 426, where the valid packet data of block A is written to the packet section 72 of block B such that the storage positions are ordered, and the flow shifts to step S428, where the area management section 70 of block B is written. Then, the process moves to step S430, writes the region status information 5 to the region management unit 70 of the block A, ends a series of processing, and returns to the original processing.

On the other hand, as a result of the selection in step S402, when the process of using the block A as the data write area is selected (), the flow shifts to step S432, where the block A is set as the data write area, and the process proceeds to step S433. Then, the block update request is released, a series of processing is ended, and the processing returns to the original processing. On the other hand, as a result of the selection in step S402, when the process of using the block B as the data write area is selected (), the process proceeds to step S434, the block B is used as the data write region, and the process proceeds to step S435. Then, the block update request is canceled, and a series of processing is ended to return to the original processing.

On the other hand, as a result of the selection in step S402, when the processing for performing the initialization processing on the blocks A and B is selected (), the flow shifts to step S436 to initialize the blocks A and B, and then proceeds to step S438. Then, the area state information 1 is written to the area management unit 70 of the block A,
A series of processes is terminated and the process returns to the original process. On the other hand, if none of the above processes is selected as a result of the selection in step S402 (x), a series of processes is terminated and the process returns to the original process.

Next, the operation of the above embodiment will be described with reference to the drawings. First, when the computer 100 is started, the packet address management table 400 is generated on the RAM 54 by the CPU 50 through step S10, and if it is determined that the packet is a valid packet, the process proceeds to steps S16 to S20. Data is read from the data section 82, a reference index is generated, the generated reference index, the address of the packet on the flash ROM 52, and the data section 8 of the packet.
2 are registered in the packet address management table 400.

Then, after repeating step S22,
A series of processes in steps S16 to S20, S12, and S14 are performed for all packets in the packet unit 72,
When the generation of the packet address management table 400 is completed, the ID index conversion table 420 is generated on the RAM 54 via step S24. Next, a case where data is read from the blocks A and B in packet units will be described.

When a data read request is received from the request source process, data reading is started for blocks A and B which are data write areas. At this time,
Along with the data read request, ID information for specifying a packet from which data is to be read is given. Reading of data is performed as follows. The CPU 50 passes the reference index corresponding to the given ID information through the steps S50 to S56 to the ID index conversion table 4.
20, the data of the data part 82 of the packet is acquired from the packet address management table 400 based on the acquired reference index. Then, the obtained data is transferred to the request source process, whereby the data reading is completed.

If the packet specified by the ID information given from the request source process does not exist as a valid packet, an error is output through steps S50 to S54 and S58. Next, a case where new writing of data to blocks A and B is performed in packet units will be described.

In the initial state, block A is used as a data write area, and data is written to block A. When a new data write request is received from the request source process, new writing of data to the block A that is a data write area is started. At this time, along with the new data write request, ID information for specifying the data to be stored and the packet in which the data is to be written are provided.

The new writing of data is performed as follows. The CPU 50 performs a new data writing process through steps S60 to S66, and proceeds to step S100.
Through steps S110 to S110, a packet for storing new data is generated in the packet unit 72 of the block A. At this time, the given ID information, a serial number indicating the order in which this packet is generated, and data length information indicating the data length of the new data are written in the management unit 80, and the state information is stored in the first state (data (Writing). Then, the data to be stored is written into the data portion 82 of the generated packet, and the state information of the generated packet is set to the second state (data writing completed).

In a normal state in which data writing is not interrupted, data is written as a packet in the packet section 72 of the block A as described above. For example, when data writing is interrupted for some reason, It operates as follows. When the data writing is interrupted, when the system is restarted, the packet address management table 400 and the ID index conversion table 420 are generated through steps S10 to S24. At this time, since the state information is in the first state, the packet in which the data writing has been performed immediately before the interruption of the data writing is determined to be an invalid packet through step S16. And the packet address management table 400
Is not registered.

Thereafter, when a data read request is received from the request source process, data reading from block A is started because block A is still a data write area here. At this time, it is assumed that the same ID information is given from the request source process together with the data read request.
However, since the packet specified by the given ID information does not exist as a valid packet,
An error is output and data is not read.

When the data writing is not interrupted and the data writing is completed normally, when the data read request is received, the given ID is passed through steps S50 to S56.
Based on the information, the data of the data portion 82 of the packet is obtained from the packet address management table 400. Then, the obtained data is transferred to the request source process, whereby the data reading is completed.

In the above description, the case where data is newly written to the block A has been described. However, the case where data is newly written to the block B operates in the same manner as described above. Next, a case in which data is updated for blocks A and B in packet units will be described. Note that some packets have already been generated in block A,
Here, any data of those packets is updated.

In the initial state, block A is used as a data write area, and data is written to block A. When a data update request is received from the request source process, data update is started for block A, which is a data write area. At this time, the updated data and the ID information of the packet to be updated are given together with the data update request.

Updating of data is performed as follows. C
The data update process is executed by the PU 50 through steps S60 to S64 and S68, and
Through 126, an update destination packet for storing the updated data is generated in the packet unit 72 of the block A.
At this time, the given ID information, a serial number indicating the order in which this packet is generated, and data length information indicating the data length of the updated data are written in the management unit 80, and the state information is stored in the first state. (Data writing), and the status information of the update source packet is set to the third status (data updating). Then, the updated data is written to the data portion 82 of the update destination packet, the status information of the update destination packet is set to the second state (data writing completed), and the status information of the update source packet is set to the fourth state. Set to status (data update completed).

In a normal state in which data updating is not interrupted, data is written and updated as a packet in the packet section 72 of the block A. For example, if the data updating is interrupted for some reason, It operates as follows. If the update of data is interrupted, the system is restarted, and steps S10 to S2
4, a packet address management table 400 and an ID index conversion table 420 are generated. At this time, since the update source packet is stored at the start address side of the packet unit 72 rather than the update destination packet,
The storage location of the update source packet is specified first, but the update source packet has been
Since the state information is in the third state, step S1
Through 6 to S20, it is determined that the packet is a valid packet,
It is registered in the packet address management table 400. On the other hand, since the update of the data has been interrupted, the status information is in the first state, so that the packet is determined as an invalid packet through step S16, and the packet address management is performed. It is not registered in the table 400.

After that, when a data read request is received from the request source processing, data reading to block A is started because block A is still a data write area here. At this time, it is assumed that the same ID information is given from the request source process together with the data read request.
Then, through the steps S50 to S56, the given I
Based on the D information, the data of the data portion 82 of the update source packet is obtained from the packet address management table 400. Then, the obtained data is transferred to the request source process, whereby the data reading is completed.

When the data update is not interrupted and the data update is completed normally, when the data read request is received, the given ID is passed through steps S50 to S56.
Based on the information, the data of the data portion 82 of the update destination packet is obtained from the packet address management table 400. Then, the obtained data is transferred to the request source process, whereby the data reading is completed.

In the above, the case where data is updated for the block A has been described. However, the case where data is updated for the block B operates in the same manner as described above. Next, a case where the blocks A and B are updated will be described with reference to FIG. FIG. 18 is a diagram for explaining a case where block A is updated to block B. When data writing / updating is continuously performed on the block A using the block A as a data write area, as shown in FIG. It becomes a mixed state. In the example of FIG.
Between a valid packet whose D is “01” and a valid packet whose ID is “03”, there are two packets that have been invalidated due to data update. When a large number of invalid packets exist in the packet section 72 of the block A, new writing / updating of data cannot be performed.

Therefore, when a new data write request or a data update request is received from the request source processing, there is not enough space in the packet section 72 of the block A to generate a packet for storing data to be stored / updated. When you do
In steps S128 and S132, a block update request is output. Upon receiving the block update request, the update from block A to block B is started. It is assumed that the block B has already been initialized, that is, the area management unit 70 of the block B stores the area state information 1
(Initialization completed) is written.

Updating of a block from block A to block B is performed as follows. Through steps S300 to S304, the CPU 50 refers to the processing definition table to execute processing for blocks A and B, and determines whether block A is valid. At this time, since the block A is valid, the area state information 4 (data is being moved) is written to the area management unit 70 of the block A in step S306.

Next, when the area state information 4 is written in the area management section 70 of the block A and the area state information 1 is written in the area management section 70 of the block B, steps S300 and S40 are performed.
Through steps 0, S402, and S424 to S430, the processing definition table is referred to, the area state information 2 (data is being written) is written in the area management unit 70 of the block B, and as shown in FIG. Valid packet data is
The data is written in the packet section 72 of the block B so that the storage positions are arranged in order, the area state information 3 (data writing completed) is written in the area management section 70 of the block B, and the area management section 70 of the block A is written. Is written in the area status information 5 (data transfer completed). When the block update is completed in this way, block A becomes a data update area, and block B becomes a data write area instead of block A.

When the area state information 5 is written in the area management section 70 of the block A and the area state information 3 is written in the area management section 70 of the block B, steps S300 and S40 are performed.
0, through steps S402 to S408, the processing definition table is referred to, the block A is initialized, the number of initializations of the block A is incremented by “1”, and the area management unit 70 of the block A is added.
The initialization number information is written in the area management unit 70, and the area state information 1 is written in the area management unit 70 of the block A.

In a normal state where the updating of the block is not interrupted, the data of the valid packet of the block A is written in the packet section 72 of the block B as described above. For example, the updating of the block is interrupted for some reason. In this case, the following operation is performed. First, if the update of data is interrupted while data is being written to block B, when the system is restarted, block A
Since the area status information 4 has been written in the area management unit 70 of the block B and the area status information 2 has been written in the area management unit 70 of the block B, steps S300, S400, S402, and S410 are performed.
Through S414, the process definition table is referred to, the block B is initialized, the number of initializations of the block B is incremented by "1", and the information on the number of initializations is written to the area management unit 70 of the block B, Block B area management unit 7
0 is written to the area state information 1.

When the area state information 4 is written in the area management unit 70 of the block A and the area state information 1 is written in the area management unit 70 of the block B, steps S300 and S40 are performed.
0, S402, and S424 to S430, the processing definition table is referred to, the area state information 2 is written in the area management unit 70 of the block B, and as shown in FIG. Is rewritten into the packet section 72 of the block B so that the storage positions are arranged in order, the area state information 3 is written in the area management section 70 of the block B, and the area management section 70 of the block A is written.
Area status information 5 is written to the. Thereafter, the block A is initialized, and the area state information 1 is written in the area management unit 70 of the block A.

Next, if the update of the data is interrupted while the block A is being initialized, the system is restarted and the area status information 5 of the block A is stored in the area management unit 70 of the block A. Since the area state information 3 has been written in the area management unit 70, steps S300, S400,
After S402 to S408, the processing definition table is referred to, the block A is reinitialized, the number of initializations of the block A is incremented by “1”, and the area management unit 70 of the block A is added.
The initialization number information is written in the area management unit 70, and the area state information 1 is written in the area management unit 70 of the block A.

In the above, the case where the update from the block A to the block B is performed has been described. However, the operation when the update from the block B to the block A is performed in the same manner as described above. As described above, in the present embodiment, the packet address management table 400 and the ID index conversion table 420 in which access information for accessing a valid packet among the packets stored in the packet unit 72 are generated at the time of startup. The access to the packet is performed with reference to the generated packet address management table 400 and the ID index conversion table 420.

Thus, it is not necessary to determine whether the packet is valid or invalid each time the packet is accessed. Therefore, access to the packet can be made relatively faster than in the past. Further, in the present embodiment, the packet address management table 400
Contains a valid packet.

Thus, the data reading from the packet is performed without passing through the flash ROM 52, so that the speed of reading the data from the packet can be relatively increased.
Further, in the present embodiment, the packet address management table 400 and the ID index conversion table 420
Was stored on the RAM 54. As a result, when the power supply to the RAM 54 is cut off, the packet address management table 400 and the ID index conversion table 420 disappear along with this, so that the packet address management table 400 Further, it is not necessary to perform the process of initializing the ID index conversion table 420.

Further, in the present embodiment, when storing data, a packet for storing data is generated in the packet portion 72 of the block, and the state information of the packet is set to the first state at the start of data writing. Is set, data is written to the data portion 82 of the packet, and when the data writing is completed, the status information of the packet is set to the second state.
Is determined to be a valid packet, and a packet whose status information is the first state or the fourth state is determined to be an invalid packet.

As a result, the data is not identified as a valid packet until the data writing is completed. Therefore, even if the data writing is interrupted for some reason until the data writing is completed, the data writing is not performed. The data of the packet being loaded is not treated as correct data. In addition, since the erasure of data on the flash ROM 52 may be performed by setting the state information of the packet storing the data to be erased to the fourth state, the number of times of initialization of the flash ROM 52 is reduced. . Therefore, as compared with the related art, it is possible to prevent the life of the flash ROM 52 from being shortened and to rewrite data at high speed, and to write data with high reliability.

Furthermore, in the present embodiment, when updating the data of a packet, an update destination packet for storing the updated data is generated in the packet portion 72 of the block, and the update source packet is started when data writing is started. Is set to the third state and the state information of the update destination packet is set to the first state, and the data portion 82 of the update destination packet is set.
The updated data is written to the second packet, and when the data writing is completed, the status information of the update destination packet is set to the second status, and the status information of the update source packet is set to the fourth status. Alternatively, a packet in the third state is determined to be a valid packet, and a packet in the state information of the first state or the fourth state is determined to be an invalid packet.

As a result, since the update destination packet is not identified as a valid packet until the data update is completed, even if the data update is interrupted for some reason until the data update is completed, The data of the update destination packet during data writing is not handled as correct data. In this case, the data of the update source packet is handled as correct data. Therefore,
Data can be updated with higher reliability than before.

Further, in the present embodiment, the storage position of the packet is specified based on the data length information. Thereby, data of an arbitrary data length that does not exceed the storage capacity of the packet section 72 can be stored as one packet in the packet section 72 of the block without being divided, so that variable-length data can be easily managed. .

Further, in this embodiment, when updating a block, the area status information 4 is written into the area management unit 70 of one of the blocks A and B at the start of data writing, and the area of the other block is written. The area status information 2 is written to the management unit 70, the valid packet data of the packet unit 72 of one block is written to the packet unit 72 of the other block, and the data is written to the area management unit 70 of one block when the data writing is completed. The state information 5 is written and the area state information 3 is stored in the area management unit 70 of the other block.
Is written, and the block in which the area status information 3, 4 is written in the area management unit 70 is determined to be a valid block, and the block in which the area status information 1, 2, 5 is written in the area management unit 70 is determined. It is determined that the block is invalid.

As a result, until the block update is completed, the other block to be updated is not identified as a valid block. Therefore, the block update is interrupted for some reason until the block update is completed. Even if the data is written, the data in the other block in the middle of data writing is not treated as correct data. in this case,
The data of one block before the update is handled as correct data. Therefore, data can be updated with higher reliability.

Further, in this embodiment, the area management unit 7
A block in which the area status information 1, 2, 5 is written to 0 is used as a data update area. Thus, a new block does not become a data update area every time a block is updated.
52 storage areas can be used effectively.

Further, in the present embodiment, blocks A,
The processing for the blocks A and B is executed by referring to the processing definition table to which the processing for the blocks A and B is assigned according to the state of the area state information of B. Thereby, according to the state of the area state information of blocks A and B,
Since there is no need to sequentially determine the processing for the blocks A and B, the processing related to data rewriting can be simplified.

Further, in the present embodiment, the block is
The flash ROM 52 is composed of data initialization units. Thereby, the number of times of initialization of the flash ROM 52 can be minimized. Furthermore, in this embodiment, when the area management information 4 is written in the area management unit 70 of one block and the area management information 2 is written in the area management unit 70 of the other block, Blocks are now initialized.

Thus, if data is interrupted while writing data to the packet section 72 of the other block for some reason, when the system is restarted, the other block is initialized and the packet of the other block is initialized. Part 7
2, the data is rewritten, so that the data can be updated with higher reliability. Furthermore, in the present embodiment, when the area management information 5 is written in the area management unit 70 of one block and the area management information 1, 2, 3 is written in the area management unit 70 of the other block. Tried to initialize one block.

Thus, if the data update is interrupted during initialization of one block for some reason, when the system is restarted, one block is re-initialized. Can be performed with higher reliability. In the above embodiment, the flash ROM 52 corresponds to the flash memory according to any one of claims 1 to 5, and includes a packet address management table 400 and an ID index conversion table 42.
0 corresponds to the access information management table described in claim 1, 2 or 5, and the ID information corresponds to the packet identification information described in claim 3. The RAM 54 corresponds to the storage medium described in claim 5.

In the above embodiment, the block is constituted by the data initialization unit of the flash ROM 52. However, the present invention is not limited to this. The block may be constituted by combining two or more data initialization units. Even with such a configuration, the number of times of initialization of the flash ROM 52 can be minimized. Further, in the above-described embodiment, the case where the data update is interrupted during the transition from step S116 to step S118 is not particularly described.
When a packet having the third state and a packet having the first state information coexist, the packet having the second or third state information may be determined to be a valid packet. Good.

Further, in the above embodiment, the case where the update of data is interrupted during the transition from step S124 to step S126 is not specifically described. When a packet having the status information of the second state and a packet having the status information of the second state coexist, the packet having the status information of the second state may be determined to be a valid packet.

Further, in the above embodiment, the case where the update of the block is interrupted during the transition from step S306 to step S424 or the transition from step S308 to step S416 is not particularly described. To cope with the case, the area management unit 7
When a block in which the area state information 4 is written in the area 0 and a block in which the area state information 1 is written in the area management unit 70 coexist, the block in which the area state information 4 is written in the area management unit 70 is determined. You may comprise so that it may be determined that it is a valid block.

Further, in the above embodiment, the case where the update of the block is interrupted during the transition from step S428 to step S430 or the transition from step S420 to step S422 is not particularly described. To cope with the case, the area management unit 7
When a block in which the area state information 3 is written in the area 0 and a block in which the area state information 4 is written in the area management unit 70 coexist, the block in which the area state information 3 is written in the area management unit 70 is determined. You may comprise so that it may be determined that it is a valid block.

In the above-described embodiment, each block is used as a data write area and one block as a data update area.
However, the present invention is not limited to this.
Alternatively, a plurality of blocks as a data write area may be used. In this case, the condition is that a plurality of blocks are not updated at the same time. When a plurality of blocks are updated at the same time, blocks as data update areas may be prepared in a number equal to the number at which the storage area is updated at the same time.

Further, in the above-described embodiment, it is explained that, for packets having the same ID information, a packet having status information in the second state and a packet having status information in the third state may coexist. But strictly speaking,
There may be more than one packet having the same ID information. For example, if the data update is interrupted after rewriting the status information of the update destination packet and before rewriting the status information of the update source packet, the status information becomes the second status.
Is determined to be valid, but the packet whose status information is in the third status remains as it is. Therefore, if this state continues several times, there will be a plurality of packets whose state information is the third state.
On the other hand, the number of packets whose status information is in the second state is always one when present.

Further, in the above embodiment, when executing the operation processing shown in the flowcharts of FIGS. 9 and 12 to 17, the case where a program stored in advance in the flash ROM 52 is executed has been described. The program is not limited to a program stored in a storage medium on which a program indicating these procedures is recorded.
The program may be read into M54 and executed.

Here, the storage medium is a semiconductor storage medium such as a RAM or a ROM, a magnetic storage type storage medium such as an FD or HD, an optical reading type storage medium such as a CD, CDV, LD, or DVD, or an MO storage medium. A magnetic storage type / optical readout type storage medium includes any storage medium that can be read by a computer irrespective of an electronic, magnetic, optical or other reading method.

Further, in the above embodiment, the flash memory data management device according to the present invention is used as a block of the flash ROM 52 composed of data initialization units as shown in FIG. Although the present invention has been applied to the case where data is stored in units of variable-length packets, the present invention is not limited to this, and can be applied to other cases without departing from the gist of the present invention.

[0121]

As described above, according to the data management apparatus for a flash memory according to the first aspect of the present invention, the update destination packet is not identified as a valid packet until the data update is completed. Therefore, even if the data update is interrupted for some reason until the data update is completed, the data of the update destination packet during the data writing is not treated as correct data. Further, it is not necessary to determine whether the packet is valid or invalid each time the packet is accessed. Therefore, as compared with the related art, it is possible to prevent a decrease in the life of the flash memory and to update data at a high speed, and to update data with high reliability. The advantage is that access can be relatively speeded up.

Further, according to the flash memory data management device of the present invention, since the data reading from the packet is performed without passing through the flash memory, the data reading from the packet is relatively speeded up. The effect that can be performed is also obtained. Furthermore, according to the data management device for a flash memory according to the present invention, when the power supply to the storage medium is cut off, the access information management table disappears with the power supply, and the data is stored in the flash memory. As compared with the configuration in which the access information management table is updated, an effect that the processing for initializing the access information management table does not have to be performed when the content of the access information management table needs to be updated is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer 100.

FIG. 2 is a diagram showing a data structure of blocks A and B.

FIG. 3 is a diagram showing a data structure of an area management unit 70.

FIG. 4 is a diagram showing contents of area state information.

FIG. 5 is a diagram showing a data structure of a packet unit 72.

FIG. 6 is a diagram showing a data structure of a management unit 80.

FIG. 7 is a diagram showing the contents of state information.

FIG. 8 is a diagram showing a data structure of a process definition table.

FIG. 9 is a flowchart illustrating a table generation process.

FIG. 10 is a diagram showing a data structure of a packet address management table 400.

FIG. 11 is a diagram showing a data structure of an ID index conversion table.

FIG. 12 is a flowchart illustrating a packet access process.

FIG. 13 is a flowchart showing a data new writing process.

FIG. 14 is a flowchart illustrating a data update process.

FIG. 15 is a flowchart showing a block update process.

FIG. 16 is a flowchart illustrating a process based on a process definition table.

FIG. 17 is a flowchart illustrating a process based on a process definition table.

FIG. 18 is a diagram for describing a case where a block A is updated to a block B.

[Explanation of symbols]

100 Computer 50 CPU 52 ROM 54 RAM 55 VRAM 56 graphic chip 57 RTC 58 I / F 59 bus 60 touch panel 70 area management unit 72 the packet 80 management unit 82 data portion P ₁ to P _n packets 400 packet address management table 420 ID Index Conversion table

Claims (5)

[Claims] 1. A storage unit for storing data in packet units in a storage area of a flash memory, wherein the packet includes a management unit for storing management data related to management of the packet, and a storage unit for storing data. The management unit stores status information indicating the status of the packet as the management data. When updating the data of the packet, the updated data is stored. An update destination packet is generated in the storage area, and at the start of data writing, the status information of the update destination packet is set to the first state and the status information of the update source packet storing the data before update is stored in the first state. 3, the updated data is written in the data portion of the update destination packet, and when the data writing is completed, the status information of the update destination packet is changed to the second. State and the state information of the update source packet to a fourth state, the state information is determined to be a packet in the second state or the third state is a valid packet, the state information In an apparatus for determining that a packet in the first state or the fourth state is an invalid packet, the access information for accessing the valid packet among the packets stored in the storage area is determined. A data management device for a flash memory, wherein the packet is accessed by referring to a registered access information management table. 2. The flash memory data management device according to claim 1, wherein the access information management table is generated at startup. 3. The access information according to claim 1, wherein the access information includes packet identification information for identifying the packet, and an address for specifying a storage position of the packet. A data management device for a flash memory. 4. The flash memory data management device according to claim 3, wherein the access information further includes the valid packet. 5. The data management device for a flash memory according to claim 1, wherein the access information management table is stored in a storage medium that requires power to hold the data. .