JP2001144074A - Surface treatment device for semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve quality of surface treatment of a semiconductor wafer and workability. SOLUTION: A heating ring 23 for supporting and heating the outer peripheral portion of a semiconductor wafer 1 as placed is provided on a wafer support base 22. An annular engaging recessed portion 22b and an annular support base side vacuum chamber 28 are provided on the outer peripheral side of the upper surface of the wafer support base 22. A guide ring 26 for positioning while engaged in the engaging recessed portion 22b is provided on the lower surface side of a cylindrical wafer holding ring 25. A packing 24 for sealing the outer peripheral edge portion of a surface 1a to be treated of a semiconductor wafer 1 is provided to this guide ring 26. An annular support base side vacuum chamber 30 is provided on the lower surface of the wafer holding ring 25 and a cylinder 27 for fastening by vacuum is provided between this vacuum chamber 30 and the support base side vacuum chamber 28. When the wafer holding ring 25 and the wafer support base 22 are fastened, a wafer treatment chamber 35 is constituted with the surface 1a to be treated of the semiconductor wafer 1 as a bottom surface and the inner peripheral surface of the wafer holding ring 25 as an inner wall, into which etchant is directly charged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor wafer surface treatment apparatus for performing a process such as an etching process on a surface of a semiconductor wafer to be processed.

[0002]

In manufacturing a sensor chip such as a semiconductor acceleration sensor or a semiconductor pressure sensor, for example, as shown in FIG. 9, an outer peripheral portion of a semiconductor wafer (silicon wafer or SOI wafer) 1 is removed. Hundreds to thousands of sensor chips 2 are formed at the site, and then each chip 2 is cut off. In the case of an acceleration sensor, the sensor chip 2 has a shape as shown in FIG. 10, and a signal processing circuit and a power supply electrode (not shown) are formed on the lower surface of the sensor chip 2, and the sensor chip 2 is formed on the upper surface of the sensor chip 2. Is such that a concave portion 2a is formed with an island-shaped bulge left in the center.

In this case, generally, in order to form the concave portion 2a, as shown in FIG. 11A, the processing surface 1a (the upper surface in the figure) of the semiconductor wafer 1 is removed except for the portion where the concave portion 2a is formed. After being covered with the mask 3, the surface 1a to be processed is
Is immersed in a strong alkaline solution such as potassium hydroxide, for example. FIG. 11 (b)
As shown in FIG. 1, a groove 4 for chip separation is simultaneously formed by this etching process.

In performing the above-mentioned etching process, as shown in FIG. 12, the semiconductor wafer 1 has a portion excluding a portion immersed in an etching solution, that is, the entire one side (circuit forming surface) and the outer peripheral edge of the surface 1a to be processed. In a state where the portion is masked by the wax 5, the portion is held by a ceramic plate 6 having high corrosion resistance, for example, as a masking jig.

[0005] Then, as shown in FIG. 13 (a), a plurality of plates 6 holding the semiconductor wafer 1 are supported by a carrier 7, and in that state, as shown in FIG. 7 is immersed in an etching bath 9 containing an etching solution 8. After being immersed in the etching solution 8 for a time until the etching amount reaches a predetermined value, the carrier 7 is pulled up from the etching tank 9 and transferred to a washing tank 11 containing pure water 10 as shown in FIG. Stop the etching. After sufficiently washing with pure water, the carrier 7 is taken out of the washing tank 11 and the semiconductor wafer 1 is dried as shown in FIG. 13 (d). By removing the semiconductor wafer 1 from 6, the etching process is completed.

However, in the above-described conventional etching method, since the semiconductor wafer 1 is immersed in the etching solution 8 together with the plate 6 serving as a masking jig, impurities adhering to the plate 6 during the masking work remove the etching solution 8. There has been a chronic problem of contamination or contamination of the wax 5 into the etching solution 8, resulting in deterioration of quality in the etching process using the high-purity etching solution 8. Also, the masking operation with the wax 5 and the removal operation of the wax 5 after the etching are difficult to automate because the fragile wafer 1 is handled, resulting in poor workability and low productivity.

As a masking jig different from the above-mentioned one using the plate 6 and the wax 5, a rubber packing 14 is interposed between the backup plate 12 and the mask ring 13 as shown in FIG. In some cases, holding and masking are performed so that the semiconductor wafer 1 is sandwiched between them. In this case, the backup plate 12 and the mask ring 13 are connected by bolts 15 at four locations on the outer peripheral side.

However, in this case, since the bolt is mechanically tightened by the bolt 15, there is a problem that stress is locally applied to the wafer 1. In recent years, the size of the wafer 1 has been increased from the conventional 100 mmφ (corresponding to 4 inches) to 150 m.
mφ (equivalent to 6 inches), and the miniaturization (thinning) and high accuracy of the sensor chip 2 are also desired. Particularly, the groove 4 as shown in FIG. There is a problem that the wafer 1 to be formed is easily cracked.

Further, as shown in FIG. 15, a thin circular container-shaped base plate 16 and a packing 17 are provided.
The semiconductor wafer 1 is sandwiched between a mask ring 18 fitted into the inside of the base plate 1 and the packing 17 and the base plate 1.
The vacuum chamber 16a formed between the wafer 1 and the vacuum chamber 6 is evacuated (in a reduced pressure state) so that the wafer 1 is sandwiched and held.

However, in this case, when the semiconductor wafer 1 is warped in the manufacturing process, stress acts on the wafer 1 as shown in FIG.
There is a problem that the wafer 1 having a large diameter or the groove 4 is easily cracked. Furthermore, the thermal cycle of raising the temperature in the etching step and rapidly cooling in the pure water cleaning step causes the masking jig to thermally expand and contract, which may cause mechanical stress on the wafer and cause cracking.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor wafer surface treatment apparatus capable of improving the quality of surface treatment of a semiconductor wafer and improving workability. To offer.

[0012]

According to a first aspect of the present invention, there is provided a surface treatment apparatus for a semiconductor wafer, wherein the semiconductor wafer is placed on a wafer support base with its surface to be processed as an upper surface. The outer peripheral edge of the semiconductor wafer is sealed by pressing the packing from above with a cylindrical wafer pressing ring, and the wafer is sealed by a fastening means. The holding ring and the wafer supporting base are configured to be fastened to the entire circumference with an equal force, and in the fastened state, the processing surface of the semiconductor wafer is set to the inner bottom surface, and the inner circumferential surface of the wafer holding ring is set to the inner wall. The wafer processing chamber described above is configured.

According to this, the semiconductor wafer is held so as to be sandwiched between the wafer support base and the wafer holding ring via the packing, and in this holding state, the packing is applied to the surface to be processed of the semiconductor wafer by the packing. The portion excluding the outer peripheral edge is in a masked state. At this time, since the fastening means fastens the entire circumference with a uniform force, it is possible to prevent mechanical stress locally acting on the semiconductor wafer. Since the wafer processing chamber is configured with the wafer support base and the wafer holding ring fastened, the wafer processing chamber functions as a masking jig for holding the semiconductor wafer and also functions as a processing container. In addition, a processing liquid or the like can be supplied directly into the wafer processing chamber to perform processing on the surface to be processed.

Therefore, the portion of the processing liquid that comes into contact with the processing liquid is limited to the surface to be processed of the semiconductor wafer and the inner peripheral surface of the wafer holding ring, so that contamination of the processing liquid by impurities can be prevented. Surface treatment quality can be improved. In addition, the amount of the processing liquid used can be reduced. Then, without transferring the semiconductor wafer from the jig, a plurality of processes such as an etching process and a subsequent rinsing process can be continuously performed, so that the workability can be improved and the work can be performed safely. be able to. Since the surface to be processed of the semiconductor wafer is disposed upward in the processing chamber, it is possible to easily remove bubbles and the like, and it is possible to obtain an advantage that defects caused by bubbles can be eliminated. it can.

At this time, the outer peripheral portion of the semiconductor wafer can be heated by the heating ring provided on the wafer support base (the invention of claim 2). In the case of processing, the temperature distribution in the surface of the semiconductor wafer can be made uniform.

In this case, since the heating ring and the wafer support base are generally made of different materials and, consequently, materials having different coefficients of thermal expansion, the heating ring is not fixedly provided on the wafer support base. The wafer support base may be provided so as to be relatively slidable in accordance with the thermal expansion and contraction of the wafer (the invention of claim 3). Is relatively slid on the wafer support base and absorbed, thereby preventing the occurrence of stress on the semiconductor wafer.

Further, a guide ring having a function of aligning the wafer support base and the wafer holding ring may be provided on the wafer holding ring, and the outer peripheral portion of the packing may be held by the guide ring. (Invention of claim 4). According to this, the wafer support base and the wafer holding ring can be easily aligned by the guide ring, and at the same time, the packing can be held in a stable shape and position.

In this case, the guide ring may be supported by the wafer holding ring with a gap for absorbing relative thermal expansion and contraction between the guide ring and the wafer holding ring. Invention), even when the guide ring thermally expands, the thermal expansion is absorbed by the gap, and the sealing by the packing can be performed stably, and no stress is applied to the semiconductor wafer.

The fastening means is formed by forming a ring-shaped vacuum chamber on the outer periphery of the lower surface of the wafer holding ring and forming a ring on the outer peripheral portion of the upper surface of the wafer support base in correspondence with the vacuum chamber on the holding ring side. A support base side vacuum chamber is formed, between which a connection hole connecting the press ring side vacuum chamber and the support base side vacuum chamber is vertically extended, and the inner circumference of the press ring side vacuum chamber is formed on both upper and lower surfaces. A ring-shaped cylinder having a seal lip for sealing the inner and outer peripheral sides of the vacuum chamber on the inner side and the outer peripheral side, respectively, and the support base side is provided. When both of the vacuum chambers are depressurized, the cylinder is elastic. The wafer holding ring and the wafer support base may be fastened to each other while being deformed to each other (the invention according to claim 6).

According to this, the wafer holding ring and the wafer support base can be fastened to the entire circumference with a uniform force without applying a local stress to the semiconductor wafer. In addition, it is possible to stably fasten the substrate by following the thermal expansion and contraction of the wafer support base.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to the case of performing an immersion type etching process on a semiconductor wafer when manufacturing a sensor chip such as a semiconductor acceleration sensor or a semiconductor pressure sensor will be described below. This will be described with reference to FIGS. In this embodiment, FIG.
To the semiconductor wafer 1 as shown in FIGS.
In this example, the recess 2a of each sensor chip 2 is formed by etching the semiconductor wafer 1. Since the semiconductor wafer 1, the sensor chip 2, and the like are common to those described in the conventional example, a new illustration is omitted. , Code are commonly used.

FIG. 1 shows the entire configuration of a masking pot 21 as a surface treatment apparatus according to this embodiment. As shown in FIGS. 2 and 4 to 6, the masking pot 21 includes a wafer support base 22 for supporting the semiconductor wafer 1 in a mounted state, a heating ring 23 for heating the semiconductor wafer 1, A packing 24 for sealing the outer peripheral edge of the processing surface 1a of the semiconductor wafer 1;
Pressing ring 25 from above, a guide ring 26 for positioning the wafer holding ring 25 and the wafer support base 22 and the like, and fastening the wafer holding ring 25 and the wafer support base 22 together. And a cylinder 27 that constitutes fastening means for this purpose.

The wafer support base 22 is made of a synthetic resin having high heat resistance and corrosion resistance such as Teflon, has an outer diameter sufficiently larger than that of the semiconductor wafer 1, and has a central portion larger than that of the semiconductor wafer 1. It is configured in a thick disk shape having a small diameter circular through hole 22a. On the upper surface, a slightly wider fitting recess 22b into which a guide ring 26 to be described later is fitted is formed in a ring shape so as to be located on the outer peripheral side of the semiconductor wafer 1, and is formed on the outermost peripheral portion. A ring-shaped support base-side vacuum chamber 28 is recessed. Although not shown, a vacuum exhaust hole for exhausting the inside of the support base side vacuum chamber 28 is formed in the wafer support base 22, and this vacuum exhaust hole is connected to a vacuum device such as a vacuum pump (not shown). It is to be connected.

The heating ring 23 is made of a metal having excellent thermal conductivity, high corrosion resistance and mechanical strength, and has a thermal expansion coefficient equivalent to that of the semiconductor wafer 1, for example, nickel. And a flange 23a having an outer diameter equal to the outer diameter of the semiconductor wafer 1 is integrally formed at the upper end thereof.

Further, a mounting portion 23b is provided integrally on the outer peripheral portion of the flange portion 23a so as to rise slightly upward. The heating ring 23 is connected to the wafer support base 22.
Is inserted into the through hole 22a from above, and the flange 23a is provided on the inner peripheral portion of the upper surface of the wafer support base 22 in a state where the semiconductor wafer 1 is mounted on the mounting portion 23b.
Is supported in a mounted state with the surface to be processed 1a as an upper surface.

At this time, the heating ring 23 is thermally connected to a heater (not shown) and transfers the heat to the outer peripheral portion on the lower surface side of the semiconductor wafer 1. At this time, a sliding surface is formed between the lower surface of the flange 23a and the upper surface of the wafer support base 22. As described later, the heating ring 23 (the flange 23a) thermally expands the wafer support base 22. , The wafer support base 22 with shrinkage
It is possible to relatively slide on the top. The lower surface of the semiconductor wafer 1 is communicated with the outside air by the hollow portion of the heating ring 23 and the through hole 22a of the wafer support base 22.

As shown in FIGS. 2 and 3, the packing 24 is made of an elastic material such as rubber having corrosion resistance, and has an inner peripheral shape formed in a ring shape corresponding to the outer peripheral shape of the semiconductor wafer 1. I have. More specifically, the packing 24 has a rib 24a that rises in the vertical direction over the entire outer peripheral portion, and is connected to the inner peripheral edge of the packing 24 in the vertical direction via a connecting portion 24b that extends inward from the rib 24a. The upper lip portion 24c and the lower lip portion 24d are integrally formed. The lower lip portion 24d abuts on the outer peripheral edge of the upper surface of the semiconductor wafer 1 (the outer portion of the portion where the sensor chip 2 is formed).

The wafer holding ring 25 is made of a material having heat resistance and corrosion resistance equivalent to that of the wafer support base 22, and has a substantially cylindrical shape which is relatively short in the vertical direction as shown in FIG. The lower half thereof is bulged in the outer peripheral direction so as to have the same outer diameter as the wafer support base 22. On the lower surface of the wafer holding ring 25, the fitting recess 22b of the wafer support base 22 is provided.
25a whose inner peripheral side is depressed by one step corresponding to the outer peripheral part of
Are formed. A packing pressing portion 25b for pressing the packing 24 is provided on the inner peripheral portion of the lower surface so as to extend toward the inner peripheral side.

Further, on the lower surface side of the wafer holding ring 25, a pin head housing for housing the head portion of the link pin 29 for connection of the guide ring 26 is located slightly inside the step 25a. A hole 25c is formed. At this time, a gap S (shown only in FIG. 2) is provided between the pin head accommodation hole 25c and the link pin 29, and the link pin 29
Is provided so as to be able to move slightly in the radial direction in the pin head accommodating hole 25c. In addition, this pin head accommodation hole 25c is
For example, it is provided at four locations (only one location is shown in the figure for convenience) at equal intervals in the circumferential direction. A ring-shaped holding-ring-side vacuum chamber 30 is formed in the outer periphery of the lower surface of the wafer holding ring 25 so as to correspond to the support base-side vacuum chamber 28.

As shown in FIG. 2, the guide ring 26 is made of a material also having heat resistance and corrosion resistance, and has a substantially rectangular cross section having a size corresponding to the fitting recess 22b of the wafer support base 22. It is formed in the shape of a ring. The inner diameter of the guide ring 26 corresponds to the outer shape of the semiconductor wafer 1 and also has a function of positioning the semiconductor wafer 1.

The lower end edge of the inner peripheral side of the guide ring 26 has an inclined cut portion 26 which is cut in an oblique direction.
a is formed. The height position of the upper end of the inclined cut portion 26a is larger than the depth dimension of the fitting recess 22b. On the inner peripheral upper surface of the guide ring 26, a housing groove 26 b into which the rib 24 a of the packing 24 is inserted at a position slightly entering the outer peripheral side from the inner peripheral edge.
Are formed, and a packing receiving portion 26c which is located at the innermost peripheral portion and receives the lower surface of the connecting portion 24b of the packing 24 is formed. At this time, the accommodation groove 26b
Is configured such that its width is larger than the width of the rib 24a.

Further, at the outer peripheral portion of the guide ring 26, there are four through holes 26d at equal intervals in the circumferential direction (only one is shown in the figure for convenience) through which the link pins 29 pass. And the through hole 2
A connecting concave portion 26e is formed on the lower surface side, which is continuous with 6d, and is located at the lower end of the link pin 29.
The guide ring 26 is provided with a link pin 29 held in a pin head receiving hole 25c of the wafer holding ring 25.
Is inserted into the through hole 26d from above, and the connection recess 26
e, the nut 32 is tightened with the tension rubber 31 interposed at the tip of the link pin 29 so that the link pin 29 is addressed to the lower surface of the wafer holding ring 25 (the inner peripheral side of the step 25a). Attached to

The guide ring 26 is slid relative to the wafer holding ring 25 by the gap S around the link pin 29 with the upper surface thereof being in close contact with the lower surface of the wafer holding ring 25. It is possible. Also, at this time, the ribs 24a of the packing 24 are previously inserted into the accommodation grooves 26b of the guide ring 26, so that the ribs 24a are sandwiched between the guide ring 26 and the wafer holding ring 25. Connection part 24
b is reliably and stably held in a state of being placed on the packing receiving portion 26c.

The wafer holding ring 25 to which the guide ring 26 and the packing 24 are attached is positioned with respect to the wafer support base 22 by fitting the lower part of the guide ring 26 into the fitting recess 22b. It is superimposed on the matching state. At this time, the lower lip portion 24d of the packing 24 comes into contact with the outer peripheral portion of the upper surface of the semiconductor wafer 1 placed on the heating ring 23. In this state, the outer peripheral portion of the lower surface of the wafer press ring 25 (the portion where the pressurizing ring side vacuum chamber 30 is formed) and the outer peripheral portion of the upper surface of the wafer support base 22 (the portion where the support base side vacuum chamber 28 is formed) are vertically moved. And the cylinder 27 is arranged in the gap portion.

The cylinder 27 is formed in a ring shape from an elastic material such as rubber, for example, and has a substantially square cross section as shown in FIG. 2, and has an inner peripheral edge and an outer peripheral edge on the upper surface and a lower surface. Are provided integrally with a seal lip 27a at the inner peripheral edge and the outer peripheral edge, respectively. In this case, the seal lip 27a projecting in a so-called X-shaped cross section in four directions is attached to the wafer holding ring 25 (the wafer support base 2).
2) It has a sufficient reaction force (for example, 5 kg) to lift. In the cylinder 27, eight connection holes 27b penetrating vertically are formed at equal intervals in the circumferential direction, for example (only one is shown in the figure).

In the cylinder 27, two seal lips 27a on the upper surface side hermetically seal the inner peripheral side and the outer peripheral side of the holding ring side vacuum chamber 30 on the lower surface of the wafer holding ring 25, respectively. Seal lips 27a
Are arranged on the upper surface of the wafer support base 22 so as to hermetically seal the inner peripheral side and the outer peripheral side of the support base side vacuum chamber 28, respectively. At this time, the cylinder 27
Between the inner peripheral surface and the outer peripheral surface of the guide ring 26,
A support ring 33 for holding the gap is provided.

In this state, the vacuum device is driven, and the air in the support base side vacuum chamber 28 is exhausted through a vacuum exhaust hole provided on the wafer support base 22 side, thereby forming a vacuum (reduced pressure) state. Then, the air in the holding ring side vacuum chamber 30 is also exhausted through the connection hole 27b to be in a vacuum (decompressed) state, and the cylinder 27 is elastically deformed while the wafer holding ring 25 and the wafer support base 22 are in contact with each other. Are pulled in a direction in which they are attracted to each other, so that the entire circumference is fastened with an equal force.

Therefore, both the vacuum chambers 28 and 30 and the cylinder 2
7. The fastening means is constituted by a vacuum device or the like.
The fastening force at this time is, for example, about 60 kg. In this fastening state, the packing holding portion 25b of the wafer holding ring 25 acts as a force for pressing the packing 24 downward to seal the semiconductor wafer 1, and in this case, for example, the sealing length of the semiconductor wafer 1 is 1.4 kg /. cm sealing force is obtained.

As a result, the masking pot 21 is configured to hold the semiconductor wafer 1. The masking pot 21 contains the semiconductor wafer 1
The surface to be processed 1a is an inner bottom surface, and the inner peripheral wall of the wafer holding ring 25 is an inner wall.
Thus, a wafer processing chamber 35 for accommodating (see FIG. 4) is formed. At this time, the masking pot 21 functions as a masking jig for holding the semiconductor wafer 1 and also functions as a processing container.

Next, the operation of the above configuration will be described with reference to FIGS. Processed surface 1 of semiconductor wafer 1
As shown in FIG. 11, a is covered with a mask 3 except for a portion where the concave portion 2a is formed. In this state, the surface 1a to be processed is immersed in a processing solution 34 (an etching solution such as potassium hydroxide), and An etching process for forming the concave portion 2a of the sensor chip 2 is performed. Incidentally, as shown in FIG.
In some cases, the etching process forms the groove 4 for chip separation at the same time. Further, as shown exaggeratedly in FIG. 16, the semiconductor wafer 1 may be warped in the steps up to that time.

In performing the etching process on the semiconductor wafer 1, an operation for accommodating the semiconductor wafer 1 in the masking pot 21 configured as described above is performed. In this operation, first, the semiconductor wafer 1 is placed on the heating ring 23 set on the wafer support base 22 with the surface to be processed 1a as the upper surface. Next, the wafer holding ring 25 on which the guide ring 26 and the packing 24 are mounted is moved to the cylinder 27 at the outer peripheral portion.
The guide ring 26 is overlapped so that the lower portion of the guide ring 26 is fitted into the fitting recess 22b while being sandwiched between the two.

Subsequently, the vacuum device is driven to fasten the wafer holding ring 25 and the wafer support base 22 to form the masking pot 21. As a result, as shown in FIG. 1 and the like, the semiconductor wafer 1 is supported by the masking pot 21 in a state where the outer peripheral edge of the upper surface is sealed by the packing 24 and the portion other than the processing target surface 1a is masked. Thus, a wafer processing chamber 35 is formed in which the processing surface 1a of the semiconductor wafer 1 is an inner bottom surface and the inner peripheral surface of the wafer press ring 25 is an inner wall.

At this time, as described above, since the entire circumference is fastened with an equal force, an equal force acts only on the outer peripheral edge of the semiconductor wafer 1 over the entire circumference, and the semiconductor wafer 1 is locally stressed. Does not act, and even if the semiconductor wafer 1 is warped, no force is applied to correct it, and the semiconductor wafer 1 is held in a stable state. Also,
The above-described wafer holding ring 25 and wafer support base 22
When they are fastened, they can be easily aligned by the guide ring 26.

In the etching process, first,
A preheating step of heating the outer peripheral portion of the semiconductor wafer 1 by raising the temperature of the heating ring 23 to, for example, about 120 ° C. is performed. In this preheating step, the temperature of the wafer support base 22 gradually increases.

After the preheating step, as shown in FIG. 4, an etching step in which an etching solution 34 is directly charged into the wafer processing chamber 35 and left for a predetermined time is executed. By this etching step, the surface 1 to be processed of the semiconductor wafer 1 is
a is immersed in the etching solution, the portion of the processing surface 1a where the mask 3 does not exist is etched, and the concave portion 2a is formed. The etching liquid 34 is, for example, a high temperature of 110 ° C. or more. Since the outer peripheral side of the semiconductor wafer 1 is heated by the preheating, the temperature distribution in the surface of the semiconductor wafer 1 is made uniform. be able to. Further, at the beginning of the etching step, first, the temperature of the surface 1a to be processed of the semiconductor wafer 1 and the temperature of the wafer pressing ring 25 rise, and thereafter, as the time elapses, the entire temperature becomes stable.

At this time, the portions that are in contact with the etching solution 34 are limited to the processed surface 1 a of the semiconductor wafer 1, the inner peripheral surface of the wafer holding ring 25, and the inner peripheral portion of the packing 24. Even if an impurity adheres to the side or the wafer support base 22, the impurity does not come into contact with the etching solution 34, so that contamination of the etching solution 34 by the impurity can be prevented. In addition, since the etching liquid 34 only needs to fill a relatively small space in the wafer processing chamber 35, the amount of the etching liquid 34 used can be reduced. Further, since the processing surface 1a of the semiconductor wafer 1 is arranged upward in the wafer processing chamber 35, the bubbles and the like generated on the processing surface 1a can be easily separated, and the occurrence of defects due to the bubbles can be reduced. Can be eliminated.

When the etching process of a predetermined thickness is completed,
The heating of the heating ring 23 is stopped to lower the temperature of the etching solution 34. When the etching solution 34 is KOH, the etching is substantially stopped by the temperature drop. Then, use a masking pot 2 with an ejector, etc.
The concentration of the etching solution 34 is diluted by sucking and discharging the etching solution 34 in 1 and further injecting pure water.
When the etching liquid 34 is an acid such as hydrofluoric acid, the temperature dependence of the etching action is small. Also,
In this case, the masking pot 21 is turned upside down as shown in FIG.
It is also possible to execute the step of pure water cleaning of the processing target surface 1a of the semiconductor wafer 1 by injecting 7.

Thereafter, a step of drying the semiconductor wafer 1 is performed, and the semiconductor wafer 1 is taken out from the masking pot 21. The removal of the semiconductor wafer 1
The vacuum in the support base side vacuum chamber 28 and the press ring side vacuum chamber 30 is gradually released to release the fastening between the wafer press ring 25 and the wafer support base 22, and the wafer press ring 2
5 is removed from the wafer support base 22. The removal of this semiconductor wafer 1
This can be performed without applying a stress such as a twist to the body.

As described above, the etching process and the pure water cleaning process for the semiconductor wafer 1 can be continuously performed while the semiconductor wafer 1 is held by the masking pot 21 without moving between the tanks. The work of removing the wax 5 as in the related art is not required.
Thereby, the handling of the fragile semiconductor wafer 1 is facilitated, and the workability can be improved. In addition, a problem in which the reaction progresses while the semiconductor wafer 1 is moving and the etching variation occurs, is also prevented. be able to. Also, the masking pot 21 itself is small, lightweight and easy to handle, and the operation can be performed safely.

In the above-described steps of preheating, etching, and cleaning with pure water, the masking pot 2
Each part is heated or cooled to thermally expand and contract. If the thermal expansion or contraction acts as a stress on the semiconductor wafer 1, there is a possibility that the semiconductor wafer 1 may be cracked, especially when the groove 4 for separating the chips is formed. It is also conceivable that the sealing performance of the packing 24 is deteriorated due to the expansion and contraction.

However, the masking pot 2 of this embodiment
In FIG. 1, as shown in FIG. 6, such a thermal expansion and contraction does not act as a stress on the semiconductor wafer 1, and a good sealing property is always ensured by the packing 24. That is, as shown in FIG.
In the preheating step, the semiconductor wafer 1 and the wafer support base 22 are heated by the heating ring 23 so that the wafer support base 22 having a large coefficient of thermal expansion expands to the outer peripheral side as shown by a thick arrow in the figure. become.

At this time, the heating ring 23 slides relatively on the upper surface of the wafer support base 22. Further, since the heating ring 23 has the same coefficient of thermal expansion as the semiconductor wafer 1, the heating ring 23 The semiconductor wafer 1 is protected, and no stress acts on the semiconductor wafer 1.
Further, the thermal expansion of the wafer support base 22 is allowed by the inclined cut portion 26 a of the guide ring 26. In addition, by the seal lip 27a of the cylinder 27,
Needless to say, airtightness in the support base side vacuum chamber 28 is ensured.

Next, in the initial stage of the etching process in which the etching solution 34 is introduced into the wafer processing chamber 35, the etching solution 34 shown in FIG.
As shown in (b), the temperature of the wafer holding ring 25 becomes high, and the wafer holding ring 25 expands toward the outer peripheral side as shown by a thick arrow in the figure. This expansion is accompanied by a dimensional change of, for example, 1.5 mm. The thermal expansion of the wafer holding ring 25 is allowed (absorbed) by the fact that the wafer holding ring 25 can move relative to the guide ring 26 by a gap S around the link pin 29.

The packing 24 has an upper lip portion 24.
a is elastically inclined to the outer peripheral side, but the lower lip portion 2
The sealing position of the semiconductor wafer 1 by 4d does not change. As a result, no stress acts on the semiconductor wafer 1 and the sealability of the packing 24 is also ensured. At this time, the seal lip 27a of the cylinder 27 ensures airtightness in the holding ring side vacuum chamber 30.

Then, during the etching step, FIG.
As shown in (c), the temperature of the guide ring 26 continues to be high, and the guide ring 26 expands toward the outer peripheral side as shown by a thick arrow in the figure. This expansion is permitted (absorbed) by the gap S between the link pins 29 of the wafer holding ring 25 and the gap already formed between the fitting recess 22b of the wafer support base 22 and stress on the semiconductor wafer 1 Does not work. At this time, the packing 24 moves relative to the inner peripheral side in the accommodation groove 26b of the guide ring 26, so that a good sealing property is secured without changing the sealing position with respect to the semiconductor wafer 1. You.

Further, at the start of the pure water cleaning step,
As shown in (d), the low-temperature pure water causes the wafer holding ring 25 to contract (return to the original position) inward as shown by the thick arrow in the drawing. Also at this time, the contraction movement of the wafer holding ring 25 with respect to the guide ring 26 is allowed (absorbed) by the gap S between the link pins 29, and no stress acts on the semiconductor wafer 1.
In addition, the inclination of the upper lip portion 24c of the packing 24 also returns, and good sealing properties are secured. Thereafter, although not shown, the whole is cooled and returns to the original state. In this case, too, the semiconductor wafer 1 is not stressed, and the sealability of the packing 24 is ensured.

As described above, according to the present embodiment, the following excellent effects can be obtained. That is, the semiconductor wafer 1 can be stably held (masked) by the masking pot 21 without locally acting mechanical stress. In this embodiment, even if the semiconductor wafer 1 has a large diameter, the semiconductor wafer 1 in which the groove 4 is formed, or the semiconductor wafer 1 in which the warp is generated, the etching process can be performed without generating the crack. Incidentally, in the present embodiment, the work of setting the semiconductor wafer 1 having a large diameter (150 mmφ, 300 μm thickness) in the masking pot 21 can be automated.

The semiconductor wafer 1 can be etched by directly introducing the etching solution 34 into the wafer processing chamber 35 formed in the masking pot 21, thereby preventing the etching solution 34 from being contaminated. Quality and the quality of semiconductor wafers 1
Quality can be prevented by the reaction during the movement of
High quality etching can be performed.

Moreover, the handling of the semiconductor wafer 1 and the masking pot 21 itself are easy, and a plurality of processing steps can be continuously performed using the masking pot 21, thereby greatly improving workability. Can be planned. Further, the processing cost can be reduced, and the safety of the operation is high. Further, in this embodiment, in particular, it is possible to prevent the stress from acting on the semiconductor wafer 1 even if there is a thermal expansion and contraction of each part constituting the masking pot 21 and to secure a good sealing property by the packing 24. Can be done.

In the present invention, there is an advantage that the degree of freedom in designing the outer shape of the wafer support base and the wafer holding ring is high. For example, the following modifications are possible. That is, in a masking pot 41 according to another embodiment of the present invention shown in FIG. 7, holes 42a and 43a for arranging electrodes are formed in a wafer support base 42 and a heating ring 43, and the portion of the semiconductor wafer 1 An electrode 44 for electrochemical stop etching, which is electrically connected to the back surface, is provided. In addition, the heating ring 4
A diaphragm thickness measurement sensor 45 is provided on the inner peripheral portion of the sensor 3.

FIG. 8 shows another embodiment of the present invention, in which a plating process is performed as a surface treatment of the semiconductor wafer 1. In the masking pot 51 according to this embodiment, the semiconductor wafer 1 is directly mounted on the wafer support base 52 without providing a heating ring. The wafer holding ring 53 is provided with a packing 54 for sealing the semiconductor wafer 1 and a cathode electrode 55 electrically connected to the semiconductor wafer 1.

A plating solution 57 is contained in a wafer processing chamber 56 formed in the masking pot 51.
An anode electrode 59 disposed in a plating solution 57 is supported on a lid 58 that closes an opening on the upper surface of the wafer holding ring 53. The cathode electrode 55
A direct-current power supply 60 is connected between the semiconductor wafer 1 and the anode electrode 59, whereby the surface 1a to be processed of the semiconductor wafer 1 is plated.

In addition, the present invention is not limited to the above-described embodiments. For example, the shape and structure of the packing and cylinder, and also the material and structure of the wafer support base and the wafer holding ring may be variously modified. Is possible,
In addition to manufacturing sensor chips for acceleration sensors and pressure sensors, the present invention can be applied to general processing of semiconductor wafers, and the present invention can be implemented with appropriate modifications without departing from the gist of the present invention. It is.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, and is a longitudinal sectional view showing an entire configuration of a masking pot.

FIG. 2 is an enlarged longitudinal sectional view showing a fastening portion between a wafer holding ring and a wafer support base.

FIG. 3 is a plan view (a) of the packing and a perspective view (b) showing a partial cross section.

FIG. 4 is a longitudinal sectional view showing a state of an etching step.

FIG. 5 is a longitudinal sectional view showing a state of a pure water cleaning step.

FIG. 6 is a longitudinal sectional view of a main part showing a state of thermal expansion and contraction of each part.

FIG. 7 is a view corresponding to FIG. 1, showing another embodiment of the present invention.

FIG. 8 is a diagram corresponding to FIG. 1, showing another embodiment different from the first embodiment;

FIG. 9 is a schematic plan view of a semiconductor wafer.

10A is a plan view showing the shape of one acceleration sensor chip, and FIG.

FIG. 11 is a partial longitudinal sectional view showing a state where a concave portion for a sensor chip is formed in a semiconductor wafer.

FIGS. 12A and 12B show a conventional example, and are a longitudinal sectional view (a) and a side view (b) showing a state where a semiconductor wafer is held by a masking jig.

FIG. 13 is a view showing a process of etching a semiconductor wafer;

FIG. 14 is a diagram corresponding to FIG. 12, showing another conventional example.

FIG. 15 is an enlarged longitudinal sectional view of a main part showing another different conventional example.

FIG. 16 is an exaggerated view showing how a semiconductor wafer is warped.

[Explanation of symbols]

In the drawings, 1 is a semiconductor wafer, 1a is a surface to be processed, 21, 4
1, 51 are masking pots (surface treatment devices), 22,
42 and 52 are wafer support bases, 23 and 43 are heating rings, 24 and 54 are packings, 25 and 53 are wafer holding rings, 26 is a guide ring, 27 is a cylinder, 27a is a seal lip, 27b is a communication hole, and 28 is a communication hole. The support base side vacuum chamber, 30 is a holding ring side vacuum chamber, 33 is a support ring, 34 is an etchant, 35 and 56 are wafer processing chambers,
S indicates a gap.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Keikichi Takada 1-1-1 Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (reference) 5F031 CA02 HA28 MA24 5F043 DD07 EE35 GG10

Claims (6)

[Claims] 1. A wafer support base for supporting a semiconductor wafer in a mounted state with its surface to be processed as an upper surface, a packing abutting on an outer peripheral portion of an upper surface of the semiconductor wafer, and A cylindrical wafer holding ring for sealing an outer peripheral edge of the semiconductor wafer; fastening means for fastening the wafer holding ring and the wafer support base to the entire circumference with a uniform force; and the wafer holding ring and the wafer. A surface processing apparatus for a semiconductor wafer, wherein a wafer processing chamber having a surface to be processed of the semiconductor wafer as an inner bottom surface and an inner peripheral surface of the wafer pressing ring as an inner wall is configured in a state of being fastened to a support base. 2. The semiconductor wafer surface treatment apparatus according to claim 1, wherein the wafer support base supports the semiconductor wafer via a heating ring that heats an outer peripheral portion of the semiconductor wafer. 3. The heating ring according to claim 2, wherein the heating ring is provided so as to be relatively slidable on the wafer support base in accordance with thermal expansion and contraction of the wafer support base. Semiconductor wafer surface treatment apparatus. 4. A guide ring having an alignment function between the wafer support base and the wafer press ring is provided between the wafer support base and the wafer press ring, and the outer peripheral portion of the packing is provided by the guide ring. 4. The semiconductor wafer surface treatment apparatus according to claim 1, wherein the semiconductor wafer is held. 5. The wafer holding ring according to claim 1, wherein said guide ring is supported by said wafer holding ring with a gap for absorbing a relative thermal expansion and contraction between said guide ring and said wafer holding ring. 5. The apparatus for treating a surface of a semiconductor wafer according to claim 4. 6. The fastening means corresponds to a ring-shaped vacuum chamber formed on an outer peripheral portion of a lower surface of the wafer holding ring and a vacuum chamber formed on an outer peripheral portion of an upper surface of the wafer support base. The ring-shaped support base side vacuum chamber formed by the above, while making a ring-shaped interposed between the lower peripheral part of the wafer holding ring and the outer peripheral part of the upper surface of the wafer support base, the holding ring side vacuum chamber A connecting hole for connecting to the support base side vacuum chamber is vertically extended, and the inner and outer peripheral sides of the holding ring side vacuum chamber and the inner and outer peripheral sides of the support base side vacuum chamber are sealed on both upper and lower surfaces, respectively. And a cylinder having a sealing lip. When the vacuum chambers are depressurized, the cylinder is elastically deformed, and the wafer holding ring and the wafer support base are mutually moved. Surface treatment apparatus for a semiconductor wafer according to any one of claims 1 to 5, characterized in that for fastening to gather.