JP2001142783A - Electric and electronic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit by which writing into a storage device is disabled at the side of a user after energizing the circuit once. SOLUTION: An integrated circuit 10C is provided with a flash memory 46 which is operated as a storage device being writing and erasing possible when a read/write enable port R/W is in a high level. When a power source Vdd is impressed on an external power source input terminal 24, the fuse 18 of a poly-silicone wiring pattern is blown in a setting time by the output of a step-up regulator circuit 16. After the fuse 18 is blown, the input of a buffer 20 is fixed to be a low level through a resistor 21. Then the read/write enable port R/W of the flash memory 46, which is the output of an AND circuit 40, is fixed to be the low level and the flash memory 46 becomes exclusive for reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, LS
An electric / electronic circuit device suitable for application to an integrated circuit such as an I (large scale integrated circuit) and capable of effectively preventing hardware modification of electric / electronic products and tampering and secondary use of software. About.

[0002]

2. Description of the Related Art From the viewpoints of foolproof and fail-safe of electric and electronic products, it is desirable that modification of hardware and software of electric and electronic products cannot be performed by a user.

Conventionally, in order to prevent the modification of the hardware of these electric / electronic products and the falsification and secondary use of the software, special screws are used for the housing of the products, or the software is not used. Some measures have been taken to prevent tampering and secondary use.

[0004] However, although these measures have a certain effect of preventing the modification of the hardware of electric and electronic products and the falsification and secondary use of the software,
Its prevention effect is not enough.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has a simple structure and is capable of modifying hardware of electric / electronic products, falsifying software, and secondary use. It is an object of the present invention to provide an electric / electronic circuit device capable of physically preventing the like.

Another object of the present invention is to provide an electric / electronic circuit device that, when used once by a user, makes secondary use impossible in the field.

[0007]

According to the electric / electronic circuit device of the present invention, when a voltage is applied to a specific terminal, the logical output of the logical output setting circuit is irreversible to a constant logical output based on the applied voltage. (The invention described in claim 1).

By using the fixed logic output of the logic output setting circuit, for example, the operation of a logic element connected to the output side of the logic output setting circuit can be fixed.

Here, the logic output setting circuit may include a cutoff element that is cut off irreversibly based on a voltage applied to a specific terminal.
Described invention).

In this case, by providing the booster circuit between the specific terminal and the cutoff element, the cutoff element is cut off by the output of the booster circuit even if the voltage applied to the specific terminal is relatively low. Can be facilitated (the invention according to claim 3).

Since the booster circuit is driven by a power-on reset circuit that operates for a certain period of time after a voltage is applied to a specific terminal, the power consumption of the booster circuit can be kept for a certain period. Preferred (the invention according to claim 4).

According to the third aspect of the present invention, the booster circuit is connected to a power consumption limiting circuit which detects that the cutoff element is shut off and reduces or eliminates the power consumption of the booster circuit. After the cutoff element is cut off, the power consumption of the electric / electronic circuit device can be reduced (the invention according to claim 5).

According to a third aspect of the present invention, the shut-off element is cut off by an output of a booster circuit that has been in an operation state for a predetermined period by a power-on reset circuit from when a voltage is applied to a specific terminal. In the booster circuit,
By detecting that the cutoff element has been cut off and connecting a power consumption limiting circuit that reduces or eliminates the power consumption of the booster circuit, in a normal state after the cutoff element is cut off, Power consumption can be reduced or eliminated (the invention according to claim 6).

In the invention according to claims 2 to 6, the electric power
When the electronic circuit device is constituted by an integrated circuit, the blocking element can be integrally formed by a silicon wiring pattern (the invention according to claim 7).

Further, when the specific terminal is used as a power input terminal of the electric / electronic circuit device, for example, when the user uses the electric / electronic circuit device for the first time, the logical output circuit of the logical output circuit is used. Is fixed (claim 8
Described invention).

Further, the electric / electronic circuit device of the present invention comprises:
A logic output setting circuit whose logic output is irreversibly fixed to a constant logic output when a voltage is applied to a specific external terminal, and an electrical writing / erasing electrically connected to the output side of the logic output setting circuit. And a possible storage device (the invention according to claim 9).

According to the present invention, there is obtained a possibility that the operation of the electrically rewritable storage device can be defined by the logical output of the logical output setting circuit.

Specifically, an external terminal for read / write control is connected to a read / write control input of the storage device, and before a voltage is applied to a specific external terminal, the external terminal for read / write control is used by using the external terminal for read / write control. By allowing read / write control of the memory device, writing and erasing of the storage device can be freely performed until the logical output setting circuit is fixed to a certain logical output, and after the logical output setting circuit is fixed to a certain logical output, writing and erasing are not performed. It can be used as much as possible (the invention according to claim 10).

Alternatively, specifically, a read / write control internal terminal is connected to a read / write control input of the storage device, and before a voltage is applied to a specific external terminal, the read / write control internal terminal is used. By enabling read / write control of the storage device, for example, the manufacturer of the electric / electronic circuit device can enable reuse (writing / erasing) any number of times (the invention according to claim 11).

That is, when a voltage is actually applied to a specific external terminal, the storage device can be used only as a read-only memory by the fixed constant logic output of the logic output setting circuit. Described invention).

In the invention according to any one of the ninth to twelfth aspects, the logic output setting circuit is configured to include a shutoff element that is irreversibly shut off based on a voltage applied to a specific external terminal. (Invention of claim 13).

Also in this case, by providing the booster circuit between the specific external terminal and the cutoff element, even if the voltage applied to the specific external terminal is relatively low, the booster circuit can be compared. There is a possibility that the shut-off element can be easily shut off by a high-voltage output (the invention according to claim 14).

Further, in the invention according to the fourteenth aspect, the booster circuit is driven by a power-on reset circuit that operates for a certain period from the time when a voltage is applied to a specific external terminal, thereby increasing the booster circuit. This is preferable because the power consumption of the circuit can be limited to a certain period.
Described invention).

Further, in the invention according to claim 14, the booster circuit is connected to a power consumption limiting circuit which detects that the cutoff element is shut off and reduces or eliminates the power consumption of the booster circuit. Thus, it is possible to reduce the power consumption of the electric / electronic circuit device after the cutoff element is cut off (the invention according to claim 16).

Further, in the invention according to claim 14,
The shut-off element is cut off by the output of the booster circuit that has been operated for a certain period of time by the power-on reset circuit from the time when a voltage is applied to a specific external terminal. Detecting that the power consumption of the booster circuit is reduced or eliminated by connecting the power consumption limiting circuit, the power consumption of the booster circuit can be reduced or reduced in the normal state after the cutoff element is shut off. It can be eliminated (the invention according to claim 17).

In the invention according to claims 13 to 17, when the electric / electronic circuit device is constituted by an integrated circuit,
The blocking element can be formed by a silicon wiring pattern (the invention according to claim 18).

According to the ninth to eighteenth aspects of the present invention, the specific external terminal is used as a power input terminal of the electric / electronic circuit device so that, for example, when the user once uses it,
Since the logic state of the logic output circuit is fixed, for example,
Secondary use in the field becomes impossible (the invention according to claim 19).

Further, the electric / electronic circuit device of the present invention irreversibly converts the logical output of the logical output setting circuit to a constant logical output by supplying a current instead of applying a voltage to a specific terminal. It can be configured to be fixed (the invention according to claim 20).

Similarly, in the electric / electronic circuit device according to the present invention, the logic output is fixed irreversibly to a constant logic output by supplying a current instead of applying a voltage to a specific external terminal. The present invention may be configured to include a logical output setting circuit and an electrically writable and erasable storage device connected to the output side of the logical output setting circuit (the invention according to claim 21).

[0030]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an integrated circuit (IC) such as an LSI to which an embodiment of an electric / electronic circuit device according to the present invention is applied.
10 shows the configuration of FIG. The integrated circuit 10 has a configuration in which an IC chip 14 basically made of a silicon wafer is mounted in a plastic package 12.

On the IC chip 14, a step-up regulator circuit (hereinafter, referred to as an SUR circuit) 16 is a booster circuit for boosting a supplied voltage to a desired high voltage.
And a fuse 18 which is a blocking element connected in series to the SUR circuit 16, a buffer 20 connected in series to the fuse 18, and a common contact between the fuse 18 and the buffer 20 and a ground (ground). Resistance value is R
(Here, the resistor 21 of R = 100 [Ω]) is integrated.

In the integrated circuit 10, the fuse 18, the resistor 21, and the buffer 20 constitute a logical output setting circuit 34.

The integrated circuits 10C, 10C, 10
D, 10E, 10F, 10G, and electric / electronic circuit 1
In 0A and 10B as well, the fuse 18, the resistor 21, and the buffer 20 form a logical output setting circuit 34.

In the following description, the input impedances (input resistances) of the SUR circuit 16 and the buffer 20 are infinite, and the output impedances (output resistances) are zero values, respectively, for easy understanding. And

The SUR circuit 16 basically includes an oscillator, a transformer connected thereto, a smoothing circuit connected to the transformer to output a direct current, and an output of the smoothing circuit returned to the oscillator. The switching regulator is provided with a feedback circuit for adjusting the oscillation intensity.

The input terminal of the SUR circuit 16 is connected to a bonding pad (hereinafter simply referred to as a pad or a terminal) 22 as a terminal, and this pad 22 is specified via a bonding wire such as a gold wire or an aluminum wire. Is connected to an external power supply input terminal 24 which is a terminal of In this embodiment, a voltage Vdd (also referred to as a power supply Vdd) externally applied to the external power supply input terminal 24 is, for example, Vdd = + 3 [V].

In the integrated circuit 10 shown in FIG.
The R circuit 16 is designed to have a gain of four times, and the voltage Vdd = + 3 [V] applied to the input node is changed to +12
The voltage is raised to the voltage [V] and generated at the output node.

When the input voltage is a low level L voltage of zero [V], the buffer 20 generates a low level L (L = 0 [V]) as a logical output, and the input voltage is, for example, +2. When the voltage is a high level voltage of 1 [V] or more, a high level H (H = + 3
[V]).

The ground of the IC chip 14 is connected to an external ground terminal 32 via a pad 30 as a ground terminal and a bonding wire.

In each circuit described below,
Voltage (power supply) of the buffer 20 and a logic circuit (not shown)
The symbols of Vdd and the ground are omitted in principle because they are complicated.

The integrated circuit 10 of this embodiment is basically configured as described above.

FIG. 2 shows a specific example of the configuration of the fuse 18 as a blocking element. The fuse 18 includes a polysilicon wiring pattern 18p having a small line width.
The line width Wf, the length Lf, and the thickness are determined so that when a certain amount of current or more flows, the wire is melted and disconnected (melted or interrupted). In this embodiment, the fusing current (also referred to as interrupting current) If is set and processed so that If = 120 [mA].

In the integrated circuit 10 of FIG. 1, as described above, the fuse 18, the resistor 21, and the buffer 20 are used.
Constitutes the logical output setting circuit 34. Various logic circuits can be connected to the output terminal of the buffer 20, which is the output stage of the logic output setting circuit.

As shown in FIG. 3, an external power supply input terminal 24, which is a specific terminal or a specific external terminal, and an external ground terminal 3,
2 and an external DC power supply 38 having a voltage Vdd = + 3 [V]
Are connected, the external power input terminal 24 and the terminal 2
2 (see FIG. 1), a voltage Vdd = + 3 [V] is applied to the input terminal of the SUR circuit 16, and a boosted voltage +12 [V] that is four times the voltage is generated at the output side of the SUR circuit 16.

As a result, a current I = 12 [V] ÷ 100 [Ω] = 120 [mA] = If obtained by dividing the boosted voltage +12 [V] by the resistance value R of the resistor 21 is applied to the fuse 18.
Flows, and the fuse 18 is blown.

In this case, the external DC power supply 38 of the voltage Vdd
Is supplied from the buffer 20 to the high level H (H = + 3) until the fuse 18 is blown.
[V]) is output, but when the fuse 18 is blown, the terminals of the fuse 18 are opened, and the input of the buffer 20 is fixed to the ground level, that is, the low level L through the resistor 21. Therefore, the output level of the buffer 20 is permanently fixed to the low level L (L = 0 [V]) after the fuse 18 is blown.

In other words, the integrated circuit 10 according to this embodiment is irreversibly interrupted based on the voltage Vdd applied to the external power supply input terminal 24 which is a specific terminal (specific external terminal). A fuse 18 which is an element, and when the fuse 18 is cut off, the buffer 20
, The logical output of the logical output setting circuit 34 is fixed irreversibly to a constant logical output, in this case, a low level L.

When the integrated circuit 10 thus configured is supplied to the user in the field from a maker or a factory, for example, when the user first energizes the integrated circuit 10, in other words, the user once uses the integrated circuit 10. Then, the logic state of the logic circuit (not shown) connected to the output side of the buffer 20 is physically fixed by the fixed logic output of the buffer 20 constituting the logic output setting circuit 34.

Therefore, the integrated circuit 10 configured as described above has a function of preventing the use of the logic circuit connected to the output side of the buffer 20 on the user side, that is, the so-called secondary use.

Although the example shown in FIG. 1 is applied to the integrated circuit 10 as an electric / electronic circuit device, the present invention is not limited to the integrated circuit 10 but is applied to an electric / electronic circuit constituted by discrete components. It can also be applied to devices.

Although the fuse 18 is blown by using the SUR circuit 16 in the example of FIG. 1, the fuse 18 is blown directly by only the external DC power supply (voltage source) 38 as shown in FIG. The configuration of the electronic circuit device 10A is also possible, and as shown in FIG.
It is also possible to adopt a configuration like the electric / electronic circuit device 10B that is directly blown by the external DC current source 39. Note that the electric and electronic circuit devices 10A of FIGS.
In FIG. 10B, to avoid complication and to facilitate understanding, components corresponding to those shown in the integrated circuit 10 of FIG. 1 are denoted by the same reference numerals. 5 example of electricity
In the electronic circuit device 10B, a current booster may be provided between the external power input terminal 24 and the fuse 18.

Hereinafter, in the circuits or devices described with reference to the drawings, the same or corresponding components as those shown in the circuits or devices described with reference to the drawings preceding the drawings are denoted by the same reference numerals. And a detailed description thereof will be omitted.

FIG. 6 shows a virtual integrated circuit 1 for explaining the operation.
5 shows the configuration of OC.

In this integrated circuit 10C, the semiconductor chip 1
The output of the buffer 20 of the logical output setting circuit 34 constituting 4C is connected to one input node of an AND circuit (AND circuit) 40, and the other input node of the AND circuit 40 is
It is connected to an external terminal 44 of the plastic package 12 via a bonding pad 42. The output of the AND circuit 40 is a read / write (read / write) enable port R / which is a read / write control input of a flash memory 46, which is a storage device capable of electrically writing and erasing.
Connected to W.

The address port, data port and other control ports of the flash memory 46 include:
The CPU (central processing unit) is connected via an address bus, a data bus and a control bus (not shown)
t) and / or DMA (direct memory access)
IC is connected.

In the virtual integrated circuit 10C shown in FIG. 6, when a logical level (high level) H is supplied to the read / write enable port R / W of the flash memory 46, writing to the flash memory 46 is performed. When a logical level (low level) L is supplied, the flash memory 46 enters a read mode and functions as a read-only memory.

When it is assumed that the output level of buffer 20 is virtually at high level H, one of the input nodes of AND circuit 40 is at high level H.
The read / write (read / write) command signal R / W supplied to the external terminal 44 of 2C
A command signal for selecting a write mode or a read mode for the flash memory 46 via the other input node of 0. At this time, the external terminal 44 functions as an external write / read enable terminal (external terminal for read / write control).

As described above, when the external DC power supply 38 of voltage Vdd = + 3 [V] is connected between the external power supply input terminal 24 and the external ground terminal 32, which are external terminals, the SUR circuit 16 The fuse 18 is blown by the output high voltage, and one input node of the AND circuit 40 connected to the output side of the buffer 20 is irreversibly fixed to the low level L. Therefore, the fuse 18 is connected to the output terminal of the AND circuit 40. The read / write enable port R / W of the flash memory 46 is fixed to the read mode. From now on,
The read / write command signal R / W supplied to the read / write control external terminal 44 becomes invalid.

The integrated circuit 10 having such a circuit configuration
In C, before a voltage is applied to the external power supply input terminal 24 which is a specific external terminal, the output of the buffer 20 is supplied to the read / write control external terminal 44 on condition that the output of the buffer 20 can be virtually set to a high level H. The read / write control to the flash memory 46 can be performed using the read / write command signal R / W. However, once the external DC power supply 38 is connected to the external power supply input terminal 24, the fuse 18 is blown by the voltage Vdd. Is done. When the fuse 18 is blown, the logical output of the logical output setting circuit 34 is irreversibly fixed to the low level L, and the rewriting to the flash memory 46 cannot be performed again. Thereafter, the flash memory 46 can be used only as a read-only memory.

Incidentally, in the virtual integrated circuit 10C shown in FIG. 6, the external DC power supply 3 is once connected between the external power supply input terminal 24 and the external ground terminal 32 of the package 12C.
8 is connected, writing to the flash memory 46 cannot be performed again. Therefore, at the time of initial writing at a factory or the like,
It is necessary to provide a special writing structure that is invisible to the user.

Therefore, at the stage of the wafer before assembling into a package, an internal pad for a probe is provided at the read / write enable port R / W of the flash memory 46 connected to the output node of the AND circuit 40.
Further, it is conceivable to perform writing control by providing an internal pad for supplying power only to the flash memory 46. However, in the final product state of the so-called semiconductor package 12 in an assembled state, It is considered that the initial writing control can be performed by using the method described above, whereby the productivity is higher.

FIG. 7 shows a configuration of an integrated circuit 10D that enables the control of the initial writing even after packaging by the external terminal 50 for read / write control.

That is, in this integrated circuit 10D, a semiconductor switch 52 having one contact and two contacts is provided between the SUR circuit 16 and the fuse 18 in the semiconductor chip 14D, and the common contact 52a to which the movable contact is connected is connected to the fuse 18D. , One fixed contact 52 b is connected to the output of the SUR circuit 16, and the other fixed contact 52 c is connected to the pad 22 connected to the external power input terminal 24. Further, a switching control terminal 52d for switching the common contact 52a of the switch 52 is connected to a pad 54 as an internal terminal for read / write control.
The external read / write control external terminal 50 is connected by wire bonding. Note that a pull-down resistor 56 having a resistance value of 100 [kΩ] is provided between a common connection point between the switching control terminal 52d of the switch 52 and the pad 54 and the ground.
Is connected.

The switch 52 is connected to the switching control terminal 5
When the high level H is applied to 2d, the common contact 52a and the fixed contact 52c are connected, and the switching control terminal 5
When 2d is at the low level L, the common contact 52
a and the fixed contact 52b on the output side of the SUR circuit 16 are connected to each other.

The integrated circuit 10D thus configured is
As described in detail below, before packaging the IC chip 14D, the pads 2 each of which is an internal terminal.
Initial writing is possible using 2, 30, 42, and 54, and after the packaging of the IC chip 14D, initial writing is possible using the terminals 24, 32, 44, and 50 that are external terminals. It is.

That is, when performing initial writing at a factory or the like, first, a high level H is applied to the external terminal 50 for initial read / write control and the external DC power supply V
dd = 3 [V] is applied. Thereby, the switch 52
The common contact 52a is immediately connected to the fixed contact 52c which is not the output side of the SUR circuit 16.

The power supply voltage Vdd = + 3 [V] is applied to the fuse 18 via the external power supply input terminal 24, the pad 22, and the switch 52. At this time, the current flowing through the fuse 18 changes the power supply voltage Vdd to the resistor 21.
[V] divided by the resistance value R of [100] [Ω] = 30 mA
Becomes The polysilicon pattern of the fuse 18 is 3
Since processing is performed so as not to cut off at 0 mA but to cut off at 120 mA, the high level H of the power supply voltage Vdd is input to the input of the buffer 20 without disconnection of the fuse 18.

Thus, the buffer 20 of the AND circuit 40
Is set to high level H, the read / write control input port of the flash memory 46 is
The level of the command signal R / W supplied to the read / write control external terminal 44 is supplied to the write enable port R / W as it is. For example, when the command signal R / W is set to the high level H, the flash memory 46 is set. Can be written.

The external terminal 50 for initial read / write control
Is a package 12D like the integrated circuit 10D.
By providing only the pad 54 on the IC chip 14 and making the initial read / write control external terminal 50 outside the package 12D, a so-called bonding option, the read / write control external terminal 50 is provided.
Can be completely hidden from the user. In this case, since the pad 54 functions as an internal terminal for initial read / write control, at the time of initial write at the factory, the pads 54, 42, 2 before and after the wafer test process of the IC chip 14 are performed.
It can be done by probing for 2, 30, etc.

FIG. 8 shows a circuit configuration of a specific example of the switch 52. The switch 52 has a multiplexer configuration including transmission gates 61 and 62 formed of CMOS (PMOS + NMOS) transistors with low power consumption and an inverter 63.

FIG. 9 shows a truth table 64 representing the operation of the switch 52 shown in FIG. 8, in which a high-level H or low-level L control input applied to the switching control terminal 52d is D, and a fixed contact 52c is provided. Input of A, fixed contact 52b
4 shows a logical relationship between the inputs A, B and the output C with respect to the control input D when the input to the control input D is B and the output appearing at the common contact 52a is C. That is, when the control input D is at the high level H, the input A is set to the output C, and when the control input D is at the low level L, the input B is set to the output C.

The integrated circuit 10D thus configured is
For example, the storage device can be incorporated in the cartridge such as a portable game machine employing a cartridge. With such a configuration, when a flash memory is used as a memory for storing software in the cartridge, it is possible to prevent the user from rewriting the contents of the flash memory for secondary use. it can. In the cartridge type storage device, RO
The advantage of using a flash memory instead of M (read only memory) is that, for example, software can be written just before shipment according to demand, thereby minimizing the inventory of cartridges in which specific software has been written, and thus minimizing the inventory. This is because sales can be made more efficient.

FIG. 10 shows the configuration of an integrated circuit 10E according to still another embodiment. This integrated circuit 10E
In the integrated circuit 10D shown in FIG. 7, even after the fuse 18 is cut off, the power supply voltage Vdd is applied to the SUR circuit 16 during the normal energization of the integrated circuit 10D, and the power consumption in the SUR circuit 16 constantly occurs. Is a circuit that solves the problem. In other words, this is for responding to a demand that when the integrated circuit 10D is used in a battery-driven device such as a portable device, the operation time is shortened by the battery, which is not preferable.

In the integrated circuit 10E of FIG. 10, the SUR circuit 16 is operated for a fixed time after the external DC power supply 38 (power supply Vdd) is turned on through the external power supply input terminal 24 provided on the package 12E. In the circuit,
An example is shown in which the power consumption of the SUR circuit 16 during normal use is saved.

Specifically, in the integrated circuit 10E, a semiconductor switch 66 having the same configuration as the switch 52 is provided between the pad 22 and the SUR circuit 16, and the switching control terminal 66d of the switch 66 and the pad 22 are connected. A power-on reset circuit (POR circuit) 68 for supplying a switching control signal Pr to the switching control terminal 66d is provided therebetween. The POR circuit 68 and the switch 66 constitute a power consumption limiting circuit.

FIG. 11 shows a specific example of the POR circuit 68. When the power supply voltage Vdd is applied to the pad 22 through the external power supply input terminal 24, charges are gradually accumulated in a capacitor 72 such as an external electrolytic capacitor, and a resistor 70 and a resistor 70 are connected to an input node of a Schmitt trigger type buffer 73. An intermediate voltage {Vdd × R2 / (R1 + R1)} determined by the ratio of the resistance values R1 and R2 of the resistor 71 takes a certain time determined by a time constant (can be determined by the capacitance C of the capacitor 72). I do.

Schmitt trigger type buffer 73
Has a function of preventing chattering of the switch 66.

In this case, as shown in the time chart of FIG. 12, the switching control terminal 66d of the switch 66 has a fixed time (also referred to as a power-on reset period) from time t0 when the power supply Vdd is applied to the external power supply input terminal 24. .) Td
The switching control signal Pr, which is a power-on reset signal that transits from a low level L to a high level H at a time t1 after the lapse of the elapsed time
Occurs.

The switch 66 is connected to the common contact 66a and the fixed contact 6 for a predetermined time Td after the power supply Vdd is turned on.
6b are connected by the low level L of the switching control signal Pr, and when the switching control signal Pr becomes the high level H,
Fixed contact 66c whose common contact 66a is at ground potential
Is switched to.

In the integrated circuit 10E, the time required for the fuse 18 to be disconnected is set to a period shorter than the power-on reset period Td, so that the fuse 18 is cut off within the power-on reset period Td. After the power-on reset period Td elapses, in other words, after the power-on reset is released, the SUR circuit 16
Is grounded through switch 66,
After the release of the power-on reset period Td, power consumption by the SUR circuit 16 can be eliminated.

The first power-on reset period T
Even if the fuse 18 could not be cut off by the energization of d, there is a high possibility that the fuse 18 can be cut off at the second and third energizations. Even in such a case, the power consumption of the SUR circuit 16 during the normal operation can be eliminated after each power-on reset period Td has elapsed.

FIG. 13 shows a POR circuit 68 of still another example.
2 shows the configuration of A. The POR circuit 68A uses a preset down counter 76 which is a digital circuit. After turning on the power, the counter 76 generates a switching control signal Pr (see FIG. 12) that rises from a low level L to a high level H when counting the clock pulses generated by the clock generator 78 by a preset number. The POR circuit 68A of FIG. 13 requires the clock generator 78 as compared with the POR circuit 68 of the analog circuit of FIG. 11, but the measurement of the time for operating the SUR circuit 16 by the clock pulse is more accurate. In addition to this, there is an advantage that a capacitor C which is an external component having a large shape such as an electrolytic capacitor is not required.

Incidentally, instead of configuring the switch 66,
The switching control signal Pr, which is a power-on reset signal from the POR circuits 68 and 68A, may be directly input to the SUR circuit 16 to stop the operation in the internal circuit of the SUR circuit 16 (stop power consumption). it can.

FIG. 14 shows an example of a circuit in which power consumption is further reduced. In the integrated circuit 10F shown in FIG. 14, the IC chip 1 housed in the package 12F
In 4F, an inverter 80 forming a feedback loop is connected between the common connection point of the fuse 18 and the buffer 20 and the switching control terminal 66d of the switch 66. During the period from when the power supply Vdd is turned on until the fuse 18 is cut off, the power supply Vdd is connected to the fixed contact 66b and the common contact 6b.
6a to the input node of the SUR circuit 16 via
A high voltage is applied to the fuse 18 from the SUR circuit 16.

When the fuse 18 is cut off, the buffer 20
, Ie, the input node of the inverter 80 changes to low level L by the resistor 21, and the output level of the inverter 80 changes from low level L to high level H. After the switch 66 is switched by the feedback loop and the fuse 18 is cut off, the SUR circuit 16
Are fixed to the ground level via the common contact 66a and the fixed contact 66c, and the SUR circuit 16
Are stopped forever, and no power consumption occurs in the SUR circuit 16. Thus, the inverter 80 and the switch 66
Means that the fuse 18 has been shut off and the SU
It functions as a power consumption limiting circuit that reduces or eliminates power consumption of the R circuit 16.

However, in the integrated circuit 10F shown in FIG. 14, when the power supply Vdd is turned on, the SUR circuit 16 with relatively large power consumption operates until the fuse 18 is blown.

In practice, the fuse 18 does not necessarily need to be blown by one energization, but may be blown by two or more energizations. Therefore, the relatively large power consumption S
In order to limit the operation time of the UR circuit 16 and, once the fuse 18 has blown, the power supply Vd is supplied to the SUR circuit 16.
FIG. 15 shows a circuit that satisfies both conditions for preventing d from being supplied permanently.

The integrated circuit 10G of the example shown in FIG.
The POR circuit 68, the integrated circuit 10E, and the inverter 80 of FIG. 14 are combined. The output of the POR circuit 68 and the output of the inverter 80 are two inputs, and the output is connected to the switching control terminal 66d of the switch 66. An OR circuit 82 is inserted.

According to the integrated circuit 10G, during the power-on reset period Td, which is a fixed period when the power supply Vdd is turned on through the external power supply input terminal 24 provided in the package 12G, the POR circuit 68 controls the power-on reset period Td. When the fixed contact 66b of the switch 66 and the common contact 66a are connected, the SUR circuit 16 operates in the same manner as the integrated circuit 10E of FIG. 10 and supplies a current for fusing to the fuse 18.

Once the fuse 18 has blown, the fixed contact whose common contact 66a of the switch 66 is at the ground level is output immediately after the power supply Vdd is turned on by the output of the high level H of the inverter 80 constituting the feedback loop. 66
c to prevent the SUR circuit 16 from being energized.
Thus, according to the integrated circuit 10G of FIG. 15,
Low power consumption and a constant initial energization period to the fuse 18 can be achieved.

The present invention is not limited to the above-described embodiment, but can adopt various configurations without departing from the gist of the present invention.

[0093]

As described above, according to the present invention, when a voltage is applied to a specific terminal of an electric / electronic circuit device or a current is supplied, the logical output of the logical output setting circuit is kept constant. The logic output is configured to be irreversible, so if this electric / electronic circuit device is used, it is possible to modify the hardware of the electric / electronic product, modify the software, Use and the like can be physically prevented.

Here, when the specific terminal is used as a power input terminal, for example, when the user uses the terminal once in the field, the terminal is included in the electric / electronic circuit device.
For example, secondary use in a field such as a storage device can be disabled.

Further, the effect of the present invention will be specifically described. For example, in a maker that manufactures a product having a storage device incorporating the electric / electronic circuit device of the present invention as an LSI, a special tool or the like is used. It is possible to install a program in a storage device such as a flash memory with built-in LSI, perform a chip shipping test, and perform a product operation test. On the other hand, after the product is shipped to the market, the user is physically prevented from modifying the hardware such as the LSI, falsifying the software stored in the storage device, and possibly using fraudulently. can do. According to the present invention, such a mechanism can be incorporated into an electric / electronic circuit device.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an integrated circuit to which an embodiment of the present invention is applied.

FIG. 2 is a pattern diagram used for describing a specific configuration of a fuse;

FIG. 3 is a schematic diagram showing a state where power is supplied to an integrated circuit.

FIG. 4 is a circuit block diagram showing a configuration of another embodiment of the present invention.

FIG. 5 is a circuit block diagram showing a configuration of still another embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a configuration of a virtual integrated circuit example provided for explanation of operation.

FIG. 7 is a circuit block diagram showing a configuration of an integrated circuit having a configuration in which a storage device can be written to by an external terminal input before a fuse is cut off.

FIG. 8 is a circuit diagram showing a configuration example of a multiplexer in the example of FIG. 7;

FIG. 9 is a diagram illustrating a truth table illustrating an operation of the multiplexer of FIG. 8;

FIG. 10 is a circuit block diagram showing a configuration of an example of an integrated circuit in which low power consumption is achieved after a fuse is cut off by employing a power-on reset circuit.

FIG. 11 is a circuit diagram illustrating a configuration example of a power-on reset circuit;

FIG. 12 is a time chart for explaining the operation of the integrated circuit in the example of FIG. 10;

FIG. 13 is a circuit diagram showing a configuration of another example of the power-on reset circuit.

FIG. 14 is a circuit block diagram showing a configuration of another example of an integrated circuit for reducing power consumption after fuse cutoff.

15 is a circuit block diagram showing a configuration of an integrated circuit example in which the circuit of FIG. 10 and the circuit of FIG. 14 are combined.

[Explanation of symbols]

10, 10C, 10D, 10E, 10F, 10G: integrated circuit 10A, 10B: electric and electronic circuit device 12, 12C, 12D, 12E, 12F, 12G: package 14: IC chip 16: step-up regulator circuit (SUR circuit,
Booster circuit 18 fuse (blocking element) 18p polysilicon wiring pattern 20 buffer 21, 56, 7
0, 71: Resistor 22, 30, 42, 54: Pad 24: External power input terminal 32: External ground terminal 34: Logical output setting circuit 38: External DC power supply 40: AND circuit 44: External terminal 46: Flash memory ( 52, 66 semiconductor switches 61, 62 transmission gates 63, 80 inverters 68, 68A power-on reset circuit (POR circuit) 72 capacitors 73 Schmitt trigger type buffers 76 counter 78 clock generator

Claims (21)

[Claims] 1. A logic circuit comprising: a specific terminal; a logic output setting circuit connected to the specific terminal for setting a logic output; and when a voltage is applied to the specific terminal, the logic of the logic output setting circuit is determined. An electric / electronic circuit device, wherein an output is fixed irreversibly to a fixed logical output. 2. The electric / electronic circuit device according to claim 1, wherein the logic output setting circuit has a shutoff element that is irreversibly shut off based on a voltage applied to the specific terminal. Electrical and electronic circuit devices. 3. The electric / electronic circuit device according to claim 2, wherein a booster circuit is provided between said specific terminal and said cutoff element. 4. The electric / electronic circuit device according to claim 3, further comprising a power-on reset circuit that keeps the booster circuit operating for a predetermined period from when a voltage is applied to the specific terminal. Electric and electronic circuit devices. 5. The electric / electronic circuit device according to claim 3, wherein the cut-off element is cut off by an output of the booster circuit when the voltage is applied to the specific terminal. An electric / electronic circuit device, wherein a power consumption limiting circuit for reducing or eliminating the power consumption of the booster circuit is detected by detecting that the cutoff element has been cut off. 6. The electric / electronic circuit device according to claim 3, further comprising: a power-on reset circuit that activates the booster circuit for a predetermined period from when a voltage is applied to the specific terminal; The power-on reset circuit shuts off the output of the booster circuit that has been turned on. The booster circuit detects that the shutoff element has been shut off, and reduces or eliminates power consumption of the booster circuit. An electric / electronic circuit device to which a power consumption limiting circuit is connected. 7. The electric / electronic circuit device according to claim 2, wherein said electric / electronic circuit device is constituted by an integrated circuit, and said interrupting element is formed by a silicon wiring pattern. An electric / electronic circuit device characterized by: 8. The electric / electronic circuit device according to claim 1, wherein the specific terminal is a power input terminal of the electric / electronic circuit device. Electronic circuit device. 9. When a voltage is applied to a specific external terminal,
A logic output setting circuit whose logic output is irreversibly fixed to a fixed logic output, and an electrically writable and erasable storage device connected to the output side of the logic output setting circuit. Electric and electronic circuit devices. 10. The electric / electronic circuit device according to claim 9, wherein a read / write control external terminal is connected to a read / write control input of the storage device, and before a voltage is applied to the specific external terminal, An electric / electronic circuit device, wherein read / write control for the storage device is enabled using the read / write control external terminal. 11. The electric / electronic circuit device according to claim 9, wherein a read / write control internal terminal is connected to a read / write control input of the storage device, and before a voltage is applied to the specific external terminal, An electric / electronic circuit device, wherein read / write control for the storage device is enabled by using the read / write control internal terminal. 12. The electric / electronic circuit device according to claim 9, wherein when a voltage is actually applied to said specific external terminal, said logic output setting circuit is fixed and fixed. An electrical / electronic circuit device characterized in that the storage device can be used only as a read-only memory by the logical output of (1). 13. The electric / electronic circuit device according to claim 9, wherein the logic output setting circuit is irreversibly cut off based on a voltage applied to the specific external terminal. An electric / electronic circuit device having a shut-off element. 14. The electric / electronic circuit device according to claim 13, wherein a booster circuit is provided between the specific external terminal and the cutoff element. 15. The electric / electronic circuit device according to claim 14, further comprising: a power-on reset circuit that activates the booster circuit for a certain period from when a voltage is applied to the specific external terminal. Electrical and electronic circuit devices. 16. The electric / electronic circuit device according to claim 14, wherein the cutoff element is cut off by an output of the booster circuit when a voltage is applied to the specific external terminal. An electric / electronic circuit device, wherein a power consumption limiting circuit for reducing or eliminating power consumption of the booster circuit is detected by detecting that the cutoff element has been cut off. 17. The electric / electronic circuit device according to claim 14, further comprising: a power-on reset circuit that activates the booster circuit for a predetermined period from when a voltage is applied to the specific external terminal; Is shut off by the output of the booster circuit that has been activated by the power-on reset circuit. The booster circuit detects that the shutoff element has been shut off, and reduces power consumption of the booster circuit or An electric / electronic circuit device to which a power consumption limiting circuit to be eliminated is connected. 18. The electric / electronic circuit device according to claim 13, wherein said electric / electronic circuit device is constituted by an integrated circuit, and said blocking element is formed by a silicon wiring pattern. An electric / electronic circuit device characterized by: 19. The electric / electronic circuit device according to claim 9, wherein the specific external terminal is a power input terminal of the electric / electronic circuit device. -Electronic circuit devices. 20. A specific terminal, and a logical output setting circuit connected to the specific terminal and setting a logical output, wherein when a current is supplied to the specific terminal, the logic of the logical output setting circuit is An electric / electronic circuit device, wherein an output is fixed irreversibly to a fixed logical output. 21. A logic output setting circuit whose logic output is irreversibly fixed to a constant logic output when a current is supplied to a specific external terminal, and an electrical circuit connected to the output side of the logic output setting circuit. An electric / electronic circuit device, comprising: a storage device capable of writing and erasing information.