JP2001137504A - Arithmetic processing unit for game - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit for a game machine reducing the waste of external I/O selection signals and the waste of external I/O selection signal output pins while considering flexibility. SOLUTION: This arithmetic processing unit can be selected for use to a first external I/0 control mode (CS mode) capable of outputting N selection signals or a second external I/0 control mode (ECS mode) capable of outputting (N+X) selection signals based on the prescribed mode specification signal (CS /ECS signal). M selection signals at maximum can be obtained by externally decoding X selection signals in the ECS mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game processing unit for a game machine (hereinafter simply referred to as a game machine) which is likely to excite a sense of gambling, such as a pachinko game machine, a throttle machine or a video game machine. In particular, so-called "amusement chips" (those formed and packaged on a common semiconductor substrate) attached to an internal substrate of the gaming machine (for example, a game control substrate in the case of a pachinko gaming machine). The present invention relates to an improvement in an arithmetic processing device.

[0002]

2. Description of the Related Art Conventionally, the manufacture and sale of a game machine and a game store (hereinafter referred to as a "hall"), which may arouse gambling spirit.
Installation and transfer to the premises is performed in accordance with various regulations based on laws and regulations. In other words, manufacturing and sales require inspection by a specified inspection organization (hereinafter sometimes referred to as "third party organization"), and installation in a hall requires confirmation by the relevant police station (hereinafter referred to as "authority"). I do. Further, when the gaming machine is moved in the same hall or replaced with a new stand (including replacement of only the game control board and the game processing device on the board), confirmation by the authority is required. These various procedures are to maintain the performance of gaming machines to a certain standard, and to eliminate unauthorized gaming by placing the gaming machines installed in halls under the control of the authorities, thereby reducing the purpose of the law. (Such as “Sounding of customs sales”).

[0003] However, despite the various regulations described above,
Unauthorized acts continue without a break, for example, a program ROM (Read Only) containing a legitimate game program.
Memory, for example, is replaced with a falsified ROM called a “back ROM” so as to easily generate a big hit. Therefore, the program ROM is stored in the CPU (Central Pr).
hardware units, a main memory, peripheral circuits, and the like, are integrated into one chip on the same semiconductor substrate to form a so-called amusement chip, which is mounted on a game control board. According to this, since the program ROM is mounted in the chip, an unauthorized game program (falsified game program) is run unless at least the amusement chip itself or the control board on which the amusement chip is mounted is replaced. Can meet the social needs by achieving the objectives of the above laws and regulations.

Here, the amusement chip is
As described above, hardware blocks such as a CPU core, a program ROM, a main memory, and peripheral circuits are integrated into one chip and packaged. Sufficient consideration is required in terms of versatility. For example, one of the peripheral circuits includes an I / O block for inputting / outputting an external signal. The number of the I / O blocks varies depending on the type of the gaming machine, and the expected maximum number of I / O blocks is mounted. Although such a case is preferable in terms of versatility, it is not practical because it increases the package size and the number of pins. Therefore, instead of mounting an I / O block, it is conceivable to mount a circuit block (hereinafter, referred to as a chip select controller) that generates and outputs a signal (hereinafter, referred to as a chip select signal) for selecting the I / O block.
According to this, for example, a chip select controller capable of generating n chip select signals of CS0 to CSn is mounted on an amusement chip, and each signal is assigned to a unique address in a memory space of a CPU.
The n chip select signals can be selectively used in the program, and the externally attached maximum of n I / O blocks can be freely used, and the package size is n I / O blocks. The size can be significantly reduced as compared with mounting blocks, and the number of pins can be suppressed to the number (n) of chip select signals.

[0005]

When the versatility of the amusement chip is considered, the number (n) of the chip select signals is the largest among all the gaming machines in which the amusement chip is expected to be mounted. The number (m) of O blocks must match the one with the largest number. That is, n = m must be satisfied. However, in this case, one to m I
Although it can be applied to all gaming machines having / O blocks and is desirable in terms of versatility, for example, m '
When applied to a gaming machine having a / O block, nm '
There is a problem that the chip select signals and pins are wasted (they are not used permanently in the gaming machine). Therefore, the problem to be solved by the present invention is the field of manufacturing a game machine such as a pachinko machine or a spinning-type game machine, or a game field (also referred to as a game store or a halt) for providing the game machine with a game or the game In the field of machine inspections, gaming machines that have improved versatility of gaming machines and have reduced the waste of external I / O selection signals and the same signal output pins to achieve a simplified configuration and reduced manufacturing costs. Another object of the present invention is to provide a computer processing unit.

[0006]

According to a first aspect of the present invention, there is provided a game processing device comprising: a game control means for controlling a game of a game machine on a common semiconductor substrate; Signal generation means for generating a selection signal for selecting an I / O, wherein the signal generation means generates any one of M internal selection signals based on a signal from the game control means. Signal generating means, and one corresponding to each of the N internal selection signals among the M internal selection signals.
Second signal generating means for generating a bit signal as the selection signal; and X corresponding to each of the remaining M-N internal selection signals excluding the N internal selection signals among the M internal selection signals. Bit (X is the value of ^X that satisfies M−N = 2 ^X )
Third signal generating means for generating each bit of the signal as the selection signal, and outputting only the output of the second signal generating means to the outside based on a predetermined mode designating signal, or Selecting means for selecting whether to output both outputs of the third signal generating means to the outside. According to a second aspect of the present invention, in the gaming operation processing device according to the first aspect, the output of the third signal generation means output from the selection means to the outside is decoded by decoding the MN number of the third signal generation means. A reproduction means for reproducing the selection signal is provided externally.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking as an example a hall in which a number of pachinko gaming machines are installed. <Overall Configuration of Hole> First, the overall configuration of the hole will be described. FIG. 1 is a block diagram showing the overall configuration of the hall. In this figure, reference numeral 1 denotes a hall (game store), and in the hall 1, a CR (card reader) type gaming machine 10j (j
Pachinko Island 1 where a, b, etc.
1. Status change information recording device JR, auxiliary status change information recording device JRs, history processing device 12, counter computer CC, facsimile device 13, office computer HC,
Printer 14, communication control devices 15 to 18, ball counter 1
9, an island safe 20, a surveillance camera system 21, an announcement system 22, and a setting / inspection device 23 are arranged. The setting / inspection device 23 is not always provided. It is used by connecting to the in-store network 24 whenever necessary.

[0008] The pachinko island 11 includes information collecting terminal devices 31a and 31b (hereinafter, appropriately represented by the information collecting terminal device 31), which are also called information collecting boxes, and gaming machines 10a and 10a.
b (gaming machine 10), card-type ball rental devices 32a, 32b
(Card type ball rental device 32), ball cutting devices 33a, 33b
(The ball cutting device 33), the pulse tanks 34a and 34b (the pulse tank 34), and the network relay device 25. Although a plurality of pachinko islands 11 are arranged in the hall 1, each "island" has a similar structure (however, the type of a game machine is often different for each island), and therefore, here, one pachinko island 11 is used. Will be described. One network relay device 25 is provided for each pachinko island 11, but each of the other devices (for example, the information collecting terminal device 31, the ball cutting device 33, and the pulse tank 34) is connected to the gaming machines 10a and 10b. The same number is arranged (that is, paired with the gaming machine 10).

The gaming machine 10 has game control devices 41a and 41b (hereinafter, appropriately represented by the game control device 41) for controlling a game state, and the game control device 41 controls a game. Arithmetic processing device (see FIG. 5; however, it is simply referred to as an arithmetic processing device in FIG. 5) 200
(Corresponding to the amusement chip described at the beginning; a detailed configuration will be described later). Game control device 41
Includes a game control board and a case for housing the board.
A card-type ball lending device 32 is arranged on the side of the gaming machine 10, so that a ball lending operation using a prepaid card (PC) can be performed by the gaming machine 10.
The ball cutting device 33 feeds the pachinko island 1 to the supply tank of the gaming machine 10.
The ball is replenished from 1 and, for example, a signal (a replenishment ball number signal shown in FIG. 2 described later) that becomes one pulse every time 10 balls are replenished is output from the ball cutting device 33. The pulse tank 34 counts the number of balls collected after the game and collected from the gaming machine 10 to the outside.
A signal (one collected ball count signal shown in FIG. 2 described later) that becomes one pulse is output for every 10 balls that have flowed out (collected).

Each of the information collecting terminal devices 31
1 and PJ2 and distribution circuits 42a and 42b (hereinafter, appropriately represented by the distribution circuit 42). The distribution circuit 42 includes the gaming machine 10, the card-type ball rental device 32, and the ball cutting device 3.
3 and the pulse tank 34, and distributes signals input / output from / to these devices to PJ1 and PJ2 for transfer. For example, the distribution circuit 42 distributes and transmits a sales signal, a supply ball number signal, a recovered ball number signal, a jackpot signal, a special figure rotation signal, a positive change signal, and an amuse communication signal to PJ1, and transmits the signal to PJ2. Stop signal, metal frame opening / closing signal, wooden frame opening / closing signal, empty plate signal (signal for detecting that the amount of balls supplied to the storage tank of the gaming machine 10 from the pachinko island 11 has decreased), abnormal signal (illegal electromagnetic wave) And a signal for detecting an illegal magnetic force and an electromagnetic wave (e.g., an electric signal) and a power-off signal.

PJ1 is a game machine which is assigned to itself based on a sales signal, a replenishment ball number signal, a recovered ball number signal, a big hit signal, a special figure rotation signal, a positive change signal, and an amuse communication signal input / output from the game control device 41. 10 and game information output from the game equipment device (ball rental device 32, etc.),
The game information is processed together with the game information (state change information) transferred from the PJ 2 to detect a change in the game information from the collected game information and the like. False determination), and the detailed block configuration will be described later. The PJ 2 transfers state change information (for example, a metal frame opening signal, an empty plate signal, etc.) mainly for monitoring the gaming machine 10 collected from the gaming machine 10 and the game equipment device (the ball rental device 32 or the like) to the PJ 1. Processing and PJ
The processing for inactivating the gaming machine 10 (processing for generating a stop signal or a power-off signal) when a firing stop request is issued from 1 is performed. Like the PJ1, its detailed block configuration will be described later. . The network relay device 25 has, for example, a function of a router (Router), and
6 and a relay connection between each LON of the in-store network 24. The island network 26 includes LON (LON (Local O) developed by
(performing Network: a registered trademark of the company)
Has been adopted.

Pachinko Island 11 is an island network 2
6. JR, JRs, history processing device 12, CC, via network relay device 25 and in-store network 24
HC, communication control devices 15 to 18, and setting / inspection device 2
3 is connected. The in-store network 24 employs the same LON as described above. Island network 26,
Network relay device 25 and in-store network 24
Constitutes a communication network 27 (hereinafter sometimes referred to as an LON communication network) connecting the PJ1, PJ2, JR, JRs, CC and HC as a whole. Note that the LON communication network 2
7, information is transferred by an authenticated message using the LONTALK protocol, and both nodes are mutually authenticated to ensure reliability. One JR and one JRs are provided in Hall 1. For example, one gaming machine is installed for every 500 gaming machines. Alternatively, when there are a plurality of game floors, one game floor may be installed for each floor. The JR organizes and records the game information (state change information) notified from the PJ1 of each pachinko island 11 for each game machine, and the JRs is J.
Back up R. The history processing device 12 is connected to the in-store network 24 by PJ1, PJ2, JR, J
This is a device for recording error information from Rs or the like.
PJ2, JR, JRs, etc.) are specified.

A general-purpose personal computer can be used as the CC. CC is the gaming machine 10 of the day
Of the state change information is collected by polling the JR or JRs, and a state change is detected and displayed. In general, a jackpot or a probability change in the state change information is generally required to check detailed game information of the gaming machine 10 in which the event has occurred in the CC. Therefore, in the case of this specific state change, the corresponding gaming machine Collect game information from 10 PJ1s,
Detailed game information is displayed together with the previous state change information.
If the JR fails to collect information due to a trouble, it immediately switches to backup JRs and performs similar information collection and display. Further, when the CC wants to check the game information of the desired gaming machine 10, the corresponding PJ
There is also a function of collecting and displaying game information from the first game information. The CC and the HC are connected by a dedicated network cable 28 (for example, Ethernet). If the CC wants to confirm management information such as sales, model information and time-series information, obtain the information from the HC. Can be displayed. A facsimile device 13 is connected to the CC, and the information collected and analyzed by the CC can be processed into a predetermined print format and transmitted to the outside.

A general-purpose personal computer can be used for the HC. The HC generates various kinds of information contributing to management decisions based on the game information of the day or the past, collects the game information by polling the PJ1 or PJ2 at predetermined intervals, records the information on a hard disk or the like, It can be displayed and printed in a predetermined format. In addition, when it is desired to check game information of a specific game machine 10 with the HC, there is also a function of directly collecting and displaying game information from the corresponding PJ1. Furthermore, when it is desired to check the state change information (real-type information) of the gaming machine 10 with the HC, the information can be obtained from the CC via the network cable 28 and displayed. Note that H
The printer 14 is connected to C and can print collected information in a predetermined format. CC and HC
Constitutes a management device that manages overall game information of the game store 1.

The communication control devices 15 to 18 include a ball counter 19,
The device performs a communication interface between the island safe 20, the surveillance camera system 21, the announcement system 22, and the in-store network 24. The ball counter 19 counts the balls (for example, for prize exchange) obtained by the player, transfers the counted value to CC and HC, and prints a counting result sheet for prize exchange to the player. Out and output. The island safe 20 is a device for storing coins and bills collected from a money changer, a cash-type ball lending device, etc. provided in the hall 1.
Transfer to C one by one. Surveillance camera system 21 is Hall 1
Is a system that manages a monitoring camera arranged in the hall and records a captured image, and an announcement system 22 is a system that performs an announcement in the hall 1 manually and automatically.

As the setting / inspection device 23, for example, a notebook personal computer can be used.
The setting / inspection device 23 is connected to the in-store network 2 if necessary.
4 and automatically obtains an account of the LON communication network 27 at the time of connection, and accesses the game processing unit 200 built in the game control device 41 of the game machine 10 connected to any PJ1. A unique ID for validity determination can be set. As described above, the setting / inspection device 23 is connected to the in-store network 24 “as needed”. The case of necessity means, for example, a case where a new stand is replaced, a case where only the game processing device 200 is replaced, or a case where the game processing device 200 is replaced.
After the replacement, the setting / inspection device 23 is connected to the in-store network 24, and is built in the game control device 41 of the table (replaced gaming machine 10) via the new PJ1. The game processing unit 200 is accessed to set a unique ID for validity determination.

Note that the game processing unit 200 is used in PJ1.
In determining the validity of the game program, the game program may be used as the determination information in addition to the determination of the unique ID as described above. The same reference game program is set from the setting / inspection device 23 to PJ1. The PJ1 reads the game program from the game processing device 200, and compares the read game program with the set reference game program to determine validity.

<Structure of PJ1> Next, the block structure of PJ1 will be described. FIG. 2 is a block diagram of PJ1. In this figure, PJ1 is a CPU 51, a ROM 5
2. RAM 53, EEPROM 54, backup power supply 55, oscillation circuit 56, communication control device 57, output interface (I / F) 58, input interface (I / F)
F) 59 and a bus 60. CPU 51 is R
Based on the processing program stored in the OM 52, the game information output from the gaming machine 10 and the game equipment device (such as the ball rental device 32) that the user is responsible for, and the game information (state change information) transferred from the PJ2. At the same time processing
A process of detecting a change in the game information from the collected game information is performed, and the validity of the game processing unit 200 is determined. The ROM 52 stores a processing program for determining the validity of the game processing device 200 and a processing program for collecting and processing game information.
Is used as a work area.

The EEPROM 54 stores the same information (hereinafter, also referred to as a "collation ID") identical to the unique ID stored at the time of manufacture in the game processing unit 200 connected to the PJ1. For example, when N gaming machines 10 are installed in the hall 1 in a playable state, the EEPR
The OM 54 stores N matching IDs. This storage operation is performed by the setting / inspection device 23. Also, E
The EPROM 54 also stores set values for monitoring state change information. This set value is set by CC or HC. The backup power supply 55 is a power supply (primary battery or secondary battery) for retaining the information stored in the RAM 53 even during a power failure.
It is. The oscillation circuit 56 supplies a control clock signal to the CPU 51. The communication control device 57 is connected to the island network 26.
Via the PJ1 and another network terminal (for example,
It controls communication necessary for transferring information with the PJ 2 or each terminal connected to the in-store network 24 via the network relay device 25.

The output interface 58 performs an output interface process between the gaming machine 10 and the CPU 51, and outputs an amuse communication signal from the output interface 58 to the game control device 41 of the gaming machine 10. The amuse communication signal is a signal for outputting various commands (for example, an authentication check command) to the game processing device 200 built in the game control device 41. The input interface 59 performs an input interface process between the gaming machine 10 and the game equipment device (the ball rental device 32 or the like) and the CPU 51, and includes an amuse communication signal, a card sales signal from the card-type ball rental device 32C, A sales signal by cash from the cash-type ball rental device 32G, a supply ball number signal from the ball cutting device 33, a pulse tank 3
4, a special figure rotation signal, a jackpot signal, and a probability change signal from the game control device 41 are respectively input. The input interface 59 interfaces these signals and sends them to the CPU 51.

The amuse communication signal input to the input interface circuit 59 is, for example, an authentication code (unique I) transmitted from the game processing unit 200 of the gaming machine 10.
This signal is monitored (authentication determination) by the CPU 51 to determine whether or not the regular game processing device 200 is mounted. The card sales signal is a signal notifying the sales of lending a ball using a prepaid card by the card-type ball lending device 32C. In addition, in addition to the card-type ball lending device 32C using a prepaid card, the ball lending device includes a cash-type ball lending device 32G that lends a ball by inserting cash. In the case of the cash-type ball lending device 32G, And a cash sales signal corresponding to the lending of a ball accompanying the input of cash. The replenishment ball number signal is a signal that informs the number of balls replenished from the pachinko island 11 to the replenishment tank of the gaming machine 10 when the number of replenishment tanks of the gaming machine 10 decreases when the number of replenishment tanks of the gaming machine 10 decreases due to the winning prize. A so-called IN signal output from the ball cutting device 33 (for example, a signal that becomes 1 pulse when 10 balls are supplied, a signal that becomes 1 pulse when 100 balls are supplied, or a signal that becomes 1 pulse when 400 balls are supplied) Is used.
Further, if the gaming machine has a terminal for directly communicating the number of prize balls to the outside from the gaming machine 10, a signal may be obtained from the terminal.

The number-of-recovered-balls signal is a signal notifying that a ball has flowed from the gaming machine 10 toward the pachinko island 11 (that is, a ball in which the game has been completed and the result of the game has been determined is out of the gaming machine). For example, an out signal that becomes one pulse in response to outflow of ten balls from the pulse tank 34 is used.
Toku-zu rotation signal, when the gaming machine 10 is the first type,
This signal indicates the rotation of the special symbol when the symbol of the special symbol display device (hereinafter referred to as a special symbol) has finished changing. The jackpot signal is a signal that informs that a special jackpot of the gaming machine 10 is in a specific profit state (for example, a jackpot slot state: “777”) and that a jackpot has occurred. This signal is a gaming machine. It is output from the time of the jackpot occurrence to the end of the jackpot from 10. When the gaming machine 10 is a gaming machine with a probability variation game, the probability variation signal is a signal that informs the player during the probability variation and during the jackpot.

As described above, the PJ 1 is provided for each of the gaming machines 10 and determines the validity of the game processing device 200 based on the amuse communication signal. If it is recognized, the PJ2 requests the PJ2 to stop firing the ball and performs processing to deactivate the gaming machine 10. In addition, a sales signal by card, a sales signal by cash, a signal of the number of supply balls, a signal of the number of collected balls, The game information and the state change information are processed based on the input of the special figure rotation signal, the jackpot signal, or the probability change signal. Also, PJ
1 is game information (state change information) transferred from PJ2
In addition to this, when a change in game information is detected from the collected game information, the contents of the state change information are independently reported to the JR and JRs. Furthermore, when there is a request command from the CC or HC, the PJ1 transfers the content of the game information to the requesting CC or HC as current game information.

<Structure of PJ2> Next, the block structure of PJ2 will be described. FIG. 3 is a block diagram of PJ2. In this figure, PJ2 is CPU61, ROM6
2. RAM 63, EEPROM 64, backup power supply 65, oscillation circuit 66, communication controller 67, output interface (I / F) 68, input interface (I / F)
F) 69 and a bus 70. CPU 61 is R
Based on a processing program stored in the OM 62, a state change is detected (for example, opening / closing of a metal frame) from a signal collected from the gaming machine 10 and the game equipment (eg, the metal frame sensor 133) assigned to the user, and the information is detected. To PJ1,
In addition to performing a process of having the PJ1 transfer the data to an upper node, the PJ1 performs a process of inactivating the gaming machine 10 (for example, stopping the launch of a ball or stopping a game program) when there is a firing stop request from the PJ1. The ROM 62 stores a processing program for state change detection and the like.
Reference numeral 3 is used as a work area.

The EEPROM 64 stores set values for monitoring status change information in the PJ 2. This set value is set by CC or HC. The backup power supply 65 is a power supply (primary battery or secondary battery) for retaining the information stored in the RAM 63 even during a power failure. The oscillating circuit 66 supplies a control clock signal to the CPU 61, and the communication control device 67 transmits the control clock signal via the island network 26.
Communication control between J2 and PJ1 is performed. The output interface 68 performs an output interface process between the gaming machine 10 and the CPU 61, and outputs a power-off signal to the gaming machine power supply 131 of the gaming machine 10 from the output interface 68, and outputs a signal from the launch control unit 132. , A stop signal is output. Gaming machine power supply 131
Is a device for turning on and off the power supply to the gaming machine 10. When a power-off signal is inputted, the power supply to the gaming machine 10 is turned off. The stop signal is a signal for instructing the gaming machine 10 to stop firing, and is output via the PJ2 in response to a command from the CC or the like. The firing control device 132 stops firing the ball in response to the input of the hitting signal. Input interface 6
9 is a gaming machine 10 and a game equipment (a metal frame sensor 133)
) And the CPU 61. The input interface 69 includes a gaming machine 1
A metal frame opening / closing signal from the metal frame sensor 133, a wooden frame opening / closing signal from the wooden frame sensor 134, an empty plate signal from the replenishment detection sensor 135, and an abnormal signal from the electromagnetic wave detection device 136 are input. The input interface 69
These signals are interfaced and sent to the CPU 61.

The metal frame sensor 133 detects the open / closed state of the metal frame in the gaming machine 10, and is constituted by a switch provided near the metal frame and for detecting the open / closed state of the metal frame. The wooden frame sensor 134 detects the open / closed state of the frame-shaped front frame in the gaming machine 10, and is configured by a switch provided near the frame-shaped front frame to detect the open / closed state of the wooden frame.
The replenishment detection sensor 135 detects that the amount of balls replenished in the tank of the gaming machine 10 (the game balls are replenished from the pachinko island 11 in the tank) has decreased, and outputs an empty plate signal. The electromagnetic wave detection device 136 outputs an abnormal signal when detecting the approach of a magnet to the gaming machine 10 or the emission of radio waves to the gaming machine 10.

As described above, the PJ 2 is provided for each of the gaming machines 10 and detects a state change from a signal collected from the gaming machine 10 and a game facility device (such as the frame sensor 133) (for example, when the frame is 10 frames). Then, the information is transferred to the PJ1 and the PJ1 transfers the information to an upper node. When the PJ1 issues a firing stop request, the gaming machine 10 is deactivated. Note that P
J2 may be integrated into PJ1. For example, PJ2 may be integrally mounted on the substrate of PJ1. Here, as a whole, PJ1 and PJ2 are monitoring devices that monitor the unique ID of the game processing device 200 included in the game control device 41 of the gaming machine 10 and evaluate the legitimacy of the game processing device 200. Is configured.

<Configuration of Gaming Machine> FIG. 4 is a view showing the gaming machine 10. The gaming machine 10 has a frame-shaped front frame 71, a metal frame (glass frame) 72 for supporting glass, and a game area. Game panel 73, a front display panel 74, and an operation panel 75 provided below the front display panel 74. The front frame 71 is attached to an upper hinge 77 and a lower hinge 78 with respect to a wooden machine frame (not shown) on which the gaming machine 10 is installed.
The metal frame 72 is supported by the front frame 71 so as to be openable and closable. One end of the display panel 74 is supported by the front frame 71 so as to be openable and closable, and the upper plate 8 for receiving a prize ball.
1 is formed, and an opening / closing lever 83 is provided for opening and closing a passage connecting the balls of the upper plate 81 to a ball storage plate (also referred to as a receiving plate) 82 in order to transfer them. The operation panel 75 is provided with an ashtray 84 and the above-mentioned ball storage tray 82, and is provided with a ball release lever 85 for pulling out the balls stored in the ball storage tray 82 outward and downward.
An operation knob 86 for shooting a ball is provided on the right end side of the operation panel 75, and a big hit indicator 87 that lights or flashes at the time of a big hit is provided above the front frame 71 of the gaming machine 10.
Is provided.

On the game board 73, a game area is formed in which a substantially circular area on the front is surrounded by a guide rail 88, and a plurality of identification information (so-called special symbols;
Special figure display device 89 for displaying variable figures in a plurality of columns, special variable winning apparatus 90 having a special winning opening, ordinary variable winning apparatus 91 (so-called “Puden”) functioning as a special figure starting port, ordinary variable winning A general symbol display device 92 provided on the device 91 for displaying a normal symbol (so-called general symbol; hereinafter, general symbol), a plurality of general symbol starting gates 9 of a through-chucker type
3. A plurality of general winning ports 94, a plurality of hitting direction converting members 96 called windmills, left and right side lamps 97 and 98, an out hole 99, and the like are provided. Ordinary fluctuation winning device 9
1 is provided with a special figure starting switch 100, and a general figure starting gate switch 101 is provided in a passing path inside the general figure starting gate 93. In addition, a continuous switch 102 is provided in the continuous winning channel in the special winning opening of the special variable winning device 90, and a count switch 103 is provided in the general winning channel (refer to FIG. 5 for each of the above switches). .

The above-mentioned general winning opening 94 is arranged above the special figure display device 89, and four special figure starting storage displays 105 are provided. Is provided. The general-purpose display device 92 is, for example, a display device including a liquid crystal or an LED having a seven-segment display unit that displays a single-digit number. . The start memory displays 105 and 106 are for displaying the number of start memories of a special figure or a normal figure, respectively. The special figure start switch 100 is an ordinary variable prize winning device 91.
, The general figure starting gate switch 101 detects that the ball has passed through the general figure starting gate 93, and the count switch 103 detects all balls that have entered the special winning opening of the special variable winning device 90. The ball is detected and the continuation switch 10
2 detects a ball that has been continuously won (so-called V-win) among the balls that have entered the special winning opening. In the game area of the game board 73, a large number of obstacle nails such as a top nail and a nail are provided, but are omitted here to avoid congestion in the drawing. In addition, the game board 73 may be provided with other various decorative lamps, LEDs, and the like. There are various types of game areas on the game board, including those belonging to the so-called first type and those belonging to the third type provided with the symbol display device, but the present invention can be applied to any type. In short, what is necessary is just to be provided with the game arithmetic processing unit 200 which controls the game control. Incidentally, this embodiment is of the type belonging to the first type.

<Structure of Game Control Apparatus> FIG. 5 is a block diagram of the game control apparatus 41. The game control apparatus 41 is a game processing unit 200 as an amusement chip for controlling an accessory required for a pachinko game or the like. And an oscillator 111 that divides the natural frequency of the vibration element to generate a predetermined clock signal (CLK), and a power supply that detects power supply to the game control device 41 and generates a system reset signal (RST) Detection circuit (noted as RST generator in the figure) 11
2 and 5 ports 113a for inputting various sensor signals
Interface 113 having a plurality of input signals 113a to 113e, and nine ports 114a to 114i for outputting various drive signals.
, An output interface 114 having a sound generator, a sound generator 115 for generating a sound effect (electronic sound or voice synthesis sound) required for the game, and a sound effect signal from the sound generator 115 being amplified and installed at a predetermined position of the gaming machine 10. An amplifier 117 for outputting to the speaker 116, an external communication terminal 118 for exchanging signals between the game processing device 200 and the information collecting terminal device 31j (see the information collecting terminal devices 31a and 31b in FIG. 1). An external bus 125 (“external” means outside the game processing device 200) connecting the game processing device 200 with the input interface 113, the output interface 114, and the sound generator 115;
13 chip select signals output from the game processing device 200 (corresponding to the select signals described in the summary of the invention)
CS0 to CS12 are converted to 24 chip select signals CS0.
And a signal extension circuit 126 extending to CS23. The gaming machine 10 according to the present embodiment
As described above, the game control device 41 includes a signal extension circuit 126 for extending the 13 chip select signals CS0 to CS12 output from the game processing device 200 to 24 chip select signals CS0 to CS23. Therefore, the CS / ECS mode, which will be described in detail later, is set to the ECS mode and used.

Each port 1 of the input interface 113
Signals from the special figure start switch 100, the general figure start gate switch 101, the continuation switch 102, the count switch 103, and the safe sensor 104 are input to 13a to 113e (five ports in the figure). The safe sensor 104 detects a winning game ball. From each of the ports 114a to 114i (9 ports in the figure) of the output interface 114, an external information terminal 119 for outputting game information to the information collecting terminal device 31, a special figure display device 89
Control device 120 for controlling the display of the game, a special winning opening solenoid 121 for opening and closing the special winning opening, which is a special variable winning device 90, a special figure start storage display 105, and a general figure display 9
2. Ordinary electric accessory solenoid 122 for driving the normal fluctuation prize device 91, general-purpose starting memory display 106, prize ball discharge circuit 123 for controlling prize ball discharge corresponding to a prize ball, various decorative lamps, LEDs ( For example, a control signal is output to a decorative accessory (124) including side lamps 97, 98 and the like.

An external bus 125 is connected to the input interface 113, the output interface 114, and the sound generator 115, and 24 chip select signals CS0 to C
S23 has been input, and the external I / O described in the summary of the invention has been entered.
The five ports 113a to 113e of the input interface 113, the nine ports 114a to 114i of the output interface 114, and the sound generator 115 correspond to 24 chip select signals CS0 to CS0.
The state of CS23 and some control signals (eg, MREQ, IOREQ, W
R, RD signal), one is selected, and via the selected I / O block and the external bus 125,
An input signal, for example, a signal from the special figure start switch 100 is taken into the game processing device 200, or a signal from the game processing device 200 is output to, for example, the display control device 120.

<Structure of Game Processing Unit> FIG. 6 is a block diagram of the game processing unit 200. The game processing device 200 is a game block 200A for performing game control.
And a management block 200B for performing information management, and is an amusement chip manufactured by packaging (manufactured below) components of each block on a common semiconductor substrate into one chip and packaging. The game block 200A includes main components such as a CPU core (corresponding to game control means described in the gist of the invention) 201, a program ROM 202 and a user work RAM 203, and also has an external bus interface 204, a random number generation circuit 205, a clock generator 206, A reset / interrupt control circuit 207, an address decoder (corresponding to the signal generating means and the first signal generating means described in the summary of the invention) 208 and a chip select controller (the signal generation means described in the summary of the invention and the second signal generating means) , Third signal generating means,
209, etc., and a CPU bus 210 for connecting these components.

The CPU core 201 is not particularly limited.
It is a Z80 core, performs arithmetic processing for game control,
The program ROM 202 stores the control program (game program). The user work RAM 203 corresponds to the main memory, and is used as a work area (work area) when executing processing based on the game program in the game block 200A. . The user work RAM 203 has a dedicated terminal (hereinafter referred to as V for convenience) assigned to one of the terminal groups of the game processing device 200.
(Referred to as CAP0), a power supply backup function can be added, and the stored contents can be retained even after the game machine 10 is powered off. VC
How to use AP0 will be described later.

The external bus interface 204 corresponds to FIG.
A plurality of bits (for example, 16 bits)
Bit) address signals A0 to A15, data signals D0 to D7 of plural bits (for example, 8 bits), a memory request signal MREQ, an input / output request signal IORQ,
It performs signal interface processing such as a memory write signal WR, a memory read signal RD, and a mode signal MODE. For example, when the mode signals are activated and the data signals D0 to D7 are added while the address signals A0 to A15 are sequentially incremented,
The mode becomes the writing mode to the program ROM 202, so that a game machine manufacturer or a third party can write a game program. Program ROM 202
When the writing of the game program into the memory is completed, a write end code is recorded in a predetermined area of the parameter memory 211 described later (for example, the code is recorded by physically cutting a predetermined code or a predetermined bit). If a write end code is recorded in the parameter memory 211, the game program cannot be written to the program ROM 202. Also, MRE
When the WR signal is activated while the Q signal or the IOREQ signal is activated, the D / D signal is supplied to a predetermined external I / O.
0 to D7 can be written, and when the RD signal is activated, D0 to D7 can be fetched from a predetermined external I / O. The predetermined external I / O is defined as each of the ports 113a-113 of the input interface 113 in FIG.
e, each port 114a of the output interface 114
114i and the sound generator 115, depending on the state of the chip select signals CS0 to CS12 (exactly 24 chip select signals CS0 to CS23 output from the signal expansion circuit 126 in FIG. 5) and the state of the WR or RD signal. It is one element selected by

The random number generation circuit 205 generates a random number (the random number is used for determining a jackpot or determining a symbol at the time of stoppage) relating to whether or not to add a game value (for example, a jackpot) in a game execution process. A mathematical method (for example, a congruential method or an M-sequence method) for generating a uniform random number is used. In the present embodiment, information related to the model is used as a seed value when generating a random number. The clock generator 206 supplies an operation clock signal to each block of the game processing device 200 including the CPU core 201 based on the clock signal CLK from the oscillator 111. A reset / interrupt control circuit 207 resets the CPU core 201 in response to a system reset signal (RST) from the power-on detection circuit 112 (details will be described later).
At the same time, various resources inside the game processing device 200 are set to the initial state.

The address decoder 208 is connected to the CPU bus 21
0 of the address bus, and according to the decoding result, 24 internal signals for selecting I / O resources (corresponding to the internal selection signals described in the gist of the invention) iCS0 to iCS0
Activate one of the iCSs 23. Where the CPU
The number of information bits on the address bus of the bus 210 is 16 bits from iA0 to iA15.
2 assigned in advance to a predetermined address in the address space up to
Four I / O addresses (for example, 2300h-2317)
In this case, the internal signal for selecting one I / O resource corresponding to the I / O address is activated.

The chip select controller 209 includes 24 internal signals iCS0 to iCS23 for selecting I / O resources from the address decoder 208 and the CPU core 20.
13 based on the mode designation signal CS / ECS from
The state of each of the chip select signals CS0 to CS12 is controlled. Specifically, the mode designation signal CS / EC
When S is "CS mode designation", all of the 13 chip select signals CS0 to CS12 are used for external I / O selection and the state is controlled. Chip select signal CS0
To CS12 (CS0 to CS7) are external I / O
For selection, control its state,
The combination state of the remaining five chip select signals CS8 to CS12 is controlled. 1 for CS mode
Using three chip select signals CS0 to CS12,
Up to 13 external I / Os can be controlled, but in the ECS mode, up to 24 external I / Os can be further controlled. That is, in the case of the ECS mode, a maximum of eight chip select signals CS0 to CS7 are used.
And the remaining five chip select signals CS8-C
2 ⁴ (= 16; index 4 corresponds to X described in the summary of the invention) in combination of 4 (CS8 to CS11) of S12, therefore, up to 8 + 16 = 24 External I / O can be controlled.

The external I / O in this embodiment is shown in FIG.
, The five ports 113 a to 113 e of the input interface 113 and the nine
Ports 114a to 114i and the sound generator 115, and includes 5 + 9 + 1 external I / Os, so that the ECS can be performed without using the CS mode.
Use mode. That is, by using the ECS mode, the actual number (13) of the chip select signals CS0 to CS12 is extended to 24, and the 15 external I / Os are extended by using the extended chip select signals CS0 to CS23.
O is supported.

The CPU bus 210 includes a data bus, an address bus, and a control bus.
And the program ROM 202, the external bus interface 204, the user work RAM 203, the clock generator 206, the reset interrupt control circuit 207, the address decoder 208, and the random number generation circuit 205, and a part of the management block 200B (boot) It is also connected to the ROM 212, the parameter memory 211, and the bus monitor circuit 214).

Next, the configuration of a management block 200B for managing information in the game processing unit 200 will be described. The management block 22B includes a parameter memory 211,
It includes a boot ROM 212, a bus monitor circuit 214, an ID property RAM 215, a security memory 216, a management work RAM 217, a control circuit 218, an external communication circuit 219, and a management bus 220, and also includes a part of the CPU bus 210 extending from the game block 200A. The CPU bus 210 has a boot ROM
212, a parameter memory 211 and a bus monitor circuit 214.

The boot ROM 212 stores a boot program, and is used at the time of system reset of the game processing device 200 (to be exact, after normal completion of the self-diagnosis and initialization of the management block 200B executed immediately after the system reset). This boot program starts up, performs a predetermined simple check, and if it is normal, passes the process to a predetermined address of the game program (a predetermined address in the address space of the CPU 201; generally, the starting address 0000h of the address space). Has become. The parameter memory 211 stores a write end code and initial setting information. The write end code is information indicating that the game program has been written in the program ROM 202 as described above. Further, the initial setting information refers to the on / off setting of the extended function (ECS mode) of the chip select signals CS0 to CS12 and the use of the chip select signals CS0 to CS12 when the game machine manufacturer writes a game program. If the mode is turned on, this is information for setting CS0 to CS23). Chip select signals CS0 to CS12
Is a function for expanding the number of chip select signals. When this function is turned on (ECS mode),
The chip select signal having only 13 signals from S0 to CS12 can be extended to 24 signals from CS0 to CS23. This embodiment uses the ECS mode as described above.

The bus monitor circuit 214 is connected to the CPU bus 21
0, and the CPU bus 210
When not used by 01,
The program block 202A and the user work RAM 203 of the game block 200A are accessed via the CPU bus 210, and necessary data (game program and contents of the user work RAM 203, etc.) are managed in the management block 200B.
Take in.

Security memory 216 (one-time P
In the ROM, a unique ID used for identifying the game processing unit 200 and determining validity is written. In addition to the unique ID, a game type code, a rank code, and a manufacturer number are stored. , And information such as a model code and an inspection number are written. The game type code is information for distinguishing a pachinko game machine, a throttle machine, and the like, and is, for example, “P” for a pachinko game machine and “G” for a throttle machine. The rank code is a model rank code of the gaming machine (a code for distinguishing the first type, the second type, and the like), a maker number, and a maker ID (or a maker code) for identifying a maker of the gaming machine. The code is the product code of the gaming machine set by the manufacturer, and the inspection number (or verification code) is the number assigned to the gaming machine that has passed the inspection by the third party.

The contents of the security memory 216 are copied to the ID property RAM 215. That is, the unique ID, the game type code, the rank code, the maker number, the model code, and the inspection number are written.
The timing of copying is when the power of the gaming machine 10 is turned on or when the system of the game processing device 200 is reset.
This is performed in the initialization processing executed in 0B. The ID property RAM 215 stores the user work RAM 20 described above.
3, a dedicated terminal (hereinafter referred to as VCAP1 for convenience) assigned to one of the terminal groups of the
The power supply backup function can be added to the game machine 10 so that the stored contents can be retained even after the power of the gaming machine 10 is turned off. VCA
The use of P1 will be described later. Management work RAM 217
Is a storage area for temporarily holding information (such as the contents of the program RAM 202 and the contents of the user work RAM 203) of the game block 200A read via the bus monitor circuit 214.

The control circuit 218 executes a predetermined sequence to control the operation of the management block 200B.
For example, the contents of the security memory 216 are copied to the ID property RAM 215 at the time of system reset (to be exact, in the initialization processing executed in the management block 200B immediately after the system reset). To detect the bus release period of the CPU core 201, read the contents of the program ROM 202 and the contents of the user work RAM 203 of the game block 200A and write them to the management work RAM 217 during the same period, and also read from the external device PJ1. The contents of the management work RAM 217 and the ID property RAM 215 are transferred to the outside in response to the management information request command. The external communication circuit 219 communicates with the above-described PJ1 (see FIG. 2).
For example, a process of transferring the stored contents of the external device to the outside is performed. The information transferred from the external communication circuit 219 to the outside may be encrypted.

FIG. 7 shows two power supply backup terminals (VCs) assigned to a terminal group of the game processing unit 200.
It is a figure showing how to use AP0 and VCAP1). As described above, VCAP0 is a power supply backup terminal of the user work RAM 203 provided in the game block 200A, and VCAP1 is a power supply backup terminal of the ID property RAM 215 provided in the management block 200B. These two terminals VCAP0, VCA
P1 can be used in any of the four patterns as shown. FIG. 7A shows two terminals VCA
This is a usage pattern of applying power (hereinafter, Vcc) to P0 and VCAP1. Vcc is a DC power supply that maintains a predetermined potential while the power of the gaming machine 10 is turned on. When used in this pattern, power (Vcc) is supplied to both the user work RAM 203 and the ID property RAM 215 only while the power of the gaming machine 10 is turned on.
215 can be used without power backup. Therefore, in this pattern, the gaming machine 10
User work RAM 20 only while the power of the
3 and the contents stored in the ID property RAM 215. In other words, when the power of the gaming machine 10 is turned off, the user work RAM 203 and the ID property RAM 21 are stored.
5 can be erased.

FIG. 7B shows two terminals VCAP0 and VCAP
This is a pattern of how to add Vcc to CAP1 and connect the capacitor C1 to VCAP0. When used in this pattern, the charging voltage of the capacitor C1 is continuously supplied to the user work RAM 203 via the VCAP0 even after the power of the gaming machine 10 is turned off, so that the power supply for the user work RAM 203 can be backed up. Therefore, in this pattern, the gaming machine 10
After the power is turned off, the stored contents of the user work RAM 203 can be kept, and the stored contents of the ID property RAM 215 can be erased when the power of the gaming machine 10 is turned off. FIG. 7C shows two terminals VCAP.
0, Vcc is added to VCAP1 and VCAP1
This is a pattern of how to connect the capacitor C2 to the capacitor.
When used in this pattern, the charging voltage of the capacitor C2 is continuously supplied to the ID property RAM 215 via the VCAP1 even after the power of the gaming machine 10 is turned off.
A power supply backup for the ID property RAM 215 can be performed. Therefore, in this pattern:
ID property RAM 215 after powering off gaming machine 10
Of the user work RAM 203 can be erased when the power of the gaming machine 10 is turned off.

FIG. 7D shows two terminals VCAP0 and VCAP.
Vcc is added to CAP1, and VCAP0 and VC
This is a usage pattern of connecting capacitors C1 and C2 to AP1. When used in this pattern, VCAP0 and VCAP1 are maintained even after the power of the gaming machine 10 is turned off.
, The charging voltages of the capacitors C1 and C2 are continuously supplied to the user work RAM 203 and the ID property RAM 215, so that power can be backed up to both the user work RAM 203 and the ID property RAM 215. Therefore, in this pattern, the user work RAM 203 and the ID are stored even after the power of the gaming machine 10 is turned off.
The content stored in the property RAM 215 can be maintained.

The capacitors C1 and C2 accumulate (charge) electric charges toward the potential of Vcc and supply (discharge) the charged electric charges to the loads (VCAP0, VCAP1) after turning off the Vcc. Functions as a battery. However, it is also possible to use a primary battery (discharge-only battery) or another battery (for example, a fuel cell) instead of C1 and C2. 7 (b) to 7 (d), Vcc and capacitor C1 (Vcc and capacitor C1).
It is desirable to insert a diode D1 (D2) between 2). If Vcc is a positive power supply, the diode D1
The anode of (D2) is connected to Vcc, and the cathode is connected to capacitor C1 (C2). Even if the potential of Vcc drops in the 0V direction when the power is turned off, the capacitor C1 (C2)
Current does not flow backward from Vcc to Vcc, and the backup terminal VC
Power can be supplied to AP0 (VCAP1) from the capacitor C1 (C2) without any trouble. It is preferable to use a Schottky type diode as the diode D1 (D2). The Schottky diode has a small forward voltage between the anode and the cathode, and the diode D
This is because a voltage drop due to insertion of 1 (D2) can be suppressed low.

FIG. 8 is a configuration diagram of a main part of the game processing device 200, showing a portion where chip select signals CS0 to CS12 are generated. As described above, the address decoder 208 fully decodes the information (16-bit address information from iA0 to iA15) on the address bus of the CPU bus 210, and as shown in FIG. When any one of the 24 I / O addresses (for example, a 24-byte address from 2300h to 2317h) which is assigned in advance to a predetermined address in the address space up to FFFFh is detected,
One I / O resource selection internal signal (one of iCS0 to iCS23) corresponding to the address is activated. For example, when address 2300h is detected, C
Activate iCS0 corresponding to S0 and set address 2
When detecting 301h, the iCS1 corresponding to CS1 is activated, and when detecting the address 2317h, the iCS23 corresponding to CS23 is activated.

As described above, the chip select controller 209 outputs the internal signals iCS0 to iCS2 for selecting 24 I / O resources from the address decoder 208.
3 and the mode designation signal CS / E from the CPU core 201.
Based on CS, 13 chip select signals CS0 to CS0
Controls the state of CS12. For example, in the CS mode, when iCS0 is active and input, the corresponding chip select signal CS0 is activated and output. When iCS1 is active and input, the corresponding chip select signal CS1 is activated and output.
When the iCS12 is active and input, the corresponding chip select signal CS12 is activated and output (in the CS mode, iCS13 to iCS23 are not used). On the other hand, in the ECS mode, similarly, when iCS0 is active and input, the corresponding chip select signal CS0 is activated and output. When iCS1 is active and input, the corresponding chip select signal CS1 is activated and output. When the iCS7 is active and input, the corresponding chip select signal CS7 is activated and output. For the iCS8 to iCS23, the four chip select signals CS8 to CS11 correspond to one of the active signals. The combination is coded and output, and the last chip select signal CS12 is fixed to active and output.

FIG. 10 shows the chip select controller 20.
9 is a configuration diagram of FIG. 13 buffers 209a, 209
b, 209c, 209d, 209e, 209f, 209
g, 209h, 209i, 209j, 209k, 209
m, 209n and five selectors 209p, 209q,
209r, 209s, 209t and one coder 209
u. 13 buffers 209a, 209b,
209c, 209d, 209e, 209f, 209g,
209h, 209i, 209j, 209k, 209m,
209n, eight buffers 209a from the top of the drawing,
209b, 209c, 209d, 209e, 209f,
209g and 209h pass through iCS0 to iCS7 through through, but the remaining five buffers 209i and 209h
09j, 209k, 209m, and 209n are the selectors 2
The signal appearing at the output (O) of 09p, 209q, 209r, 209s, 209t is passed. Selector 209
Each of p, 209q, 209r, 209s, and 209t has two input terminals AB, one output terminal O, and a selection input terminal S as shown in an enlarged view of FIG. When the logic state (state when the CS / ECS signal is in the CS mode) is set, the signal applied to the input A, i.e., iCS8 to iCS12, is taken out from the output O, and the selected input S is taken to another logic state (CS / ECS signal is When in the ECS mode, the signal applied to input B (output signal of coder 209u; selectors 209p, 209)
The selection operation of extracting B0 to B3 for q, 209r, and 209s and STB for the selector 209t from the output O is performed. Note that STB is a signal (so-called strobe signal) indicating the state determination of the 4-bit codes B0 to B3.

The coder 209u outputs 1 from I0 to I15.
When any one of the 6-bit inputs is activated, 4-bit codes B0 to B3 corresponding to the active bit positions are generated (however, when the CS / ECS signal specifies the ECS mode). Bit B0
Each of B3 has four selectors 209p, 209q, 20
9r and 209s. Also, the coder 209u outputs a 4-bit code B0 as described above.
A strobe signal STB representing the determined state of .about.B3 is extracted, and this STB is given to the input B of the fifth selector 209t. FIG. 11 is an input / output truth table of the coder 209u. When one of the 16-bit inputs I0 to I15 of the coder 209u becomes active, the 4-bit outputs B0 to B3 become "0000" to "1".
111 ".

That is, I0 (address decoder 208)
When the output iCS8) becomes active, the 4-bit outputs B0 to B3 are coded into a bit array of "0000", and when I1 (the output iCS9 of the address decoder 208) becomes active, the 4-bit outputs B0 to B3 are output. "0
001 ”, and when I2 (output iCS10 of the address decoder 208) becomes active, the 4-bit outputs B0 to B3 are coded into a bit array of“ 0010 ”and I3 (the output of the address decoder 208). When iCS11) becomes active, 4-bit outputs B0 to B3 are coded into a bit array of "0011", and I4 (output iCS12 of address decoder 208).
Becomes active, 4-bit outputs B0-B3 are coded into a bit array of "0100", and when I5 (output iCS13 of address decoder 208) becomes active, 4-bit outputs B0-B3 become "0101". It is encoded into a bit array, and I6 (address decoder 20
When the output iCS14 of the address decoder 208 becomes active, the 4-bit outputs B0 to B3 are coded into a bit array of “0110”, and I7 (the output iCS1 of the address decoder 208) is coded.
When 5) becomes active, the 4-bit outputs B0 to B3
Are coded into a bit array of “0111”, and when I8 (output iCS16 of the address decoder 208) becomes active, the 4-bit outputs B0 to B3 are coded into a bit array of “1000”, and I9 (address decoder 2)
When the output iCS17 (08) becomes active, the 4-bit outputs B0 to B3 are coded into a bit array of "1001", and I10 (output iC of the address decoder 208).
When S18) is activated, the 4-bit output B0
B3 is coded into a bit array of “1010” and I1
When 1 (the output iCS19 of the address decoder 208) becomes active, the 4-bit outputs B0 to B3 become "101".
When the I12 (the output iCS20 of the address decoder 208) becomes active, the 4-bit outputs B0 to B3 are coded into the "1100" bit array and I13 (the address decoder 208).
When the output iCS21) becomes active, the 4-bit outputs B0 to B3 are coded into a bit array of “1101”, and I14 (the output iCS2 of the address decoder 208) is coded.
When 2) becomes active, the 4-bit outputs B0 to B3
Is coded into a bit array of “1110” and I15
When the (output iCS23 of the address decoder 208) becomes active, the 4-bit outputs B0 to B3 become "111".
1 ".

Therefore, according to the chip select controller 209 of the present embodiment, the CS / ECS signal is
By setting the mode to the S mode, the thirteen signals (iCS0 to iCS12) from the address decoder 208 are passed through as they are, and the thirteen chip select signals CS0 to CS
12 can be externally output, while the CS / ECS signal is
By setting the mode, eight of the thirteen signals (iCS0 to iCS7) from the address decoder 208 are passed through as they are, and eight chip select signals CS0 are output.
It is possible to externally output to CS7, create a 4-bit signal B0~B3 with coded by 2 ^four states remaining 16 signal (iCS8~iCS22), 4 pieces of the chip select signals of the 4 bits It can be externally output as signals CS8 to CS11. As a result, in the CS mode, a maximum of 13 external I / Os can be controlled,
In S mode, it can control up to eight +2 ⁴ = 24 external I / O. In order to control a maximum of 24 external I / Os in the ECS mode, as described later, code information output from the chip select controller 209 (that is, chip select signals CS8 to CS1)
1) decodes, 2 ⁴ pieces of the expansion means for generating a chip select signal CS8'~CS23 '(see outer decoder 330 of FIG. 13) for a game processing unit 200
Must be provided outside the

FIG. 12 shows an example of the use of the chip select signals CS0 to CS12 in the CS mode. As described above, in the case of the CS mode, the thirteen chip select signals CS0 to CS1 output from the game processing device 200 are provided.
Numerals 2 correspond to individual external I / Os, respectively, and can control up to thirteen arbitrary external I / Os. Now, assuming arbitrary external I / Os 300 to 312 from the 0th to the twelfth, 13 chip select signals CS0 to CS are applied to the chip select terminals (CS) of the respective external I / Os 300 to 312.
12 may be input. Then, on the game program, for example, address 2300h (see FIG. 9)
To activate the WR signal or the RD signal, the specific chip select signal (CS0) associated with the address 2300h is activated to activate the 0th bit.
Of the external I / O 300 (when the WR signal is active) or read the signal from the 0th external I / O 300 (when the RD signal is active).
However, in the case of the CS mode, the number of control of the external I / O cannot exceed the number (13) of the chip select signals CS0 to CS12 output from the game processing device 200. As such, 15 external I /
O (five ports 113a to 113e of the input interface 113 in FIG.
For those having the ports 114a to 114i and the sound generator 115), the ECS mode is used.

FIG. 13 shows an example of using the chip select signals CS0 to CS12 in the ECS mode. The difference from the CS mode is that four of the thirteen chip select signals CS0 to CS12 output from the game processing device 200, that is, four coded chip select signals CS8 to CS11 Strobe signal (CS1
2; decoded at the timing of Fig.), With a signal expansion circuit 126 including the equivalent) 330 to the reproducing unit described in the Summary of the outer decoder (invention to generate two ^four extension chip select signal CS8'～CS23 ' On the point.

FIG. 14 is an input / output truth table of the decoder 330. This truth table is a combination of 4-bit inputs I0 to I3 [predetermined timing indicated by CS12 (determination of 4-bit output of the coder 209u). 16) from B0 to B15 according to the combination
Activate one of the outputs.
That is, a 4-bit input (chip select signals CS8 to CS8 to
When the combination of CS11) is “0000”, B0
(Extended chip select signal CS8 ') is activated and output. When the combination is "0001", B1
(Extended chip select signal CS9 ') is activated and output. When the combination is "0010", B2
(Extended chip select signal CS10 ') is activated and output. When the combination is "0011", B
3 (extended chip select signal CS11 ') is activated and output. When the combination is "0100",
When B4 (extended chip select signal CS12 ') is activated and output, and when the combination is "0101", B5 (extended chip select signal CS13') is activated and output, and when the combination is "0110" Then, B6 (extended chip select signal CS14 ') is activated and output. When the combination is "0111", B7 (extended chip select signal CS15') is activated and output, and the combination is "1000".
B8 (extended chip select signal CS16 ')
Activate and output
In the case of "1", B9 (extended chip select signal CS1
7 ') is activated and output.
010 ", B10 (extended chip select signal C
S18 ') is activated and output. If the combination is "1100", B12 (extended chip select signal CS20') is activated and output. If the combination is "1101", B13 (extended chip) is output. Select signal CS21 ') is activated and output. When the combination is "1110", B14 (extended chip select signal CS22') is activated and output. When the combination is "1111", B15 ( The extended chip select signal CS23 ') is activated and output.

It is assumed that a maximum of 24 external I / Os 300 to 323 from the 0th to the 23rd are assumed. When one external I / O is controlled, the address 2300
h to the address 2317h (see FIG. 9) to activate the WR signal or the RD signal. For example, when the address 2300h is called, the chip select signal CS0 becomes active and the 0th external I / O 300 is controlled. When the address 2307h is called, the chip select signal C0 is used.
S7 becomes active and the seventh external I / O 307 is controlled. Alternatively, when the address 2308h is called, the extended chip select signal CS8 'output from the external decoder 330 becomes active and the eighth external I
/ O 308 is controlled, and when the address 2317h is called, the extended chip select signal CS23 'output from the external decoder 330 becomes active, and the 23rd external I / O 323 is controlled.

Next, the operation will be described. First, the operation of each unit related to the determination of the validity of the game processing device 200 will be described. A description will be given, and at the end of the description of the system reset operation, a chip select operation (CS mode and ECS mode) which is a point of the present invention will be described. <Judgment Operation of Legitimacy of Processing Unit for Game 200> The judging operation of legitimacy of the processing unit for game 200 is PJ1,
PJ2, JR, JRs and game processing unit 200
Are performed in relation to each other. FIGS. 15A and 15B
7 is a flowchart showing a main routine and an interrupt routine of PJ1, respectively. The main routine of PJ1 is started when the power of PJ1 is turned on (power on). When PJ1 is powered on, first in step S1, CJ
Initialization of the PU 51, checking and initialization of the RAM 53 are performed. As a result, the CPU 51 is initialized, and the setting processing of the register in the system, the initialization of the flag, and the like are performed, and the normality determination processing of the RAM 53, the initialization of the work area, and the like are performed.

Next, a setting process is performed in step S2.
This is to set the same matching ID as the unique ID of the game processing device 200 from the setting / inspection device 23 to the PJ1. After the step S1, the setting process is performed in the step S2. Next, in step S3, a check process of the game processing unit 200 is performed. This is for determining whether or not the unique ID of the game processing device 200 is valid. That is, the game processing unit 2
00 has a unique ID (a game processing device 2
The ID stored in the security memory 216 is stored in the security memory 216, and the data stored in the security memory 216 (such as a unique ID) is copied to the ID property RAM 215. And the gaming machine 1 in the hall 1
0 is delivered, PJ1 becomes ID property RAM21
5 is periodically read out, and the setting / inspection device 2
The validity of the game processing device 200 is determined by comparing with the collation ID set from Step 3 (the detailed determination operation will be described later in a subroutine). The contents of the processing in the main routine will be described in detail in a later-described subroutine as needed. this is,
The same applies to the following steps. The same applies to other devices other than PJ1.

Next, event processing is performed in step S4. This processing and processing of each signal output from the gaming machine 10 and the like (this includes the gaming machine 10 and the game equipment. The same applies hereinafter) and the game information transferred from the PJ2.
In addition to performing a recording process, when there is a state change in the game information, the state change information is transmitted to the JR and JRs (detailed in a subroutine described later). Here, as the processed signals output from the gaming machine 10 and the game information transferred from the PJ2, for example, the time (hour and minute: the time when the game information was collected), the cumulative safe, and the cumulative Out, cumulative special prize count, cumulative probable change count, cumulative special prize safe, cumulative special prize out, cumulative probable change safe, cumulative probable change out, cumulative probable start,
Total start, total card sales, total cash sales, final start count, hit count, hit target value, final out ball count,
There are the number of times the metal frame is opened, the number of times the wooden frame is opened, the number of abnormal electromagnetic waves, and the like. In addition, the status for monitoring the state change of the game information and the contents thereof include a prize, a probability change, a detection during operation, an automatic stop, a manual stop, an out abnormal, a safe abnormal, a base abnormal, an overrun abnormal, a prize abnormal, and a special prize abnormal. , An arithmetic processing device abnormality (a bit that becomes state 1 when the unique ID of the gaming arithmetic processing device 200 is abnormal), a node abnormality (a bit that becomes state 1 when mutual authentication between terminal devices is abnormal). Mutual authentication is performed by the LON protocol), metal frame opening, metal frame opening abnormality, wooden frame opening, wooden frame opening abnormality, electromagnetic wave abnormality, empty plate detection, empty plate detection abnormality, call, and the like.

Next, in step S5, a response process to polling of game information from the HC is performed. Next, in step S6, the desired gaming machine 1 required by the HC or the CC
When it is desired to acquire game information of 0, a browsing response process for responding to the request is performed. Next, game information setting processing is performed in step S7. This is because the PJ1 operates at night while monitoring the status change information set by the HC or the CC, and the PJ1 operates at night. A process for clearing information and the like is performed. Next, in step S8, a setting / inspection device request process is performed. this is,
A request command for memory contents (RAM 53: contents of the working memory) from the setting / inspection device 23 or a request command for a reference game program stored in the ROM 52 is communicated to the game operation processing device 200, or a game operation A process of relaying information (memory contents, game program) responding to the request command from the processing device 200 to the setting / inspection device 23 is performed. The setting / inspection device 23 can be used not only at the time of the on-site inspection of the authority in the hall 1 but also at the time of performing the inspection inspection of the gaming machine 10.

After step S8, the process returns to step S3 to repeat the processing loop (steps S3 to S8). PJ1 (same for PJ2) and LON communication network 27
The (intra-island network 26, the network relay device 25, and the in-store network 24) are also operating at night, and especially the nodes (terminal devices) connected to the intra-island network 26 monitor the change in the state of the game information even at night. Therefore, by repeating the processing loop of steps S3 to S8, by acquiring each game information the next morning before the store opens, fraud can be monitored. Further, if an external communication device (for example, a facsimile device) is connected to the LON communication network 27 that is energized at night, it is possible to transmit the situation that the fraud has occurred to the outside at the time of fraud. Can be effectively dealt with.

In the interrupt routine of PJ1, FIG.
As shown in (b), an input process is performed in step S11. This is because any one of the amuse communication signal, the sales signal (card, cash), the number of supply balls, the number of collected balls, the special figure rotation signal, the big hit signal, and the positive change signal is input to the input interface 59 of the PJ1. At this time, an interrupt is triggered by the input signal as a trigger, and processing for storing the input signal is performed. The signal saved in the input processing is used in the processing of the main routine of PJ1. Next, a timer process is performed in step S12. Thereby, various timers used in the PJ1 are created, and for example, a timer of 100 ms or the like is created. After step S12, the interruption ends. In addition, PJ
The processing similar to the contents shown in FIGS. 15A and 15B is performed for No. 2, and the description is omitted here. However,
The PJ 2 transmits the state change information (for example, a metal frame opening signal, an empty plate signal, etc.) collected from the gaming machine 10 and the game equipment to the P.
The PJ1 is different from the PJ1 in that the PJ1 is transferred to a terminal device (for example, JR or JRs) of an upper node from the PJ1 and a process of inactivating the gaming machine 10 in response to a firing stop request. .

Next, a subroutine for checking the game processing unit 200 will be described. FIG. 16 is a flowchart showing a subroutine of a game processing unit check. In the process of checking the game processing device 200, related processing is performed in the game processing device 200, PJ1 and PJ2. As described above, the game processing unit 200 has a unique I
D (an ID different for each game processing device 200) is stored in the security memory 216, and data stored in the security memory 216 (such as a unique ID) is copied to the ID property RAM 215. After the gaming machine 10 is delivered to the hall 1, the setting / inspection device 23 is set in the LON communication network 27 so that it can be determined whether or not the PJ1 is a legitimate game processing device 200 based on the unique ID. Is connected to the game processing device 2
The same information (collation ID) as the unique ID stored in advance in 00 is set in PJ1 to which the gaming machine 10 is connected. In PJ1, a game processing unit 20 is provided at predetermined intervals.
0, a unique ID read command is transmitted, and the game processing device 200
The information including the unique ID copied to H.215 is PJ1
PJ1 transmits the unique ID included in the received information to the collation ID set by the setting / inspection device 23.
By comparing with, the validity of the game processing device 200 is determined. If the unique ID that can be known only by a specific person (for example, a person who stores and manages the unique ID in the game processing device 200 at the time of manufacturing) is valid, the valid game processing device 200 is valid. Is determined to be legitimate.

When judging the validity of the game processing device 200 by the program shown in FIG. 16, first, in the game processing device check process of the main routine of the PJ1, the unique ID is confirmed at predetermined intervals at step S21. It is determined whether or not it is a timing (for example, every one second). If it ’s a check timing,
In step S22, a unique ID request (for example, a unique ID read command) is transmitted to the game processing device 200 of the gaming machine 10 connected to the PJ1. This is a game control board 4 of the gaming machine 10 which is paired with PJ1 (that is, PJ1 is a check target).
This is a request for a unique ID to the gaming operation processing device 200 built in 1.

In the game processing unit 200, the external communication circuit 219 performs a process.
It is determined whether or not the unique ID request command sent from is a legitimate command information, and if not, the routine ends. Therefore, there is no response at this time. By making no response, fraud is prevented. For example, if there is any response, the response may be analyzed, so that no response is made. In short, the configuration is such that a response operation to an illegal command is not performed. In addition,
Not limited to no response, predetermined information may be returned (for example, no response is possible). By making no response in this way, analysis by an unauthorized person can be made extremely difficult.

On the other hand, if the command information is regular command information in step S23, the process proceeds to step S24, where the
It is determined whether or not the instruction is a request instruction. If not, the routine is terminated. If the command is a request for a unique ID, the unique ID request transmitted from the PJ1 is received in step S25, and the information (information including the unique ID) copied to the ID property RAM 215 is transmitted to the PJ1 in step S26. End the routine.

The unique ID is information for judging the validity of the game processing device 200, and is previously determined by the game processing device 2
00, the information to be transmitted to the PJ1 is information copied from the security memory 216 to the ID property RAM 215. The game processing unit 20
0 and the response process of the unique ID request in CP
Management block 2 without involvement of U-core 201
It is performed only by the operation of 00B. That is, the external communication circuit 219 of the management block 200B receives the unique ID request, and in response, transmits information including the unique ID copied to the ID property RAM 215 to the outside. Therefore, the process of accepting and responding to the unique ID request can be executed without affecting the operation of the CPU core 201 at all. In this way, the management block 200B independently responds to the unique ID request, so that, for example, even during the execution of the game program (that is, during the game), the unique I
There is an advantage that a security check based on D can be realized.

In PJ1, in step S27, the unique ID transmitted from the external communication circuit 219 of the game processing device 200 is received, and in step S28, the received unique ID is normal (is normal) Is determined. The unique ID for checking (collation ID) is set in advance.
Setting for PJ1 by the inspection device 23 (for example, EE
Stored in the PROM 54). Set the ID for verification
Not limited to the example set by the inspection device 23, for example, CC
It may be set by, for example,.

If it is determined in step S28 that the unique ID received from the game processing unit 200 is normal,
In step S29, the unique ID normal state is stored (for example, the bit of the game processing device abnormality in the state change information is set to "0" and stored as normal: used in step S44 of the event processing shown in FIG. 17). ) And return to the main routine. On the other hand, the game processing unit 20
When the unique ID of 0 is not normal (for example, in the case of a forged game processing device), the process proceeds to step S30 to transmit a firing stop request to the PJ2 in order to perform a measure corresponding to the abnormality of the unique ID. Step S57
To store the abnormal state of the unique ID (for example, setting the bit of the game processing device abnormality in the state change information to "1" and storing it: used in step S44 of the event processing shown in FIG. 17) and returning to the main routine. To return.

In PJ2, in the abnormality handling process, when a firing stop request is received from PJ1 in step S32, the process proceeds to step S33, in which a hitting signal is turned on for the abnormal gaming machine to stop firing the ball, and Return to routine. Thereby, the firing of the game ball in the corresponding gaming machine 10 connected to the PJ 2 is stopped, and the gaming machine 1
The operation of 0 is deactivated. Therefore, when the game processing device 200 is forged and the unique ID is not a legitimate one, the game cannot be continued and fraud can be prevented. In step S33, the firing of the abnormal gaming machine is turned off. However, the present invention is not limited to this. Is also good. In short, it is only necessary that the game cannot be executed.

Next, a subroutine relating to the event processing of PJ1 will be described. FIG. 17 is a flowchart showing a subroutine of event processing. In the course of event processing, related processing is performed in PJ1, JR, and JRs. First, in the event processing of the main routine of PJ1, an event signal confirmation processing is performed in step S41. In order to acquire game information from the gaming machine 10 and the game equipment managed by the PJ 1, the input of signals (event signals) from these terminals is first checked. That is, the PJ1 can accept the input of a sales signal (card, cash), a supply ball number signal, a collected ball number signal, a special figure rotation signal, a jackpot signal, and a probable change signal, but these signals are always input. Instead, the event is input in response to occurrence of a corresponding event (for example, when an event of lending a ball by a prepaid card occurs, a sales signal (card) is input, etc.). If an event has occurred, the reception of a signal corresponding to the event is confirmed.

Next, at step S42, the game information transmitted from the PJ2 is confirmed, and at step S43, the game information is processed and recorded based on the information transmitted. As a result, the collected information is processed into game information, and the game information for the current day is recorded (for example, the RAM 53).
Recorded on). Next, in step S44, it is determined whether there is a state change (change in status) of the game information,
If there is no change, the current routine ends and the process returns to the main routine. If there is a state change, step S45
To create state change information. As a result, the state change information having the content corresponding to the status change is created.
Next, the state change information created in step S46 is
And send (report) to the JRs, and terminate the routine.
When the JR (and JRs; hereinafter, referred to as JR) receives the notification of the state change information from the PJ1, it acquires it in step S47, and organizes and records the state change information for each gaming machine 10 in step S48. To end. afterwards,
When a request from the CC (a polling request at predetermined intervals) is received, the organized state change information is transmitted.

Next, a subroutine relating to the inspection processing of the setting / inspection device 23 will be described. FIG. 18 is a flowchart showing a subroutine of the inspection processing. In the course of the inspection processing, related processing is performed in the setting / inspection device 23, the PJ1, and the game processing device 200.
This is because the setting / inspection device 23 sends the memory contents (user work RA
In response to the request command of (the content stored in M203) or the request command of the game program stored in the program ROM 202, the arithmetic processing unit 200 for game sends to the setting / inspection device 23 via the PJ1 the response information to the request command. Is a process of notifying the user. In this case, the setting / inspection device 2
3 is used not only at the time of the on-site inspection of the authorities but also at the time of the inspection test of the gaming machine 10. for that reason,
The setting / inspection device 23 is not always installed in the hall 1.

When the inspection process is performed by the program shown in FIG. 18, first, in the inspection process routine in the setting / inspection device 23, a process of transmitting request information is performed in step S51. This means that a desired request command (contents are a memory request command and a game program command, and the request is an input by an operator) managed by the setting / inspection device 23 is transmitted to a desired game processing device 200 (that is, a game). To the PJ1 corresponding to the device 10), and waits for a response to the request for a predetermined time in step S61. In PJ1, it is determined in step S52 whether or not there is request information, and if there is no request information, the routine ends. If there is the request information, the process proceeds to step S53, where the request information is transmitted to the game processing device 200 of the gaming machine 10 which is the lower node.

The game processing unit 200 determines in step S54 whether or not the request command received from the PJ1 is valid request information. If not, the routine ends. That is, there is no response to an incorrect request command. If the request is valid, it is determined in step S55 whether or not the request command is a request for memory information (memory contents).
At 56, the current memory contents (the contents of the user work RAM 203) are transmitted to the setting / inspection device 23 via the PJ1. If it is not a request for memory information, step S
In step 57, it is determined whether the request is a game program or not. If the request is not a game program request, the routine is terminated and no response is made. On the other hand, if the request is for a game program, the process proceeds to step S58, where the game program is transmitted to the setting / inspection device 23 via the PJ1, and the routine ends.

The processes of steps S54 to S58 are independently processed so as not to hinder the execution of the game program (CPU core 201). However,
In the case of reading a game program, the operation stop state of the game program is a precondition, and the bus monitor circuit 214
Thus, the CPU bus 210 can be used by the external communication circuit 219, and the contents of the program ROM 202 can be transferred from the external communication circuit 219 to the outside using the CPU bus 210. On the other hand, when the memory contents (information of the user work RAM 203) are transferred to the outside, the user work RAM 203 is used so that the CPU core 201 can be used even during the execution of the game program.
The external communication circuit 219 is also accessible from the side. In PJ1, after transmitting the request information in step S58, a response to the request is received from the game processing device 200 in step S59, the information acquired in step S60 is transmitted to the setting / inspection device 23, and the routine ends. I do. Therefore, in this case, the PJ 1 performs a process like a relay device that performs a communication process between the game processing device 200 and the setting / inspection device 23 and a communication process with the setting / inspection device 23.

In the setting / inspection device 23, step S61
Waits for a response for a predetermined period in order to determine whether or not the corresponding request information (ie, response information to the request transmitted in step S51) has been received. If there is no response after the predetermined period, the process proceeds to step S64 to notify the abnormality. And terminate the routine. If a response is received within the predetermined period, response information (memory information response or game program response) to the corresponding request is stored in step S62, and the information is reported (for example, displayed) in step S63, and the routine ends. . In this way, the processing at the time of on-site inspection of the hall 1 using the setting / inspection device 23 or the gaming machine 1
In the test of the verification test of 0, the reading of the memory content of the game arithmetic processing device 200 or the reading of the game program is performed, and for example, it is determined whether there is any suspicious information in the memory content, the authenticity of the game program, and the like. Will be.

Next, a subroutine relating to the setting process of the setting / inspection device 23 will be described. FIG. 19 is a flowchart showing a subroutine of the setting process. In the course of the setting process, related processes are performed in the setting / inspection device 23, the PJ1, and the game processing device 200.
This is a process of setting a unique ID from the setting / inspection device 23 to the PJ 1 for monitoring when a new gaming machine 10 (that is, the game processing device 200) is delivered to the hall 1. This is a process of changing a command requested from the inspection device 23 to the game processing device 200 via the PJ1. In this case, the setting / inspection device 23
It is used by connecting to the N communication network 27.

When setting a unique ID to the PJ1, first, in the setting processing routine of the setting / inspection device 23, it is determined whether or not there is a unique ID setting request in step S71. The unique ID setting request is made by the operator inputting the setting / inspection device 23 (such as a notebook personal computer). If there is a unique ID setting request, information including the unique ID is transmitted to PJ1 in step S72, and it is determined in step S73 whether or not the setting has been completed, and the process waits. The operator of the setting / inspection device 23 is a third party organization or the like. The unique ID of the game processing device 200 provided in the new gaming machine 10 includes, for example, a management table, and the unique ID is assigned to the PJ1 based on the management table.
Is set. That is, a unique ID is set for each PJ1.

On the other hand, in PJ1, in step S81, it is monitored whether or not there is a unique ID setting request from the setting / inspection device 23. If there is a unique ID setting request, the flow proceeds to step S82 to transmit from the setting / inspection device 23. The acquired unique ID is obtained, and the unique ID is stored as a collation ID in step S83 (for example, stored in the EEPROM 54). Next, in step S84, the completion of the setting of the unique ID is transmitted to the setting / inspection device 23, and the process proceeds to step S85. As described above, the setting / inspection device 23 determines whether or not the setting is completed in step S73, and waits. When the setting completion of the unique ID is transmitted from the PJ1, the determination result in step S73 is YES. Then, the process proceeds to step S74.

In the case of performing a command change setting process for issuing a request command to the game processing unit 200, it is first determined in step S74 whether or not there is a request information change request. The operator of the third party similarly inputs this request information change request. If there is no request information change request, this routine ends. When there is a request information change request, for example, when the request instruction of the game program is “5A5A”, when it is desired to change it to “5555”,
Proceeding to step S75, the change information of the corresponding request command is input (in this case, “5A5A” → change → input of “5555”) and the information is transmitted to PJ1. As a result, the request command change information is transmitted to the game processing device 200 via the PJ1 (details will be described later). In addition, in consideration of the fact that the operator may forget the changed request command, the request command can be returned to a default value (processing steps will be described later).

In PJ1, it is determined in step S86 whether or not there is request information from the setting / inspection device 23. If there is no request information, the routine ends. With the requested information,
Proceeding to step S86, the request information is transmitted to the game processing unit 200, and a response is waited for in step S87. In the game processing device 200, the PJ1
It is determined whether or not the request information received from the server is legitimate request information. If the request information is not legitimate, the routine is terminated (no response). If the request information is legitimate request information, it is determined in step S92 whether the request command is a change in the request information. If the request information has not been changed, the routine ends (no response). If the request information has been changed, the process proceeds to step S93 to perform a change request information setting process. This is to store the change request information in the security memory 216. Information such as a unique ID is stored in the security memory 216 in advance, and after the request command is changed, change information is stored together with the information.

Next, in step S94, response information indicating that the setting change has been completed is transmitted to PJ1, and the routine ends.
The processes in steps S91 to S94 are executed by the external communication circuit 219 and the security memory 216 in the game processing device 200, and are not executed by the CPU core 201, but can be executed regardless of the operation of the game program. That is, processing is performed independently so as not to hinder execution of the game program (CPU core 201). In PJ1, as described above, step S87
In step S87, it is determined whether or not there is response information from the game processing device 200. If the response information indicating that the setting change is completed is transmitted from the PJ1, the determination result in step S87 becomes YES and the process proceeds to step S87. Proceed to S88. Step S
At 88, the response information is transmitted to the setting / inspection device 23, and the routine ends. Therefore, the PJ 1 in this case performs processing like a relay device between the game processing device 200 and the setting / inspection device 23. The setting / inspection device 23 waits for response information as to whether or not the setting change has been completed from the game processing device 200 via the PJ1 in step S76, and if there is a response, proceeds to step S77 to set the operator. The completion of the change is notified, and the routine ends. In this manner, the command for requesting the game processing device 200 is changed using the setting / inspection device 23.

When the operator forgets the changed request command, the process of returning the request command to the default value is performed by inputting a command to return to the default value as the request command in step S75 of the setting / inspection device 23. , That, P
It is transmitted to the game processing unit 200 via J1. Upon receiving the change command to the default value, the game processing device 200 changes the request command to the default value stored in advance, and transmits response information indicating the completion of the setting change to the setting / inspection device 23 via the PJ1. I do. As described above, by executing the above-described steps S75 to S77, S85 to S88, and S91 to S94, including the change of the request command and the change of the default value, the process of returning the request command to the default value is performed. Done.

<System Reset Operation of Game Operation Processing Device 200> Next, a system reset operation of the game operation processing device 200 will be described. FIG. 20 is a state transition diagram of the game processing device 200, and is 226 to 229.
Is a state, and 230 to 239 are transition lines. First, when a system reset occurs due to power-on (transition line 230), self-diagnosis and initialization processing are executed in the management block 200B (state 226), and the result is NG (transition line 23).
If it is 1), a required alarm or the like is generated, and the state shifts to the standby state. If OK (transition lines 232, 233), the management block 200B is set to the idle state (transition line 234: standby state for a management information request). And boot ROM 2
12 is executed (state 228). Then, the boot result is NG (transition line 23).
If it is 7), a necessary alarm or the like is generated and the process shifts to the standby state. If OK (transition line 238), a boot reset (generation of a start address of the game program) is generated and stored in the program ROM 202. The current game program is executed (state 229), and thereafter, every time a user periodic reset occurs (transition line 239), the game program is repeated. The transition line 235 indicates a management information request command from the external device PJ1, and the transition line 236 indicates a management information response to the PJ1.

FIG. 21 is a flowchart of the management block system reset operation executed in the state 226 of FIG. In this flowchart, when a system reset occurs, first, in step S101, the storage content of the ID property RAM 215 is set to a variable KD, and in step S102, it is checked whether valid data (significant data) is stored in the variable KD. . Now, if the ID property RAM 215 is not backed up,
That is, assuming that the capacitor C2 is not connected to VCAP1 (see FIG. 7A or FIG. 7B), the ID property RAM2 immediately after the system reset is performed.
15 is erased and becomes "undefined", the data of the variable KD in which the stored content is set is also undefined, and the result of the determination in step S102 is "N".
O ". On the other hand, assuming that the ID property RAM 215 is backed up by the power supply, that is, the case where the capacitor C2 is connected to the VCAP1 (see FIG. 7C or 7D), the system is reset. The content stored in the ID property RAM 215 immediately after is the unique I
Since the data is significant data including D, the data of the variable KD in which the stored content is set is also significant data,
As a result, the result of the determination in step S102 is "YES". Therefore, it can be said that the determination operation in step S102 is an operation of determining whether or not there is a power supply backup in the ID property RAM 215.

The result of the determination in step S102 is "YES"
In other words, if it is determined that the ID property RAM 215 has a power supply backup, the contents stored in the security memory 216 are read out in step S110, and the read out contents are set in the variable SD. In step S111, the contents of the two variables KD and SD are read out. Determine match. This judgment operation is
This corresponds to determining whether the stored contents of the ID property RAM 215 whose power is backed up and the stored contents of the security memory 216 from which the stored contents of the ID property RAM 215 are copied. If the result of this determination is “NO”, it means that the storage content of the ID property RAM 215 during power backup has changed (for example, a bit is corrupted) for some reason, and such a change in the storage content is illegal. Since it may be caused by the action, after performing the abnormality warning processing in step S112, the NG processing is performed in step S109 (state 23 in FIG. 20).
Perform 1) and end the flowchart. The abnormality alarm processing includes, for example, a notification display using a lamp or the like, a notification sound output using an electronic sound or a synthesized voice, an external output of a signal indicating abnormality, and the like. In particular, when performing external output of a signal indicating an abnormality, a pager call or E-m is used by using this signal.
It is preferable because it is possible to transmit an aile or the like, and to notify an administrator who is at home or out of the office without delay. In the NG process of step S109, the management block 200B is automatically turned off under the condition that the abnormal state is released by a valid procedure (for example, input of a predetermined authentication code or predetermined switch operation). Security memory 2
16 to the ID property RAM 215 may be executed, and then the activation may be started in the same manner as in the normal state. In this way, even if a sudden abnormal state due to noise or the like occurs, the start can be started in an emergency evacuation.

On the other hand, the determination result of step S111 is YE
In the case of S, that is, when the contents of the two variables KD and SD match, the ID property R
Since the storage content of the AM 215 has not changed at all and matches the storage content of the security memory 216, the process proceeds to step S103, where the self-diagnosis processing of the management block 200B is performed, and the self-diagnosis result is OK (step S1).
If the answer is YES in step S104), the initialization process of the management block 200B is executed in step S105. If the result of the initialization process is OK (YES in step S106), the boot is started in step S107 (see FIG. 20). State 22
8), and in step S108, the management block 200B
After the transition to the idle state (transition line 234 in FIG. 20), the flowchart ends.

Management block 2 in step S105
00B in the ID property RAM 215
The data copy to is performed. The data copy source is the security memory 216 of the management block 200B.
FIG. 22 is a conceptual diagram of copying data from the security memory 216 to the ID property RAM 215. In FIG.
Each information of the game type code, the rank code, the maker number, the model code, the inspection number, and the unique ID is copied to the AM 215.

<Chip Select Operation: CS Mode / EC
S mode> Here, in the boot process activation in step S107, the CPU core 201 executes the boot program stored in the boot ROM 212,
Various initialization processes including the operating environment of the U core 201 are performed. One of the initialization processes is to specify the CS / ECS mode. The specification of the CS / ECS mode specifies whether or not to use the extended chip select signals CS8 'to CS23'. In the case of a system having more than 13 external I / Os as in the present embodiment, the ECS is used. Specify the mode, and specify CS mode for other systems with up to 13 external I / Os.

That is, when the CS mode is designated,
An external I / O address assignment map when the ECS mode is designated can be represented as shown in FIG. In FIG. 23, addresses 2300h to 2317h are external I / O assignment candidate addresses. When one of the addresses is called on a program executed by the CPU core 201, a chip select located on the right side thereof is selected. Indicates that the signal becomes active. As can be understood from FIG.
Calling any of 300h to 230Ch, 13
One of the chip select signals CS0 to CS12 becomes active, and one external I / O can be controlled using the chip select signal. The maximum number of external I / O controls in the CS mode is 13, and this number is equal to the number of chip select signals CS0 to CS12.

On the other hand, when the ECS mode is set, 2300
When any of h to 2317h is called, one of the 24 chip select signals CS0 to CS23 becomes active, and one external I / O can be controlled using the chip select signal. The maximum number of external I / O controls in the ECS mode is 24, and this number is equal to the number of all chip select signals CS0 to CS23 including the extended chip select signal. In the ECS mode, the number of chip select signals extracted from the game processing device 200 is thirteen from CS0 to CS12, which is the same as that in the CS mode. CS
The difference from the mode is that four out of the chip select signals CS0 to CS12 extracted from the game processing device 200.
By coding the number of chip select signal CS8～CS11, in that it to have a 2 ⁴ = 16 information.

For this reason, by providing means for decoding the chip select signals CS8 to CS11 (see the external decoder 330 in FIG. 13) outside the game processing unit 200, four coded chip select signals CS8 are provided.
To CS11 can be decoded to generate 16 extended chip select signals CS8 'to CS23'.

As described above, according to the present embodiment, the eight non-coded chip select signals CS0 to CS
7 and 16 extended chip select signals CS8'-CS
23 ′ and a total of 24 chip select signals C
S0 to CS23 can be used, and the present invention can be applied to a system having a large number of external I / Os exceeding 13 as in this embodiment without any trouble. Further, according to the present embodiment, only by switching between the CS mode and the ECS mode, the usage mode of the chip select signal (ie,
In addition, the number of chip select signal terminals of the game processing unit 200 can be easily changed. Also, regardless of the CS mode or the ECS mode, the number can be kept to a smaller number (13), and a special effect of solving the problem of increasing the number of package pins can be obtained.

The number N of chip select signals in the CS mode (N = 13) and the number M of chip select signals including the extended chip select signal in the ECS mode in the embodiment (M = 24) are convenience values for explanation. Of course. At least N and M are both positive integers, and the relationship of N <M and the difference ΔN between N and M
It suffices that M has a relationship that satisfies the expression “ΔNM = 2 ^x ”.

The embodiments of the present invention are not limited to the above examples, and various modifications as described below are possible. (A) The gaming machine as a gaming machine is not limited to a pachinko gaming machine, and may be a throttle machine. (B) The gaming machine according to the present invention is not limited to a pachinko gaming machine, but can be applied to, for example, a video game machine. (C) The gaming machine as a gaming device is not limited to a real ball type, but may be a sealed ball type gaming machine. The present invention can be applied to any type of gaming machine as a gaming machine to which the present invention is applied. For example, the present invention can be applied without being limited to the types of gaming machines such as lending a ball with a magnetic card and lending a ball with an IC card. (D) The communication network in the game store is not limited to the optical communication system, LAN, LON, wireless system, infrared system, wired system, etc., as long as it can transfer game information, etc. May be used.

[0102]

According to the game processing device of the present invention, a game control means for performing game control of a game machine on a common semiconductor substrate, and an external I / O while being controlled by the game control means. Signal generation means for generating a selection signal for selecting O, wherein the signal generation means generates any one of M internal selection signals based on a signal from the game control means. Means, second signal generating means for generating, as the selection signal, a 1-bit signal corresponding to each of the N internal selection signals among the M internal selection signals, and Each bit of a signal of X bits (X is a value of ^X satisfying MN = 2X) corresponding to each of the remaining MN internal select signals excluding the N internal select signals is used as the select signal. A third signal generating means for generating a predetermined mode; A selection means for selecting whether only the output of the second signal generation means is externally output or whether both outputs of the second signal generation means and the third signal generation means are externally output based on the designation signal; A first external I / O control mode (CS mode) capable of outputting N selection signals based on a predetermined mode designation signal (CS / ECS signal), and N + X selection signals can be output A game processing device that can be used by switching to the second external I / O control mode (ECS mode) can be provided. By externally decoding X selection signals, a total of M selection signals are obtained. be able to. Therefore, a highly versatile game processing device that can be flexibly applied to systems with different numbers of external I / Os can be realized, the number of selection signal output pins can be N + X, and M-N By reducing the number of pins by -X, wasteful use in the ECS mode can be eliminated. According to the game processing device of the second aspect, in the game processing device of the first aspect, the output of the third signal generation means, which is output from the selection means, is decoded into MN pieces. Since the reproducing means for reproducing the selection signal is externally provided, the reproducing means can be applied to a system having a large number of external I / Os only by providing the reproducing means outside the game processing device. Versatility can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a game store.

FIG. 2 is a block diagram of PJ1 (game information collection device 1).

FIG. 3 is a block diagram of PJ2 (game information collection device 2).

FIG. 4 is a front view of the gaming machine.

FIG. 5 is a block diagram showing a configuration of a game control device.

FIG. 6 is a block diagram showing a configuration of a game processing unit.

FIG. 7 shows two power supply backup terminals (VCAP0 and VCA) assigned to a terminal group of the game processing device.
It is a figure showing how to use P1).

FIG. 8 is a main part configuration diagram of a game processing device including an address decoder and a chip select control.

FIG. 9 is a conceptual diagram of address assignment of external I / O.

FIG. 10 is a specific configuration diagram of a chip select controller.

FIG. 11 is a diagram showing input / output truth values of a coder included in the chip select controller.

FIG. 12 is a use state diagram of 13 chip select signals in a CS mode.

FIG. 13 is a use state diagram of 24 chip select signals in the ECS mode.

FIG. 14 is a diagram showing input / output truth values of an external decoder required in the ECS mode.

FIG. 15 is a flowchart showing a program of PJ1 (game information collection device 1).

FIG. 16 is a flowchart showing a check processing subroutine program of the game processing device.

FIG. 17 is a flowchart showing an event processing subroutine program.

FIG. 18 is a flowchart showing a subroutine program of a setting / inspection process.

FIG. 19 is a flowchart illustrating a subroutine program of a setting process.

FIG. 20 is a state transition diagram of the game processing device.

FIG. 21 is a flowchart of a system reset operation of the management block.

FIG. 22 shows an ID property RA from the security memory.
It is a conceptual diagram of data copy to M.

FIG. 23 is a diagram showing an address assignment map of external I / O in a CS mode and an ECS mode.

[Explanation of symbols]

CS0-CS12 Chip select signal (selection signal) iCS0-iCS23 (internal selection signal) 10 Gaming machine 113a-113e Port (external I / O) 114a-114i Port (external I / O) 115 Sound generator (external I / O) 200 Game processing device 201 CPU core (game control means) 208 Address decoder (signal generation means, first signal generation means) 209 Chip select controller (signal generation means,
(Second signal generating means, third signal generating means, selecting means) 330 external decoder (reproducing means)

Claims (2)

[Claims] 1. A game control means for performing game control of a game machine on a common semiconductor substrate, and a signal generation means for generating a selection signal for selecting an external I / O while being controlled by the game control means. A signal generating means for generating one of M internal selection signals based on a signal from the game control means; and N signal among the M internal selection signals. Second signal generating means for generating, as the selection signal, a 1-bit signal corresponding to each of the internal selection signals, and the remaining M-N of the M internal selection signals excluding the N internal selection signals X corresponding to each of the internal selection signals of
A third signal generating means for generating each bit of a bit (X is a value of ^X satisfying MN = 2 ^X ) as the selection signal; and a second signal generating means based on a predetermined mode designating signal. A game processing device comprising: selection means for selecting whether only an output is externally output or whether both outputs of the second signal generation means and the third signal generation means are externally output. 2. A reproducing means for decoding an output of said third signal generating means output from said selecting means to reproduce MN selection signals, externally. An arithmetic processing device for a game as described in the above.