JP2001136662A - Controller for semiconductor switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller capable of minimizing the magnitude of accident current and reducing superimposed DC current components by controlling gate signal occurrence timing properly. SOLUTION: An ignition period determining part 105 determines, for each phase arm, the ignition period of a gate signal given to each phase arm based on the quantity of electricity on the AC side of electrical power systems 1, 2 connected with a semiconductor switch 3 and the switching determination of a switching determining part 101, in addition to ordinary gate control conducted by a switching determining part 101 determining the closing and opening of the semiconductor switch 3 for each phase arm comprising the switch 3 and a gate circuit 104 giving a gate signal to each phase arm according to the switching determination of the switching determining part 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a control device for a semiconductor switch such as a thyristor switch for interconnecting a plurality of power systems including at least one of a power supply and a load.

[0002]

2. Description of the Related Art An interconnection of a power system by a semiconductor switch will be described with reference to FIG. In FIG. 16, a first power receiving / power supply system 1 and a second power receiving / power supply system 2, which are power systems including at least one of a power supply and a load, are connected via a semiconductor switch 3. The systems 1 and 2 are linked. The first power receiving / power supply system 1 includes a commercial power system 11, an interconnection transformer 12, and a general load 13, and the second power receiving / power supply system 2 includes a private power generator 21 and a private power load 22.

FIG. 17 shows a semiconductor switch 3 shown in FIG.
FIG. 3 is a three-line connection diagram, in which a semiconductor switch 3 is composed of arms of a plurality of phases, and each phase arm is composed of a switching element such as a thyristor. Specifically, the semiconductor switch 3 includes a U / X-phase thyristor arm, a V / Y-phase thyristor arm, a W / Z-phase thyristor arm, and a control device 4. Each thyristor arm is provided with a snubber circuit (not shown) for connecting a plurality of thyristors in series and protecting these thyristor elements.

FIG. 18 shows an example of a conventional control device for the semiconductor switch shown in FIG.
A description will be given with reference to the time chart of FIG. 19 and FIG. 20 showing a schematic example of voltage / current waveforms of the power receiving / power supply system at the time of occurrence of an accident.

[0005] First, the open / close determining unit 101 outputs an open circuit signal b and a close signal c of the semiconductor switch 3. The accident detection circuit 102 detects an accident that has occurred in the first power receiving / power supply system 1 and outputs a cutoff signal d of the semiconductor switch 3.
Power receiving / power supply system 1 to which semiconductor switch 3 is connected
A current transformer 5 and a transformer 6 for detecting the current / voltage of the second 2 are provided, and the current transformers 5 and 6 supply a current / voltage signal to the fault detection circuit 102. The interlock circuit 103
The closing signal b from the opening / closing determination unit 101 is passed. The closing signal b is appropriately amplified and insulated by the gate circuit 104 into an electric gate signal or an optical gate signal suitable for lighting the thyristor constituting each arm. Semiconductor switch 3
Are turned on by the gate signal a, and the semiconductor switch 3 shown in FIG. 17 is turned on.

When either the open circuit signal c from the open / close determining unit 101 or the shutoff signal from the accident detection circuit 102 is given, the output signal from the interlock circuit 103 is suppressed, and the gate signal a is suppressed. After the zero crossing of the power, the semiconductor switch 3 is turned off.

[0007] A description will be given below of how the fault detection circuit 102 causes the semiconductor switch 3 to perform a shut-off operation when a fault occurs in the first power receiving / power supply system 1.

In the prior state, the semiconductor switch 3 is in a conductive state by the closing signal b from the open / close determining unit 101, and a three-phase alternating current is flowing through the semiconductor switch 3. First
When an accident occurs in the power receiving / power supply systems 1 and 2, in addition to the fault current from the power supply of the first power receiving / power supply system 1,
An accident current flows from the power supply of the power receiving / power supply system 2 to the accident point via the semiconductor switch 3.

When an accident occurs, the AC voltage of the systems 1 and 2 decreases. The accident detection circuit 102 detects an increase in current flowing through the semiconductor switch 3 via the current transformer 5. Alternatively, the AC voltage drop is detected via the transformer 6. When the shutoff signal d is output from the accident detection circuit 102, the gate circuit 103 gives priority to the shutoff signal d over the closing signal b from the open / close determination unit 101, and suppresses the gate signal to the semiconductor switch 3.

The thyristor element constituting the semiconductor switch 3 has a characteristic that when the gate signal is lost and the passing current becomes zero, the current blocking capability is restored and the thyristor element is turned off. Therefore, after the gate signal a from the gate circuit 103 is removed by the cutoff signal d of the fault detection circuit 102, the fault current passing through the semiconductor switch 3 becomes zero and the fault current is reduced at the timing when the polarity is about to be reversed. Removed.

[0011]

In the control of such a semiconductor switch, since the semiconductor switch is handled in the same manner as a mechanical switch, there is an advantage that the cutoff speed is higher than that of the mechanical switch.

However, in the semiconductor switch, the magnitude of the peak value of the first wave up to the first zero cross of the fault current is the same as that of the mechanical switch, so that the stress on the generator, turbine and the like constituting the system is reduced. large.

Further, the fact that a large DC component is included in the fault current causes the semiconductor switch and the mechanical switch to have the same form as is apparent from FIG. 20 showing the state of the current waveform.

That is, in the conventional semiconductor switch control method, there is a problem that the responsibility of the generator for supplying the fault current becomes excessive and damage may occur. In particular, if the DC component included in the fault current is large, the instantaneous active power at the time of the fault fluctuates greatly, which may further increase mechanical stress on the generator. FIG. 20 shows the fluctuation of the instantaneous effective current.

An object of the present invention is to appropriately control the generation timing of a gate signal to be applied to each arm constituting a semiconductor switch, so that the magnitude of a fault current can be made smaller than that of a mechanical switch. Another object of the present invention is to provide a control device for a semiconductor switch that can reduce a superposed DC current component.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor switch having a normal control function.
A means for determining the timing of the ignition period from the amount of electricity of the AC system to which the AC semiconductor switch is connected is added. In addition, a gate circuit is provided for each arm in order to apply a gate signal to each arm.

That is, the present invention relates to a control device for controlling a semiconductor switch composed of a plurality of phase arms interconnecting a plurality of power systems including at least one of a power supply and a load, wherein each phase arm A closing / opening determining unit that determines closing / opening for each, a gate means for providing a gate signal to each phase arm according to the opening / closing determination from the closing / opening determining unit, and an AC side of the power system to which the semiconductor switch is connected. A lighting period determining means for determining a lighting period of a gate signal to be applied to each phase arm for each phase arm based on the amount of electricity and the opening / closing determination from the closing / opening determination unit. I do.

According to such a configuration, the ignition period can be set to a desired timing and period by appropriately setting the ignition start phase and the ignition end phase by the ignition period determining means. By supplying a gate signal with a necessary and sufficient pulse width at the timing required for semiconductor switch operation, unnecessary fault current can be prevented from flowing, reducing overcurrent from generators unrelated to faults. In addition, it is possible to reduce the stress of the generator and the like constituting the power system.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
FIG. 3 is a configuration diagram showing the first embodiment of the present invention. As shown in FIG. 1, the present embodiment employs an open / close determining unit 1 for performing a conventional gate control of a semiconductor switch.
01, an accident detection unit 102, an interlock circuit 103, and a gate circuit 104 are added with a firing period determining unit 105 for determining a firing period of each arm. Also,
To control each phase arm individually, the gate circuit 104 is used.
Are provided for each arm.

FIG. 2 shows an example of the ignition period determination unit 105. 2, a firing period determining unit 105 includes a synchronization detecting circuit 201 that obtains a synchronization signal from an AC voltage, a firing start phase setting circuit 202, a firing end phase setting circuit 203,
Firing period creation circuit 204 and ignition period creation circuit 204
And an interlock circuit 103 for inputting a firing period signal e, a semiconductor switch opening signal b, a closing signal c, or a shutoff signal d, and a gate circuit 104 for outputting a gate signal a to each arm.

For the synchronization detection circuit 102, for example,
Since it can be realized by the technique disclosed in Japanese Patent Publication No. 60-37711, description thereof will be omitted.

FIG. 3 shows an example of the internal configuration of the ignition period generating circuit 204. The firing period creation circuit 204 includes a comparison circuit 301 and a flip-flop circuit 302.

Here, the phase detection circuit 102 detects the voltage of the first power receiving / power supply system 1 to which the semiconductor switch is connected,
The signal is converted into a signal of a level suitable for the electronic circuit by the instrument transformer 6 and is taken in. From this signal, the phase detection circuit 202
Detects the phase signal f. The comparison circuit 301 in the ignition period creating circuit 204 compares the phase signal f with the ignition start setting signal g from the ignition start phase setting circuit 202, and when the voltage phase becomes equal to the ignition start phase. , The flip-flop circuit 302 is set to generate a firing period signal e. Further, the phase signal f is compared with the ignition end setting signal h from the ignition end phase setting circuit 203, and when the voltage phase becomes equal to the end phase, the flip-flop circuit 302 is reset, and the ignition period signal e To end.

The interlock circuit 103 is supplied with the closing signal b from the opening / closing determination unit 101,
When the cutoff signal d is not given, the ignition period signal e is passed. When the open circuit signal c from the open / close determination unit 101 or the cutoff signal d from the accident detection unit 102 is given, the ignition period signal e is suppressed. Such an operation can be realized by a combination of a logical product, an inverting circuit, and the like.

The firing period signal e corresponding to each arm is appropriately amplified and insulated into an electric gate signal or an optical gate signal suitable for firing a thyristor constituting each arm by the gate circuit 104 corresponding to each arm. Is done. When a gate signal a is given to a thyristor constituting each arm, the thyristor is closed, and when the gate signal a is suppressed, the thyristor is opened after waiting for a current zero cross.

From the above, the ignition start phase setting circuit 202,
By appropriately setting the firing end phase setting circuit 203, the firing period of the thyristor constituting each arm can be set to a desired timing / period.

The V / W phase is shifted from the first phase by one.
A similar operation is performed at a timing shifted by 20 ° to obtain a gate signal. For the X, Y, and Z phases, U
Similar operations are performed at timings shifted by 180 ° from the V and W phases, respectively.

Next, the operation of the present embodiment will be described. First, in the state where the gate signal a is given to the semiconductor switch 3 by the closing signal b from the opening / closing determination unit 101,
A gate signal is applied to each arm constituting the semiconductor switch 3 for a predetermined period from a predetermined phase timing every cycle. The suppression of the gate signal a is based on the open circuit signal c from the opening / closing determination unit 101 and the cutoff signal d from the accident detection unit 102, as in the conventional normal gate control.

Here, the firing period applied to the U-phase arm, that is, the timing of starting and ending the transmission of the gate signal will be described. For the V / W phase, it is 120
A similar operation is performed at a timing shifted by ° to obtain a gate signal. For the X, Y, and Z phases, U, V,
By performing the same operation at a timing shifted by 180 ° from the W phase, the ignition period can be determined for all six arms.

The present embodiment proposes a period in which a gate signal is applied to the arm of each phase. The gate signal actually applied to the thyristor constituting each arm has a wide width in which a pulse is continuously applied during the ignition period. It can be a pulse,
When a forward voltage is applied to the thyristor during the firing period, the pulse may have a narrow width necessary and sufficient for the thyristor to fire.

In the present embodiment, the transfer reference of the gate signal is set to the voltage phase of the first phase of the first power receiving / power supply system 1 as the actually measurable electric quantity. After the semiconductor switch 3 is turned on, if the current flowing through the semiconductor switch 3 starts a zero-crossing timing at which the current starts flowing through the U-phase arm or a slightly earlier timing from the zero-crossing to the U-phase, the current starts flowing. The thyristor is immediately energized when trying to do so, so that current can flow.

Generally, the power factor of the power receiving / power supply system is 1
, The phase of the current flowing through the semiconductor switch 3 is
It is almost in phase with the voltage phase of the first power receiving / power supply system 1. Therefore, the ignition start timing of the U-phase arm is the first
The voltage of the first phase of the power receiving / power supply system 1 may be set to around 0 °.

However, as will be described later, in order to reduce the fault current peak at the time of fault, the ignition start timing is such that the gate signal is generated at a timing delayed from the equivalent power supply voltage phase of the second power receiving / power supply system 2 by 0 °. give. The phase of the equivalent power supply voltage can be estimated from the generator group, the impedance existing between the generator and the load, and the amount of power flowing through the impedance. Usually, this equivalent power supply voltage phase leads the voltage phase of system 2 to supply power to the load. Therefore, the phase 0 ° of the equivalent power supply voltage is usually ahead of the phase of the zero cross of the current flowing through the semiconductor switch 3, and even if the start timing of the ignition period is set between these two phases, It does not interfere with energizing operation.

When the semiconductor switch 3 is in a closed state,
Since the voltage of the first power receiving / power system 1 and the voltage of the second power receiving / power system 2 are synchronized, the voltage phase of the equivalent voltage source of the second power receiving / power system 2 and the voltage of the first power receiving / power system 1 The relationship between the voltage phases is described in the second power receiving / power system 2
The relationship between the voltage phase of the equivalent voltage source and the voltage phase of the first power receiving / power supply system 1 is the same.

Next, the firing end timing will be described with reference to FIGS.
This will be described with reference to FIG. 3, FIG. 4 showing the timing chart, and FIG. 5 showing a schematic current / voltage waveform at the time of an accident.

First, the first power receiving / power supply system 1
Assuming that the direction toward the power receiving / power supply system 2 is a positive direction,
The role of the U-phase arm is to supply this positive current. From the second power receiving / power supply system 2, the first power receiving /
As for the current flowing in the reverse direction toward the power supply system 1, the X arm is energized. Therefore, even if the firing period of the U-phase arm is limited to within the current energizing period in the positive direction, the operation of the semiconductor switch 3 is hindered. Also, even if the gate signal a is output to the U-phase arm during a period other than this period, the current cannot flow and is meaningless due to the characteristics of the thyristor because the direction of the current is opposite to the U-phase arm. .

As described above, the gate signal of the U-phase arm may be terminated at the time of zero crossing where the current in the positive direction ends.

As a characteristic of the thyristor, the energization state continues as long as the forward current continues to flow after the gate signal is applied. Therefore, the firing period end timing may be earlier than the above-described forward current end timing. Further, even if the U-phase ignition period is terminated before the X-phase ignition period start timing in which a current in the direction opposite to the U-phase flows, the semiconductor switch 3
There is no hindrance to the power supply function. The same applies to the case where the ignition period end timing is further earlier than the phase 180 ° of the corresponding phase of the equivalent power supply voltage of the second power receiving / power supply system 2 in order to reduce the accident current peak described later.

When the firing period is determined so that the U-phase firing period and the X-phase firing period do not overlap each other, the U-phase
The X-phase firing periods are each less than 180 °. Further, the same determination can be made for other V / Y phases and W / Z phases.

The operation of the semiconductor switch 3 when an accident occurs in the first power receiving / power supply system 1 while controlling the gate signal as described above will be described. For the sake of simplicity of explanation, the accident that occurred was a three-phase short circuit.

It is assumed that the accident occurs at the peak of the forward current flowing through the U-phase arm. In a normal system, the load currents are balanced in three phases, so that reverse currents flow in the second and third phases of the semiconductor switch 3, and Y
The phase and the Z phase are each energized. When an accident occurs, the first
Since the anode voltage of the U-phase arm connected to the power receiving / power supply system 1 becomes zero and the cathode voltage connected to the second power receiving / power supply system 2 continues to be the voltage from the power supply of the second power receiving / power supply system 2, It remains positive.

Accordingly, the U-phase arm current rapidly decreases and becomes zero. Since this timing is a period during which no current flows through the X-phase arm, it is not a firing period of the X-phase arm, so that the gate signal a is not supplied, and the X-phase arm continues to be in a non-conductive state. Therefore, the reverse current flowing from the second power receiving / power supply system 2 to the first power receiving / power supply system 1 via the X-phase arm is blocked.

Similarly, for the other phases, the current flowing in the Y and Z phases decreases to zero, and the second power receiving / power supply system 2
The current flowing into the fault point from is blocked.

After a while, the shutoff signal d is output from the accident detecting unit 102, the gate signals a to all the phase arms are suppressed, and the shutoff state of the semiconductor switch 3 is continued.

On the other hand, in the conventional control, since the gate signal a is continuously supplied to the X-phase arm, the X-phase arm flows a reverse current, and the second power receiving / power supply system 2 causes an accident at the accident point. Electric current flows. This current is blocked after the interruption signal d from the accident detection unit 102 is given. At the timing when the cutoff signal d is given, the reverse current has already started to flow, and the peak value of the first wave of the fault current has the same magnitude as that of the cutoff by the mechanical switch. That is, the reverse current block operation of the present invention is different from the conventional control method in that the reverse current block operation is instantaneously performed without the operation of the accident detection unit.

As described above, according to the present embodiment, an unnecessary fault current is prevented from flowing by supplying a gate signal having a necessary and sufficient pulse width at a timing necessary for the operation of the semiconductor switch 3. Thus, overcurrent from the generator irrelevant to the accident can be reduced, and the stress on the generator can be reduced.

In the present embodiment, an example in which the phase reference signal is created from the voltage signal of the first power receiving / power supply system 1 has been described. However, after the semiconductor switch 3 is turned on, the first power receiving / power supply is turned on. Since the system 1 and the second power receiving / power supply system 2 are synchronously interconnected, a similar effect can be obtained even if the voltage signal of the second power receiving / power supply system 2 is used.

When an accident occurs in the second power receiving / power supply system 2, the voltage of the second power receiving / power supply system 2 is lost, but the gate signal is suppressed by the accident detecting unit immediately thereafter, which is a substantial problem. There is no.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
It is a lineblock diagram of an embodiment. This embodiment is an example of a circuit configuration having a forward voltage detection circuit 7 in each arm in addition to the configuration in FIGS. FIG. 7 shows a configuration example inside the gate circuit.

The present embodiment is an example of a circuit configuration including a pulse interlock circuit 401 and a pulse shaping circuit 402 in addition to a simple insulating / amplifying function.

The operation of the present embodiment will be described.

In the present embodiment, the operation up to the generation of the firing period signal e is the same as that shown in FIGS. 2 and 3, and a description thereof will be omitted, and the generation of the gate signal e after the generation of the firing period signal will be described. explain.

The current flowing through each arm is connected in parallel with the thyristor constituting each arm of the semiconductor switch 3 in order to keep flowing due to the inertia of the inductance existing in the current route even when the semiconductor switch 3 is open. A snubber circuit or the like (not shown) is charged, and a forward voltage is applied to the thyristor. The forward voltage detection circuit 7 detects the forward voltage and outputs a forward voltage signal I to the pulse interlock circuit 401 in the gate circuit 104.

As soon as the forward voltage signal I is generated while the firing period signal e is being supplied to each arm, a signal is output from the pulse interlock circuit 401, and the thyristor is fired from the pulse shaping circuit 402. An appropriate gate signal e is output. FIG. 2 and FIG. 3
Therefore, the description is omitted.

By performing such an operation, the operation shown in FIGS.
The same operation as that of the embodiment can be obtained.

According to the present embodiment, the same effects as those of the configurations shown in FIGS. 2 and 3 can be obtained.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
It is a lineblock diagram of an embodiment. The present embodiment is the same as the examples of FIGS. 2 and 3 except that the ignition period is determined by the one-shot circuit 303.

The operation of the present embodiment will be described.

In this embodiment, the ignition start timing is output from the comparison circuit 301 when the synchronizing signal f and the ignition start setting signal g match, as in the examples of FIGS. The output signal of the comparison signal 301 is introduced to the one-shot circuit 303, and the one-shot circuit outputs the firing period signal e for a predetermined period from the timing.

The subsequent operation is the same as in FIGS.
The same effect is obtained.

In this configuration, the same effects as in the configurations of FIGS.

Although the present embodiment has been described with respect to an example in which the gate signal is continuously output during the firing period, a necessary gate signal is output when a forward voltage is applied, as in FIGS. Of course, the same operation and effect can be obtained with the configuration.

(Fourth Embodiment) FIG. 9 shows a fourth embodiment of the present invention.
It is a lineblock diagram of an embodiment. In the present embodiment, in the configuration shown in FIGS. 2 and 3, the gate signal width is set to less than 60 °, and a gate signal is simultaneously supplied to two arms in which an interconnection current flows between the two systems in pairs. This is a configuration in which a circuit 205 is provided.

The operation of the present embodiment will be described.

The basic operation is the same as that of the embodiment shown in FIGS. However, in order to set the firing period to less than 60 °, the firing end setting signal h is different in that the firing period is set to be less than 60 °.

The current flowing between the two systems is typically 3
If phase equilibrium is assumed, the U-phase arm starts energizing and
After elapse, the firing period of the Z-phase arm, which is the next energized phase, starts. At this time, in the steady state, since the U-phase arm is already energized, the current flowing from the first power-receiving / power-supply system 1 to the second power-receiving / power-supply system 2 by the U-phase arm without a gate signal is supplied. Since the Z-phase arm is closed, current can circulate from the second power receiving / power supply system 2 to the first power receiving / power supply system 1 through the Z-phase arm.

However, at the time when the closing signal b is supplied to the semiconductor switch 3, when starting firing from the Z-phase arm, it is assumed that a gate signal is supplied only to the Z-phase arm. The closing of the Z-phase arm attempts to form a current flow path from the second power receiving / power supply system 2 to the first power receiving / power supply system 1. However, if a gate signal is not supplied to the U-phase arm, the power receiving / power supply When the system is not grounded, a flow path in the reverse direction cannot be secured, and the semiconductor switch 3 cannot flow current.

In the configuration shown in FIG. 9, since pulses are always applied simultaneously to the thyristors of the two phases, the first power receiving / power supply system 1 passes through the second power receiving / power supply system 2 again, and then returns to the first power receiving / power supply system 1 again. Is formed, and the semiconductor switch 3 can be smoothly closed.

As described above, according to the present embodiment, effects similar to those of the first embodiment can be obtained. In particular,
When the power supply system has a non-grounded configuration, the interconnection by the semiconductor switch 3 can be started smoothly.

In the present embodiment, an example has been described in which the phase reference signal is created from the voltage signal of the first power receiving / power supply system 1. However, after the semiconductor switch is turned on, the first power receiving / power supply system 1 Since the second power receiving / power supply system 2 is synchronously connected to the second power receiving / power supply system 2, the same effect can be obtained even when the voltage signal of the second power receiving / power supply system 2 is used.

When an accident occurs in the second power receiving / power supply system 2, the voltage of the second power receiving / power supply system 2 is lost, but the gate signal is suppressed by the accident detecting unit immediately after that, so that there is a substantial problem. There is no.

Further, the configuration example in which the gate signal is continuously supplied during the ignition period has been described. However, similarly to FIGS. 6 and 7, the configuration in which the gate signal is supplied when a forward voltage is applied to the arm during the ignition period is also possible. The same operation and effect can be obtained.

(Fifth Embodiment) FIGS. 10 and 11 are configuration diagrams of a fifth embodiment of the present invention. The present embodiment uses a configuration in which the semiconductor switch 3 and the reactor are connected in series in order to interconnect the first power receiving / power supply system 1 and the second power receiving / power supply system 2. Also in this configuration, similarly to the configuration including only the semiconductor switch 3, control can be performed by the control configuration examples of FIGS.

The operation of the present embodiment will be described.

FIG. 10 differs from FIG. 1 in that there is a reactor 8 in series with the semiconductor switch 3, so that when the first power receiving / power system 1 supplies active power to the second power receiving / power system 2, the first power receiving / power system 2 The voltage phase of the power supply system 1 leads the voltage phase of the second power receiving / power supply system 2. Furthermore, as shown in the vector diagram of FIG. 12, the phase of the current flowing through the semiconductor switch 3 and the reactor 8 is intermediate between the voltage phases of the two systems.

Accordingly, the ignition start phase setting circuit 202 in FIG. 2 is set so that the ignition period start timing applied to the semiconductor switch 3 is applied at a timing slightly advanced from the voltage phase 0 ° of the second power receiving / power supply system 2. Good. Also,
The firing period end timing is determined by the second power receiving / power system 2
By setting the ignition end setting circuit 203 so as to be earlier than the equivalent power supply phase of 180 °, it is possible to realize a desired ignition timing of the ignition timing.

Therefore, similarly to the embodiment shown in FIGS. 2 and 3, even if an accident occurs in the first power receiving / power supply system 1,
The accident current can be reduced, and the stress on the generator of the second power receiving / power supply system 2 can be reduced.

Further, even if an accident occurs in the second power receiving / power supply system 2, if the inductance value of the reactor 8 connected in series with the semiconductor switch 3 is appropriately selected,
It is possible to reduce the fault current flowing from the first power receiving / power supply system 1 to the fault point, and it is possible to reduce the voltage drop of the first power receiving / power system 1 and the stress of the generator.

As described above, according to the present embodiment, the same effects as those of the embodiments of FIGS. 2 and 3 can be obtained. Accident spillover can be reduced.

In the present embodiment, an example in which the synchronization signal f is created from the voltage signal of the first power receiving / power supply system 1 has been described.
If the inductance value of the reactor and the magnitude of the flowing current are known, the phase difference between the first power receiving / power system 1 and the second power receiving / power system 2 is determined. Obviously, the timing of the gate signal applied to the semiconductor switch 3 can be determined even if it is used.

Although the configuration example in which the gate signal is continuously supplied during the ignition period has been described, the configuration in which the gate signal is supplied when a forward voltage is applied to the arm during the ignition period, as in FIGS. The same operation and effect can be obtained.

(Sixth Embodiment) FIG. 13 is a configuration diagram of a sixth embodiment of the present invention. This embodiment has a configuration in which a transformer is added in the embodiment of FIG. 11 in order to set the voltage for synchronous detection to the inter-electrode voltage in which the semiconductor switch 3 and the reactor 8 are connected in series.

The operation of the present embodiment will be described.

The phase relationship between the current flowing through the semiconductor switch 3 and the reactor 8 and the voltage appearing in the reactor 8 lags behind the voltage by 90 °. Therefore, the ignition period start timing given to the semiconductor switch 3 is 90 ° from the voltage appearing between the electrodes.
The ignition start position setting circuit 202 in FIG. 2 may be set so as to be provided near the delay timing.

The ignition end phase setting circuit 203 of FIG. 2 is similarly set so that the ignition period end timing is earlier than the phase of the interelectrode voltage of 270 °. A period can be realized.

With such a configuration, the same operation as that of the embodiment shown in FIG. 11 can be realized.

As described above, in this embodiment, the same effects as those in the embodiment of FIG. 11 can be obtained.

Although the present embodiment has shown the configuration example in which the gate signal is continuously supplied during the ignition period, the gate signal is supplied when a forward voltage is applied to the arm during the ignition period, as in FIGS. The same operation and effect can be obtained as a configuration.

(Seventh Embodiment) FIGS. 14 and 15 are configuration diagrams of a seventh embodiment of the present invention. This embodiment is the same as the embodiment of FIG. 11 or FIG. 12, except that the output signal from the forward voltage detecting unit 7 for detecting the forward voltage applied to the series configuration of the semiconductor switch 3 and the reactor 8 is output during the ignition period. This is a configuration for inputting to the determination unit 105. Firing period determination unit 105
Are the on-delay circuit 304 and the one-shot circuit 303
Consists of

The operation of the present embodiment will be described.

The operation of this embodiment will be described by taking a U-phase arm as an example.

The forward voltage detector 7 detects that the voltage applied to the U-phase arm and its series reactor has become forward for the U-phase arm, and a forward voltage signal i is output. In the ignition period determination unit 105, the on-delay circuit 30
By the operation 4, a signal having a timing delayed by an electrical angle of 90 ° is created and given to the one-shot circuit 303. If a desired value is set as the pulse width of the one-shot circuit 303, a gate signal can be output only for a desired firing period.

According to the present embodiment, the gate signal is not output at the moment when the forward voltage is applied, and the output of the gate signal is started after a time corresponding to the electrical angle of 90 ° has elapsed. By doing so, the DC component of the current flowing through reactor 8 can be suppressed. In other words, when a gate signal is immediately applied to the corresponding arm of the semiconductor switch at the moment when a voltage is applied to the reactor 8, a DC component is superimposed on the current flowing through the reactor 8, and unnecessary power fluctuation occurs. However, according to the present configuration, since the current starts to flow through the reactor 8 near the voltage peak, the DC component can be reduced.

Further, even if an accident occurs in the first power receiving / power supply system 1 or the second power receiving / power supply system 2 and the phase of the voltage fluctuates, the gate signal can always make the DC component of the current flowing through the reactor 8 available. Since it is generated at a timing that does not occur as long as possible, the DC component of the fault current is hardly generated. Therefore, the zero cross of the fault current appears in about 1/2 cycle, and since the gate signal to the semiconductor switch has already been suppressed by the signal from the fault detection unit, the fault current can be cut off in about 1/2 cycle.

Since the DC component of the fault current hardly occurs,
The peak value of the fault current can be reduced, and the stress of the circuit breaker through which the fault current passes and the generator supplying the fault current can be reduced.

As described above, according to the present embodiment, the same effect as that of the embodiment of FIG. 6 can be obtained.

In the above description, a thyristor element, which is a typical example of a semiconductor switch, has been described as an example. However, any element that can constitute a switch may be used. For example, a transistor, a triac, GT
O, IGBT, etc. may be used.

Although the number of AC phases will be described with three phases, the present invention can be applied to a case where the number of phases is other than three.

Further, in the above example, two power receiving / power supply systems have been described, but the present invention can be similarly applied to three or more systems.

[0100]

As described above, according to the present invention, by supplying a gate signal of a semiconductor switch at an appropriate timing for a predetermined period, the same energizing function as that of the related art can be realized. The fault current peak value can be reduced.

Further, in the configuration in which the semiconductor switch and the reactor are connected in series, the fault current is further reduced by the reactor, and the DC current component is reduced by controlling the phase of the semiconductor switch. Therefore, the peak value of the fault current is reduced. be able to.

Therefore, by applying the present invention to a power receiving / power supply system as a power system, it is possible to reduce stress on equipment such as a generator and to reduce voltage drop when an accident occurs.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a semiconductor switch control device according to the present invention.
FIG. 1 is a configuration diagram showing an embodiment.

FIG. 2 is a configuration diagram showing details of a roll call period determination unit in FIG. 1;

FIG. 3 is a configuration diagram showing details of a roll call period creation circuit in FIG. 2;

FIG. 4 is a waveform chart showing the operation timing of the semiconductor switch according to the embodiment.

FIG. 5 is a diagram showing an example of an operation waveform at the time of an accident when the embodiment is applied.

FIG. 6 shows a second embodiment of the semiconductor switch control device according to the present invention.
FIG. 1 is a configuration diagram showing an embodiment.

FIG. 7 is a configuration diagram showing details of a gate circuit in FIG. 6;

FIG. 8 shows a third embodiment of the semiconductor switch control device according to the present invention.
FIG. 1 is a configuration diagram showing an embodiment.

FIG. 9 shows a fourth embodiment of the semiconductor switch control device according to the present invention.
FIG. 1 is a configuration diagram showing an embodiment.

FIG. 10 is a diagram showing a link system using a semiconductor switch and a reactor to which a fifth embodiment of the control device for a semiconductor switch according to the present invention is applied;

FIG. 11 is a configuration diagram showing a fifth embodiment of the semiconductor switch control device according to the present invention.

FIG. 12 is a view showing the operation of the embodiment.

FIG. 13 is a configuration diagram showing a sixth embodiment of the semiconductor switch control device according to the present invention.

FIG. 14 is a configuration diagram showing a seventh embodiment of a control device for a semiconductor switch according to the present invention.

FIG. 15 is a configuration diagram showing details of a roll call period creation circuit in FIG. 14;

FIG. 16 is a diagram showing an example of a coordination system to which a conventional semiconductor switch control device is applied.

FIG. 17 is a diagram showing a three-phase connection of a conventional semiconductor switch.

FIG. 18 is a diagram showing an example of a conventional semiconductor switch control device.

FIG. 19 is a diagram showing an example of operation waveforms of a semiconductor switch by a conventional control device.

FIG. 20 is a diagram showing an example of operation waveforms in the event of an accident of a semiconductor switch by a conventional control device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st power receiving / power supply system 1, 2 ... 2nd power receiving / power supply system 2, 3 ... semiconductor switch, 4 ... control device, 5 ... current transformer, 6 ... transformer, 7 ... forward voltage detector, 8 ... Reactor, 11: Commercial power system, 12: Power receiving transformer, 13: General load, 21: Self-generated, 22: Self-generated load, 101: Open / close determination unit, 102: Accident detection unit, 103: Interlock circuit, 104 ... Gate circuit, 105: ignition period determination unit, 201: synchronization detection circuit, 202: ignition start phase setting circuit, 203: ignition end phase setting circuit, 204: ignition period creation circuit, 301: comparison circuit, 302 ... Flip-flop circuit, 303: one-shot circuit, 304: on-delay circuit, 401: pulse interlock circuit, 40
2 ... Pulse forming circuit

Claims (19)

[Claims] 1. A control device for controlling a semiconductor switch including a plurality of phase arms interconnecting a plurality of power systems including at least one of a power supply and a load, wherein each of the phase arms is closed and opened. A closing / opening determining unit for determining the open / close determination from the closing / opening determining unit; a gate means for providing a gate signal to each of the phase arms in accordance with the open / close determination from the closing / opening determining unit; A switch-on period determining means for determining a switch-on period of a gate signal to be applied to each phase arm for each phase arm based on an open / close determination from a close / open determination unit. Control device. 2. The ignition period determining means includes means for setting the ignition periods of the arms connected in antiparallel to each other in the phase arms so that the ignition periods of the arms do not overlap with each other. The control device for a semiconductor switch according to claim 1. 3. The semiconductor switch control device according to claim 1, wherein said ignition period determining means includes means for setting the ignition period of each phase arm to an electrical angle of less than 180 °. . 4. The ignition period determining means divides the ignition period of each of the phase arms into two or more, sets one ignition period related to the division to an electrical angle of less than 60 °, and 2. The control device for a semiconductor switch according to claim 1, further comprising: means for simultaneously providing a gate signal to an arm to be energized in pairs with an arm to which a gate signal for one ignition period is applied. 5. The ignition period determining means includes means for setting an ignition period start timing of each phase arm to a phase near a current zero cross point at which each phase arm starts to flow current. The control device for a semiconductor switch according to claim 1. 6. The ignition period determining means sets the ignition period start timing of each phase arm to a position near the phase of 0 ° of each phase arm of an equivalent power supply of a power system on the power supply side. The control device for a semiconductor switch according to claim 1, further comprising: 7. The ignition period determining means sets the ignition period start timing of each phase arm near the phase 0 ° of each phase arm of the equivalent power supply of the power system to which power is supplied. The control device for a semiconductor switch according to claim 1, further comprising: 8. The ignition period determining means includes means for estimating a phase of each phase arm of the equivalent power supply from an equivalent power supply impedance in the power system and power flowing between AC voltage detection points. The control device for a semiconductor switch according to claim 6 or 7, wherein: 9. The ignition period determining means sets the ignition period start timing of each phase arm to a phase of 0 ° of a corresponding phase of an equivalent power supply of a power system to which power is supplied and a semiconductor switch in a conductive state. 2. The control device for a semiconductor switch according to claim 1, further comprising means for setting a value between a current zero cross point at which each phase arm of the semiconductor switch starts flowing a current. 10. The ignition period determining means sets the ignition period end timing of each phase arm constituting a semiconductor switch to a phase of a corresponding phase of an equivalent power supply of a power system to which power is supplied to 180 °. 2. The control device for a semiconductor switch according to claim 1, further comprising means for setting before the start. 11. The ignition period determination means sets the ignition period end timing of each phase arm constituting the semiconductor switch before the vicinity of the current zero crossing where the current flowing through each phase arm of the semiconductor switch ends. 2. The control device for a semiconductor switch according to claim 1, further comprising: 12. The ignition period determining means comprises means for obtaining a reference phase of the ignition period from a voltage of a power supply side power supply system via a semiconductor switch. A control device for a semiconductor switch as described in the above. 13. The ignition period determining means includes means for obtaining, via a semiconductor switch, a reference phase of an ignition period start timing from a voltage of a power system to which power is supplied. The control device for a semiconductor switch according to claim 1. 14. An interconnection comprising a semiconductor switch comprising a plurality of phase arms interconnecting a plurality of power systems including at least one of a power supply and a load, and a reactor connected in series to the switch. In the system, means for giving a gate signal to a plurality of phase arms to make the semiconductor switch conductive is: opening / closing determining means for determining opening / closing of each phase arm; and electric quantity of an AC system to which the semiconductor switch is connected. A switch-on period determining means for respectively determining a switch-on period for applying a gate signal to each phase arm from the semiconductor switch. 15. The ignition period determining means sets the ignition period start timing between the AC voltage phase 0 ° of the power supply side power system and the AC voltage phase 0 ° of the power supply side power system. 15. The control device for a semiconductor switch according to claim 14, further comprising means for setting an intermediate value. 16. The ignition period determining means includes means for setting the ignition period start timing to around 0 ° of the AC voltage phase of the power system on the power supply side. 15. The control device for a semiconductor switch according to claim 14. 17. The ignition period determining means includes means for setting an ignition period start timing to about 0 ° of an AC voltage phase of a power system to which power is supplied. 15. The control device for a semiconductor switch according to claim 14. 18. The ignition period determining means according to claim 1, wherein when the semiconductor switch is activated, when a gate signal is first supplied, a delay of about 90 ° with respect to a voltage phase applied between one arm poles constituting the semiconductor switch. 15. The control device for a semiconductor switch according to claim 14, further comprising means for starting ignition in a phase. 19. The ignition period determining means starts ignition at a timing about 90 ° electrical angle delayed from a timing when a forward voltage is applied between one arm poles constituting the semiconductor switch when the semiconductor switch is activated. 15. The control device for a semiconductor switch according to claim 14, further comprising means for starting the operation.