JP2001135081A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which generates stable internal power source potential and is small in layout area. SOLUTION: In a VPP generating circuit of a SDRAM, when at least one side out of an active level detecting signal ϕ2 and a standby level detecting signal ϕ3 is a 'H' level, an active pump control circuit 4 makes a signal ϕ4 a 'H' level, and puts charge pumps 6a-6d, 7a-7d into an operable state. Even when only one bank is activated for a long time and the signal ϕ2 is not varied keeping a 'L' level, since the signals ϕ3, ϕ4 are made a 'H' level, the charge pump 6a-6d, 7a-7d are put into an operable state. Thus, a boosting potential VPP is stabilized, and pool capacity 10, 11 may be small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an internal circuit having a standby state and an active state.

[0002]

FIG. 19 shows a conventional synchronous DRAM.
FIG. 1 is a block diagram illustrating a schematic configuration of an SDRAM (hereinafter, referred to as an SDRAM). In FIG. 19, this SDRAM comprises a clock buffer 101, a control signal buffer 102, an address buffer 103, a mode register 104, a control circuit 10
5, four memory arrays 106 to 109 (banks # 0 to # 0)
# 3), and an I / O buffer 110.

A clock buffer 101 is activated by an external control signal CKE, and transmits an external clock signal CLK to a control signal buffer 102, an address buffer 103 and a control circuit 105. Control signal buffer 10
2 are synchronized with the external clock signal CLK from the clock buffer 101 to output the external control signals / CS, / RAS, /
CAS, / WE, and DQM are latched and applied to the control circuit 105. The address buffer 103 latches the external address signals A0 to Am (where m is an integer of 0 or more) and the bank selection signals BA0 and BA1 in synchronization with the external clock signal CLK from the clock buffer 101, and controls the control circuit. Give to 105.

A mode register 104 stores a mode designated by external address signals A0 to Am and the like.
An internal command signal corresponding to the mode is output. Each of the memory arrays 106 to 109 is arranged in a matrix,
Each memory cell includes a plurality of memory cells each storing 1-bit data. The plurality of memory cells are grouped in advance by n + 1 (where n is an integer of 0 or more).

The control circuit 105 includes a clock buffer 10
1, control signal buffer 102, address buffer 103
And various internal signals are generated in accordance with signals from mode register 104 to control the entire SDRAM. Control circuit 105 controls the four memory arrays 10 according to bank select signals BA0 and BA1 during the write operation and the read operation.
Selecting one of the memory arrays from 6 to 109;
According to the address signals A0 to Am, n + 1 memory cells in the memory array are selected. Selected n +
1 is activated and the I / O buffer 110 is activated.
Is combined with

The I / O buffer 110 converts the data D0 to Dn input from the outside during the write operation to the selected n + 1
And at the time of a read operation, read data Q0 to Qn of n + 1 memory cells are output to the outside.

FIG. 20 shows the memory array 1 shown in FIG.
FIG. 12 is a circuit block diagram showing a configuration of a part of a part 06 and a part related thereto. In FIG. 2, the memory array 106
It includes a plurality of memory cells MC arranged in a matrix, a word line WL provided corresponding to each row, and a bit line pair BL, / BL provided corresponding to each column. Memory cell M
C is a well-known device including an N-channel MOS transistor for access and a capacitor for storing information.

A row decoder 111, a column decoder 112 and a sense amplifier + input / output control circuit 113 are provided corresponding to the memory array 106. The sense amplifier + input / output control circuit 113 includes a data input / output line pair IO, / IO, a column selection gate 114 provided for each column of the memory array 106, a sense amplifier 115, and an equalizer 116.
And

Column select gate 114 includes a pair of N-channel MOS transistors connected between bit line pair BL, BL of the corresponding column and data input / output line pair IO, / IO. The gate of each N-channel MOS transistor is connected to column decoder 112 via a corresponding column selection line CSL. When column select line CSL is raised to the selected level of "H" level by column decoder 112, an N-channel MOS
The transistor is turned on, and the bit line pair BL, / BL is coupled to the data input / output line pair IO, / IO.

In response to sense amplifier activation signals S0N and ZS0P attaining an "H" level and an "L" level, respectively, sense amplifier 115 provides bit lines BL and //.
The small potential difference between the BLs is amplified to the power supply voltage VCC. The equalizer 116 equalizes the potentials of the bit lines BL and / BL to the bit line potential VBL in response to the activation of the bit line equalizing signal BLEQ to the “H” level.

The row decoder 111 receives a row address signal RA
According to 0 to RAm, one word line WL of the plurality of word lines WL is raised to the selected level “H”. Column decoder 112 includes column address signals CA0 to CA
According to m, one column select line CSL of the plurality of column select lines CSL is raised to the selected level “H”.

Next, the SDR shown in FIGS.
The operation of the AM will be described. In SDRAM,
For example, at the rising edge of external clock signal CLK, external control signals / CS, / RAS,.
0 to Am etc. are taken in. Address signals A0 to Am
Are row address signals RA0-R multiplexed in a time-division manner.
Am and column address signals CA0-CAm.

At the time of a read operation, first, bit line equalize signal BLEQ falls to the inactive level of "L" level, and equalizer 116 is inactivated and bit lines BL,
/ BL is stopped. Row decoder 111
Raises the word line WL of the row corresponding to the row address signals RA0 to RAm to the selected level “H”. The potentials of bit lines BL and / BL are set to the level of activated memory cell M
It changes by a very small amount according to the charge amount of the capacitor of C.
Next, sense amplifier activation signals S0N and ZS0P attain "H" level and "L" level, respectively, and sense amplifier 115 is activated.

When the potential of bit line BL is slightly higher than the potential of bit line / BL, the potential of bit line BL is raised to "H" level, and the potential of bit line / BL is lowered to "L" level. Will be reduced. Conversely, bit line / BL
Is higher than the potential of bit line BL by a small amount, the potential of bit line / BL is raised to "H" level and the potential of bit line BL is lowered to "L" level.

Next, column decoder 112 raises column selection line CSL corresponding to column address signals CA0-CAm to the selected level "H" for a certain period of time, and makes column selection gate 114 of that column conductive. Data of the bit line pair BL, / BL of the selected column is applied to I / O buffer 110 via column select gate 114 and data input / output line pair IO, / IO, and externally provided by I / O buffer 110. Is output. Next, the word line WL is lowered to the “L” level of the non-selection level, the sense amplifier 115 is deactivated, the equalizer 116 is activated, and the bit line B
L and / BL are equalized to the bit line potential VBL, and preparation for the next read operation is completed.

In the write operation, after the equalizer 116 is inactivated, the word line WL corresponding to the row address signals RA0 to RAm is raised to the selected level "H" level by the row decoder 111 and the memory cell MC is activated, and the sense amplifier 115 is activated. Column decoder 1
Numeral 12 raises the column selection line CSL corresponding to the column address signals CA0 to CAm to the activation level "H" level to make the column selection gate 114 conductive. Externally applied write data is applied to bit line pair BL, / BL of the selected column via data input / output line pair IO, / IO. Write data is applied as a potential difference between bit lines BL and / BL. In the capacitor of the selected memory cell MC,
An amount of charge corresponding to the potential of bit line BL or / BL is stored. Next, the word line WL falls to the “L” level of the non-selection level, the sense amplifier 115 is inactivated, the equalizer 116 is activated, and the bit line B
The potentials of L and / BL are equalized to bit line potential VBL, and preparation for the next writing operation is completed.

In the refresh operation, the equalizer 116 is inactivated, the word line WL designated by the refresh counter is raised to the selected level "H", the memory cell MC is activated, and the sense amplifier is activated. 115 is activated, and data is rewritten into memory cell MC. Thereafter, word line WL falls to "L" level, sense amplifier 115 is inactivated, and equalizer 116 is activated, and one word line WL is activated.
The refresh of the data of each memory cell MC corresponding to L ends. Refreshing of data is performed at a predetermined cycle.

Now, such an SDRAM is provided with a VPP generation circuit for boosting the power supply potential VCC to generate a boosted potential VPP. Boosted potential VPP is mainly applied to the gate of an N-channel MOS transistor included in memory cell MC to sufficiently reduce the conduction resistance of the N-channel MOS transistor and sufficiently charge the capacitor. Further, boosted potential VPP is applied to the gate of an N-channel MOS transistor included in equalizer 116 to sufficiently reduce the conduction resistance of the N-channel MOS transistor and to perform high-speed equalization of bit line pair BL, / BL. Used for etc.

FIG. 21 is a circuit block diagram showing a configuration of such a VPP generation circuit. In FIG. 21, the VPP generation circuit includes an active level detection circuit control logic 121, an active level detection circuit 122, a standby level detection circuit 123, and inverters 124a to 124a.
4d, charge pumps 125a to 125d, 126a to
126d, 128, oscillator 127 and pool capacity 13
0,131.

Active level detection circuit control logic 1
21 is a circuit for controlling the operation frequency of the active level detection circuit 122. The active level detection circuit control logic 121 includes bank activation signals RAS0 to RAS3
And the active level detection circuit activation signal φ121 is set to the “H” level of the activation level for a predetermined time in response to the rising edge of the signal. When bank activation signals RAS0-RAS3 are set to the "H" level of the activation level, four banks # 0- # 3 are activated, respectively.

Active level detection circuit 122 detects whether signal φ121 is activated during the activation level “H” level, and whether or not potential VPP at the node of boosted potential VPP has reached target potential VR. , The signal φ122 is set to “L” level, and if not, the signal φ122 is set to “H” level. The active level detection circuit 122 is a circuit having a high response speed but a large current consumption. For this reason, the operation frequency is controlled by the active level detection circuit control logic 121.

The standby level detection circuit 123 constantly detects whether or not the potential VPP at the node of the boosted potential VPP has reached the target potential VR, and if so, sets the signal φ123 to the “L” level, If not, the signal 123 is set to the “H” level. The standby level detection circuit 123 has a slow response speed but a small current consumption compared to the active level detection circuit 122.

Bank activation signals RAS0-RAS3 are
These are directly input to the charge pumps 125a to 125d, respectively, inverted by inverters 124a to 124d, and supplied to the charge pumps 126a to 126d. Charge pumps 125a to 125d are activated when output signal φ122 of active level detection circuit 122 is at the “H” level, and boosted potential V in response to rising edges of signals RAS0 to RAS3 at the “H” level.
A positive charge is applied to the node of PP. Charge pump 126
a to 126d are activated during the period when the output signal φ122 of the active level detection circuit 122 is at the “H” level, and respond to the falling edges of the signals RAS0 to RAS3 to the “L” level. Give a positive charge.

Oscillator 127 is activated while output signal φ 123 of standby level detecting circuit 123 is at “H” level, and supplies clock signal φ 127 of a predetermined frequency to charge pump 128. Charge pump 128 applies a positive charge to the node of boosted potential VPP in response to the rising edge of clock signal φ127. It should be noted that the boosted potential VP in the standby mode can be obtained only by the charge pump 128.
Even if P can be maintained at the target potential VR, the boosted potential VPP in the active state cannot be maintained at the target potential VR.

Pool capacitances 130 and 131 are connected between a line of power supply potential VCC and a line of ground potential GND, respectively, and a node of boosted potential VPP. The pool capacitors 130 and 131 are provided to prevent the potential of the node of the boosted potential VPP from suddenly changing.

Next, the operation of the VPP generation circuit will be described. During standby, the standby level detection circuit 123 detects whether the boosted potential VPP has reached the target potential VR. When boosted potential VPP is lower than target potential VR, oscillator 127 is activated to generate clock signal φ127, and charge pump 128
, A positive charge is supplied to the node of the boosted potential VPP. When boosted potential VPP is higher than target potential VR, oscillator 127 is inactivated, generation of clock signal φ127 is stopped, and supply of positive charges from charge pump 128 is stopped.

When active, signals RAS0-RAS3
Active level detection circuit 122 is activated for a predetermined time in response to one or three of the signals attaining an "H" level, and active level detection circuit 122
Thereby, it is detected whether or not the node of boosted potential VPP has reached target potential VR. When boosted potential VPP is lower than target potential VR, charge pumps 125a to 125a
25d, 126a-126d are made operable, and charge pumps 125a-125d, 125d are synchronized with rising and falling edges of signals RAS0-RAS3.
Positive charges are supplied from 126a to 126d to the node of the boosted potential VPP. When boosted potential VPP is higher than target potential VR, charge pumps 125a to 125d, 12
6a to 126d are disabled. Therefore,
In the standby mode and the active mode, the node of boosted potential VPP is maintained at target potential VR with low power consumption.

[0028]

However, the conventional VPP
The generator has the following problems. Now, SDR
Four banks of AM {one bank of 0 to 3}
0 is activated for a long time, and as shown in FIG. 22, the signal RAS0 of the bank activation signals RAS0-RAS3 is activated.
Only the “H” level is set to the “H” level for a long time.

When signal RAS0 rises to the "H" level (time t1), signal .phi.121 attains the "H" level of the activation level for a predetermined time, and active level detection circuit 122 is activated. At this time, boosted potential VPP has reached target potential VR, and signals φ122, φ123
Are both at the “L” level. Signal RAS
During the period when 0 is at the “H” level (time t1 to t3), the active level detection circuit 122 is not activated again.

The potential VPP at the node of the boosted potential VPP is
It is assumed that the voltage gradually decreases due to leakage due to some cause, and the boosted potential VPP becomes lower than the target potential VR at a certain time t2. At this time, the output signal φ123 of the standby level detection circuit 123 goes to “H” level to drive the charge pump 128, but the output signal φ122 of the active level detection circuit 122 remains at “L” level and remains unchanged. 125a-125d, 12
6a to 126d are fixed in an inoperative state.

At time t3, bank activation signal RAS
0 falls to the "L" level, bank # 0 shifts from the active state to the inactive state, so that boosted potential VP is applied.
P is used, and the potential VPP at the node of the boosted potential VPP drops sharply.

Conventionally, in order to suppress such a decrease in the boosted potential VPP, extremely large pool capacitances 130 and 131 are used.
Is provided, there is a problem that the layout area of the VPP generation circuit becomes large.

Therefore, a main object of the present invention is to provide a semiconductor device capable of generating a stable internal power supply potential and having a small layout area.

[0034]

The invention according to claim 1 is
A semiconductor device having an internal circuit having a standby state and an active state, wherein an internal power supply node for applying an internal power supply potential to the internal circuit, and whether a potential of the internal power supply node has reached a predetermined target potential And a first detection circuit for constantly detecting whether or not the internal circuit has been activated and setting the first control signal to an activation level when the internal circuit has not been reached, and activating the internal circuit for a predetermined time in response to activation of the internal circuit. A second detection circuit that detects whether or not the potential of the internal power supply node has reached a predetermined target potential, and if not, sets a second control signal to an activation level; A first charge pump that is activated when the first control signal is at the activation level and has a small charge supply capability to supply charges to the internal power supply node at a predetermined cycle; and a first and second control signal. And a control circuit for setting the third control signal to the activation level when at least one of them is at the activation level, and the internal circuit is activated when the third control signal is at the activation level. A second charge pump having a large charge supply capability for supplying charges to the internal power supply node in response to the state being set is provided.

According to a second aspect of the present invention, the control circuit according to the first aspect of the present invention includes a latch circuit for latching a level of a first control signal in response to the internal circuit being set to a standby state. The third control signal is set to the activation level when at least one of the first control signal and the second control signal latched by the circuit is set to the activation level.

According to the third aspect of the present invention, the second charge pump according to the first aspect of the present invention is configured such that when the third control signal is at an activation level and the internal circuit is in a standby state, A signal generation circuit for setting a signal to an activation level; and a capacitor having a predetermined capacitance value, the capacitor is charged in response to the pump signal being set to an inactivation level, and the pump signal is set to an activation level. And a charge / discharge circuit for discharging the charge of the capacitor to the internal power supply node in response to the operation. The control circuit sets the fourth control signal to the activation level in response to the first control signal being set to the activation level, and sets the fourth control signal to the fourth level in response to the pump signal being set to the inactivation level. A flip-flop for setting the control signal to an inactive level is included, and when at least one of the second and fourth control signals is set to the active level, the third control signal is set to the active level.

In the invention according to claim 4, claims 1 to 3
In the invention according to any one of the first to third aspects, the third control signal is activated when the activation level is at the activation level, and has a large charge supply capability for supplying charges to the internal power supply node in response to the activation of the internal circuit. Three charge pumps are further provided.

According to the fifth aspect of the present invention, the first to fourth aspects are described.
The internal circuit according to any one of the above aspects includes a memory array, and the semiconductor device is a semiconductor storage device.

[0039]

[First Embodiment] FIG. 1 is a circuit block diagram showing a configuration of a VPP generating circuit of an SDRAM according to a first embodiment of the present invention.

In FIG. 1, the VPP generation circuit includes an active level detection circuit control logic 1, an active level detection circuit 2, a standby level detection circuit 3, an active pump control circuit 4, inverters 5a to 5d, charge pumps 6a to 6d, 7a to 7d, 9; an oscillator 8;

Active level detection circuit control logic 1
Is a circuit for controlling the operation frequency of the active level detection circuit 2. That is, as shown in FIG. 2, the active level detection circuit control logic 1
2. It includes a delay circuit 13 and an AND gate 15, and the delay circuit 13 includes an odd number of stages of inverters 14 connected in series. The EX-OR gate 12 outputs the bank activation signal RAS
0 to RAS0, and the output signal φ12
3 and is input to one input node of the AND gate 15 and directly input to the other input node of the AND gate 15. Delay circuit 13 and AND gate 15
Constitutes a pulse generator. The output signal of AND gate 15 becomes active level detection circuit activation signal φ1.

When bank activation signals RAS0-RAS3 attain the activation level "H" as shown in FIG.
Four banks # 0- # 3 corresponding to bank activation signals RAS0-RAS3 are activated, respectively. EX-OR
Output signal .phi.12 of gate 12 attains "H" level when one or three of four bank activation signals RAS0-RAS3 attain an "H" level of the activation level, and in other cases. Becomes "L" level. The active level detection circuit activation signal φ1 is supplied to the EX-OR gate 1
In response to the rising edge of the second output signal φ12, the pulse signal goes to the “H” level for the delay time of the delay circuit 13.
Active level detection circuit activation signal φ1 is applied to active level detection circuit 2.

The active level detection circuit 2 outputs the signal φ1
Is activated during the period of “H” level, detects whether the node of boosted potential VPP is at target potential VR or not, and provides signal φ 2 of a level corresponding to the detection result to active pump control circuit 4. That is, as shown in FIG. 4, the active level detection circuit 2 includes P-channel MOS transistors 21 to 24 and N-channel MOS transistors 25 to 3
0, inverters 31 to 34 and a transfer gate 35.

MOS transistors 21, 22, 25, 2
6 is connected in series between the node of the boosted potential VPP and the line of the ground potential GND, and MOS transistors 23 and 2
7, 28 and MOS transistors 24, 29, 30 are connected in series between a line of power supply potential VCC and a line of ground potential GND, respectively. The gate of P-channel MOS transistor 21 is grounded, and the gates of P-channel MOS transistors 22 and 29 are each connected to a constant voltage VC.
1, VC2. P channel MOS transistor 2
Each of 1, 22, and 29 operates as a resistance element. N
The gates of channel MOS transistors 25 and 27 are both connected to the drain of N channel MOS transistor 25, and the gates of P channel MOS transistors 23 and 24 are both connected to the drain of P channel MOS transistor 24. N-channel MOS transistor 25,
27 and P-channel MOS transistors 23 and 24 each constitute a current mirror circuit. N-channel MO
The gates of the S transistors 26, 28, and 30 are connected to the signal φ1
Receive.

Inverter 31, transfer gate 3
5 and inverter 33 are connected to the drain (node N23) of P-channel MOS transistor 23 and output node N2.
Are connected in series. The signal φ1 is output from the inverter 32
P-channel MOS of transfer gate 35
The signal is input to the gate on the transistor side and is also input directly to the gate of the transfer gate 35 on the N-channel MOS transistor side. Inverter 34 is connected to inverter 33 in anti-parallel. Inverters 33 and 34
Constitute a latch circuit.

When signal .phi.1 attains the "H" level of the activation level, N-channel MOS transistors 26, 28, 30
In addition, the transfer gate 35 becomes conductive, and the active level detection circuit 2 is activated. A current having a value corresponding to the potential VPP at the node of the boosted potential VPP flows through the MOS transistors 21, 22, 25, and 26. MOS transistors 27 and 28 can flow a current having a value corresponding to the current flowing through MOS transistor 25. A constant current having a value corresponding to the constant voltage VC2 flows through the MOS transistors 23, 24, 29, and 30.

When boosted current VPP is higher than target potential VR, the current flowing through MOS transistor 23
The current becomes smaller than the current that can be passed by transistors 27 and 28, and node N27 attains "L" level, and signal φ2 attains "L" level as shown in FIG. Boosted potential VPP
Is lower than the target potential VR, the current flowing through the MOS transistor 23 becomes larger than the current that can flow through the MOS transistors 27 and 28, the node N23 goes high, and the signal φ2 goes high. . Signal φ1
Is at the inactive level of "L", N channel MOS transistors 26, 28, 30 and transfer gate 35 are rendered non-conductive, and active level detecting circuit 2 is inactivated. The signal φ2 is output from the inverter 3
It is latched by a latch circuit composed of 3, 34.

The active level detecting circuit 2 has good responsiveness but consumes a large amount of power. Therefore, the active level detecting circuit 2 consumes power only by activating the active level detecting circuit 2 when the signal .phi.1 attains the activation level "H". Power consumption is being reduced.

The standby level detection circuit 3 constantly monitors the potential VPP of the node of the boosted potential VPP, and supplies a signal φ3 having a level corresponding to the monitored result to the active pump control circuit 4 and the oscillator 8. That is, as shown in FIG. 6, the standby level detection circuit 3
Transistors 41 to 43, N-channel MOS transistors 44 and 45, and inverters 46 and 47 are included. MO
S transistors 41, 42, and 44 are connected in series between a node of boosted potential VPP and a line of ground potential GND,
MOS transistors 43 and 45 are connected in series between the line of power supply potential VCC and the line of ground potential GND.

The gate of P channel MOS transistor 41 is grounded, and P channel MOS transistors 42 and 4
Gates 3 receive constant voltages VC3 and VC4, respectively.
Each of P channel MOS transistors 41 to 43 operates as a resistance element. The gates of N-channel MOS transistors 44 and 45 are both connected to the drain of N-channel MOS transistor 44. N-channel MOS transistors 44 and 45 form a current mirror circuit. Inverters 46 and 47 include a drain (node M43) of P-channel MOS transistor 43 and an output node N
3 is connected in series. The signal appearing at output node N3 becomes standby level detection signal φ3.

A current having a value corresponding to the potential VPP at the node of the boosted potential VPP flows through the MOS transistors 41, 42, and 44. N channel MOS transistor 45
A current having a value corresponding to the current flowing through N-channel MOS transistor 44 can flow. A constant current having a value corresponding to constant voltage VC4 flows through P channel MOS transistor 43.
When boosted potential VPP is higher than target potential VR, the current flowing through P-channel MOS transistor 43 is smaller than the current that can be passed by N-channel MOS transistor 45, and node N43 attains "L" level, as shown in FIG. Thus, signal φ3 attains the “L” level. Boosted potential VP
When P is lower than target potential VR, P-channel MOS
The current flowing through transistor 43 becomes larger than the current that can be passed by N-channel MOS transistor 45, so that node N43 attains "H" level and signal φ3 attains "H" level.

Active pump control circuit 4 includes an OR gate 47, as shown in FIG. The OR gate 47
An active level detection signal φ2 generated by the active level detection circuit 2 and a standby level detection signal φ3 generated by the standby level detection circuit 3 are received, and an output signal φ4 thereof is supplied to the charge pumps 6a to 6d and 7a to 7d. .

The bank activation signals RAS0-RAS3 are
The signals are directly input to the charge pumps 6a to 6d, respectively, and input to the charge pumps 7a to 7d via the inverters 5a to 5d. Charge pumps 6a to 6d
Are provided corresponding to the four banks # 0 to # 3, respectively, become operable when signal φ4 is at "H" level, and boosted potential VPP in response to activation of the corresponding bank. Supply positive charge to the node. Charge pump 7
a to 7d are provided corresponding to the four banks # 0 to # 3, respectively, become operable when signal φ4 is at the "H" level, and in response to the corresponding bank being inactivated. A positive charge is supplied to the node of the boosted potential VPP.

Charge pump 6a includes an AND gate 51, a capacitor 52 and N-channel MOS transistors 53 and 54, as shown in FIG. AND gate 51 receives signals RAS0, φ4. Capacitor 52
Is connected between the output node of AND gate 51 and node N53. N channel MOS transistor 53
Is diode-connected between the line of the power supply potential VCC and the node N53. N channel MOS transistor 54
Is diode-connected between the node N53 and the node of the boosted potential VPP.

Charge pump 6a is activated while active pump control signal φ4 is at "H" level. While signal RAS0 is at the “L” level (ground potential GND), output signal φP of AND gate 51 is at the “L” level, and current flows from power supply potential VCC line to node N53 via N-channel MOS transistor 53. Inflow,
When the capacitor 52 is connected to VCC-Vthn (Vthn
Is the threshold voltage of the N-channel MOS transistor). When signal RAS0 is raised to the "H" level (power supply potential VCC), node N53 is set at 2VC
C-Vthn, and N-channel MO
A positive charge is supplied to the node of the boosted potential VPP via the S transistor 54. Therefore, whenever signal RAS0 rises from "L" level to "H" level while signal φ4 is at "H" level, a positive charge is supplied to the node of boosted potential VPP, and the potential of the node of boosted potential VPP rises. I do. Other charge pumps 6b-6d, 7a-7d
Has the same configuration as the charge pump 6a.

However, since the charge pumps 7a to 7d receive the inverted signals of the bank activation signals RAS0 to RAS3, the charge pumps 7a to 7d respectively output the signals RAS0 to RAS while the signal φ4 is at the “H” level.
Each time S3 falls from "H" level to "L" level, a positive charge is supplied to the node of boosted potential VPP.

The oscillator 8 has a NAN as shown in FIG.
Even-numbered inverter 56 connected in series with D gate 55
And Standby level detection signal φ3 generated by standby level detection circuit 3 is input to one input node of NAND gate 55. An output signal of the NAND gate 55 is supplied to the NAND gate 55 through an even-numbered inverter 56.
5 is input to the other input node. The output signal of the final-stage inverter 56 becomes the output signal φ8 of the oscillator 8. When standby level detection signal φ3 attains the “H” level of the activation level, NAND gate 55 operates as an inverter with respect to signal φ8, and NAND gate 55 and even-numbered stage inverter 56 constitute a ring oscillator. This ring oscillator generates a clock signal φ8 of a predetermined frequency. Clock signal φ8 is input to charge pump 9.

Charge pump 9 includes an inverter 61, a capacitor 62 and N-channel MOS transistors 63 and 64, as shown in FIG. Clock signal φ
8 is input to one electrode of a capacitor 62 via an inverter 61. N channel MOS transistor 63
Is diode-connected between the power supply potential VCC line and the other electrode of the capacitor 62 (node N63). N
Channel MOS transistor 64 is diode-connected between node N63 and a node of boosted potential VPP.

While clock signal φ8 is at “H” level, the output node of inverter 61 is at “L” level, and current flows from power supply potential VCC line to node N63 via N-channel MOS transistor 63. Capacitor 62 is charged to VCC-Vthn. When clock signal φ8 falls to "L" level, node N63
Becomes 2VCC-Vthn, and a current flows from the node N63 to the node of the boosted potential VPP via the N-channel MOS transistor 64. Therefore, the clock signal φ
Each time 8 falls from "H" level to "L" level, a positive charge is supplied to the node of boosted potential VPP.

The charge pump 9 is for maintaining the potential of the node of the boosted potential VPP in the standby state, and has a small charge supply capability. Therefore, the charge pump 9 reduces the boosted potential VPP in the active period to the target potential. Cannot be maintained at VR.

The pool capacitors 10 and 11 are connected between the power supply potential VCC line and the ground potential GND line and the boosted potential VPP node, respectively. Pool capacity 1
0 and 11 are provided to prevent a sudden change in the potential of the node of the boosted potential VPP.

Next, the operation of the VPP generation circuit shown in FIGS. 1 to 11 will be described. Bank activation signal RAS0
When one or three of the signals RAS3 to RAS3 attain the activation level "H" level, the output signal .phi.1 of the active level detection circuit control logic 1 attains the activation level "H" level for a predetermined time, and The level detection circuit 2 is activated. The active level detection circuit 2 detects whether or not the boosted potential VPP has reached the target potential VR. If the boosted potential VPP has not reached the target potential VR, the signal φ2 goes to the activation level “H” level . The standby level detection circuit 3 detects whether or not the potential of the node of the boosted potential VPP has reached the target potential VR. If the boosted potential VPP has not reached the target potential VR, the signal φ3 changes to the activation level. "H" level. The logical sum signal φ4 of the signals φ2 and φ3 is supplied from the active pump control circuit 4 to the charge pumps 6a to 6a.
d, 7a to 7d.

When signals RAS0 to RAS3 are raised to the "H" level of the activation level while signal φ4 is at the "H" level of the activation level, charge pumps 6a to 6d are activated and charge pump 6a, respectively. ~ 6d
, A positive charge is supplied to the node of the boosted potential VPP. When signals RAS0-RAS3 fall to an inactive level of "L" level while signal φ4 is at an active level of "H" level, charge pumps 7a-7d respectively
Is activated, and positive charges are supplied from charge pumps 7a to 7d to the node of boosted potential VPP.

When signal .phi.3 attains the "H" level of the activation level, oscillator 8 is activated, clock signal .phi.8 is input from oscillator 8 to charge pump 9, and charge pump 9 supplies the boosted potential VPP to the node of boosted potential VPP. A positive charge is provided. Thus, the potential of the node of boosted potential VPP increases.

On the other hand, when boosted potential VPP has reached target potential VR, both signals φ2 to φ4 attain “L” level and charge pumps 6a to 6d, 7a to 7d, 9
Are deactivated, and the charge pumps 6a to 6d and 7a to 7
The supply of charges from d and 9 to the node of the boosted potential VPP is stopped. Therefore, boosted potential VPP is equal to target potential VR.
Is maintained.

Next, a case where only one bank # 0 is activated for a long time will be described. In this case, as shown in FIG. 12, the signal RA among the signals RAS0-RAS3 is output.
Only S0 is set to the "H" level for a long time. Signal RAS0
Rises to the "H" level (time t1), signal .phi.1 attains the "H" level of the activation level for a predetermined time, and active level detection circuit 2 is activated. At this time, it is assumed that boosted potential VPP has reached target potential VR, and signals φ2 and φ4 have become “L” level. Signal R
While AS0 is at the “H” level (time t1 to t3), the active level detection circuit 2 is not activated again.

The potential VPP at the node of the boosted potential VPP is
It is assumed that the voltage gradually decreases due to leakage due to some cause, and the boosted potential VPP becomes lower than the target potential VR at a certain time t2. At this time, the output signal φ3 of the standby level detection circuit 3 goes high and the signal φ4 goes high. When signal φ4 attains an “H” level, charge pumps 6a to 6d and 7a to 7d enter an operable state.

When signal RAS0 falls to the inactive level of "L" at time t3, positive charges are supplied from charge pumps 7a to 7d to the node of boosted potential VPP, and the node of boosted potential VPP is boosted. You. Therefore, since the potential of the node of boosted potential VPP does not decrease at time t3, pool capacitances 10 and 11 can be small, and the layout area of the VPP generation circuit can be small.

Although this embodiment has been described with reference to the case where the SDRAM has four banks, the number of banks is four.
Needless to say, the number is not limited to one.

[Second Embodiment] FIG. 13 is a circuit block diagram showing a configuration of a VPP generation circuit of an SDRAM according to a second embodiment of the present invention, which is compared with FIG.

Referring to FIG. 13, the difference between this VPP generation circuit and the VPP generation circuit of FIG. 1 is that active pump control circuit 4 includes active pump control circuits 70a-70.
d, 71a to 71d. Active pump control circuits 70a to 70d control charge pumps 6a to 6d according to signals RAS0 to RAS3 and signals φ2 and φ3, respectively. The active pump control circuits 71a to 71d include inverters 5a to 5d, respectively.
The charge pumps 7a to 7d are controlled according to the output signals / RAS0 to / RAS3 and the signals φ2 and φ3. Output signals of the active pump control circuits 70a to 70d and 71a to 71d are input to charge pumps 6a to 6d and 7a to 7d instead of the signal φ4, respectively.

The active pump control circuit 71a has the configuration shown in FIG.
4, an OR gate 72, a transfer gate 73, and inverters 74 to 77 are included. Signal φ2
Is input to one input node of the OR gate 72. Signal φ3 is input to the other input node of OR gate 72 via transfer gate 73 and inverters 75 and 77. The output signal / RAS0 of the inverter 5a is
N of the transfer gate 73 via the inverter 74
The signal is input to the gate on the channel MOS transistor side, and the P-channel MOS
It is directly input to the gate on the transistor side. Inverter 76 is connected to inverter 75 in anti-parallel. As shown in FIG. 15, output signal φ72 of OR gate 72 is applied to charge pump 7a instead of signal φ4.

When signal / RAS0 is at the "L" level of the activation level, transfer gate 73 is turned on, and signal φ3 is applied to transfer gate 73 and inverter 7
5, 77 are input to the other input node of the OR gate 72. When signal / RAS0 rises to "H" level at a certain time t3, transfer gate 73 is rendered non-conductive, and the level of signal φ3 is latched by a latch circuit including inverters 75-77. Therefore, FIG.
At time t3, the signal RAS0 falls to the "L" level, the boosted potential VPP becomes higher than the target potential VR, and even when the signal .phi.3 goes to the "L" level, the signal .phi.72 remains at the "H" level. It does not change. Therefore, the positive charge charged in the capacitor 52 of the charge pump 7a can be sufficiently supplied to the node of the boosted potential VPP, and the use efficiency of the charge pump 7a increases.

More specifically, in FIG. 15, while signal φ72 is at the “H” level, signal / RAS0 attains the “L” level (time t2 to t3), and capacitor 52 becomes VC.
It is assumed that C-Vthn is charged. A certain time t
3 when signal / RAS0 attains "H" level.
3 becomes 2VCC-Vthn, and the boosted potential VPP from the node N53 via the N-channel MOS transistor 54
A positive charge flows through the node. If signal φ72 attains the “L” level while positive charges are flowing from node N53 to the node of boosted potential VPP, the positive charges charged in capacitor 52 do not sufficiently flow out, and the use efficiency of charge pump 7a is reduced. Gets worse. However, in the second embodiment, since signal φ72 is held at the “H” level, the positive charges charged in capacitor 52 can be sufficiently discharged, and the use efficiency of charge pump 7a can be increased. Other active pump control circuits 71b to 71d, 7
0a and 70d are the same as the active pump control circuit 71a.

[Third Embodiment] FIG. 17 is a circuit block diagram showing a configuration of a VPP generation circuit of an SDRAM according to a third embodiment of the present invention, which is compared with FIG. Referring to FIG. 17, this VPP generation circuit is connected to VPP of FIG.
The difference from the PP generation circuit is that the active pump control circuit 4 has the active pump control circuits 80a to 80d and 81a.
-81d. The active pump control circuits 80a to 80d and 81a to 81d respectively generate pump signals φ of the charge pumps 6a to 6d to 7a to 7d.
Charge pumps 6a-6a in accordance with P and signals φ2, φ3
d, 7a to 7d are controlled. Output signals of the active pump control circuits 80a to 80d and 81a to 81d are charge pumps 6a to 6d and 7a instead of the signal φ4, respectively.
To 7d.

The active pump control circuit 81a is configured as shown in FIG.
As shown in FIG. 8, the NAND gate 8 includes an OR gate 82, an inverter 83, and NAND gates 84 and 85.
Reference numerals 4 and 85 constitute a flip-flop 86. Signal φ2
Is input to one input node of the OR gate 82. The signal φ3 is supplied to the flip-flop 8 via the inverter 83.
6 is input to the set terminal 86a. Charge pump 7
The pump signal φP of “a” is input to the reset terminal 86 b of the flip-flop 86. Output signal φ86 of flip-flop 86 is input to the other input node of OR gate 82. The output signal φ82 of the OR gate 72 is the signal φ
4 is input to the charge pump 7a.

Now, it is assumed that signals φ2 and φ3 are at “L” level and “H” level, respectively. At this time, since the output signal φ86 of the flip-flop 86 is at the “H” level, the signal φ82 is at the “H” level, and the charge pump 7a is in an operable state. At a certain time t3 (see FIG. 16), signal / RAS0 attains “H” level, and pump signal φP of charge pump 7a attains “H” level, and positive charge flows from charge pump 7a to the node of boosted potential VPP. Charge pump 7a
Becomes high when the pump signal φP of FIG.
The output signal of AND gate 85 attains "L" level. Positive charge flows from the charge pump 7a to the node of the boosted potential VPP, the boosted potential VPP reaches the target potential VR, and the period during which the pump signal φP is at the “H” level even when the signal φ3 is at the “L” level The output signal φ86 of the flip-flop 86 remains at “H” level and does not change.

Therefore, as in the second embodiment, the positive charge charged in capacitor 52 of charge pump 7a can be sufficiently supplied to the node of boosted potential VPP.
The use efficiency of the charge pump 7a increases. The other active pump control circuits 81b to 81d and 80a to 80d are the same as the active pump control circuit 81a.

It should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0080]

As described above, according to the first aspect of the present invention, it is always detected whether or not the potential of the internal power supply node has reached the target potential. If not, the first control signal is output. A first detection circuit for setting an activation level, and activation for a predetermined time in response to the internal circuit being activated, for detecting whether or not the potential of the internal power supply node has reached a target potential; A second detection circuit that sets the second control signal to the activation level when the signal has not reached the first detection signal; and a second detection circuit that is activated when the first control signal is at the activation level and supplies a charge to the internal power supply node at a predetermined cycle. A first charge pump having a small charge supply capability, and a control circuit for setting a third control signal to an activation level when at least one of the first and second control signals is at an activation level. , Third
Is activated when the control signal is at the activation level, and a second charge pump having a large charge supply capability for supplying charges to the internal power supply node in response to the internal circuit being set to the standby state is provided. Therefore, the first and second
When at least one of the control signals is activated, the second charge pump is activated, so that the internal circuit is activated for a long time and the internal power supply node reaches the target potential. Even when there is no internal power supply, the charge is supplied from the second charge pump to the internal power supply node when the internal circuit is set to the standby state, and the change in potential of the internal power supply node is suppressed. Therefore, the pool capacity for suppressing the potential change of the internal power supply node can be small,
The layout area is small.

According to a second aspect of the present invention, the control circuit according to the first aspect of the present invention includes a latch circuit for latching a level of a first control signal in response to an internal circuit being in a standby state, The third control signal is set to the activation level when at least one of the first control signal and the second control signal latched by the circuit is set to the activation level. In this case, it is possible to prevent the third control signal from going into the inactivation level when the charge charged in the second charge pump is not sufficiently supplied to the internal power supply node. Efficiency can be increased.

According to the third aspect of the present invention, the second charge pump according to the first aspect of the present invention provides a pump wherein the third control signal is at an activation level and the internal circuit is in a standby state. A signal generation circuit for setting a signal to an activation level; and a capacitor having a predetermined capacitance value, wherein the capacitor is charged in response to the pump signal being set to the inactivation level, and the pump signal is set to the inactivation level. And a charge / discharge circuit for discharging the charge of the capacitor to the internal power supply node. The control circuit sets the fourth control signal to the active level in response to the first control signal being set to the active level, and sets the fourth control signal in response to the pump signal to be set to the inactive level. And a flip-flop for setting the third control signal to the activation level when at least one of the second and fourth control signals is set to the activation level. Also in this case, it is possible to prevent the third control signal from going into the inactivation level when the charge charged in the second charge pump is not sufficiently supplied to the internal power supply node. Usage efficiency can be improved.

In the invention according to claim 4, claims 1 to 3
In the invention according to any one of the first to third aspects, the third control signal is activated when the activation level is at the activation level, and has a large charge supply capability for supplying charges to the internal power supply node in response to the activation of the internal circuit. Three charge pumps are further provided. In this case, the change in potential of the internal power supply node can be further suppressed.

According to the fifth aspect of the present invention, the first to fourth aspects are described.
The internal circuit according to any one of the above aspects includes a memory array, and the semiconductor device is a semiconductor storage device. The present invention
This is particularly effective in this case.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a VPP generation circuit of an SDRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an active level detection circuit control logic shown in FIG.

FIG. 3 is a time chart showing an operation of an active level detection circuit control logic shown in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of an active level detection circuit shown in FIG.

FIG. 5 is a time chart showing an operation of the active level detection circuit shown in FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of a standby level detection circuit shown in FIG. 1;

FIG. 7 is a time chart illustrating an operation of the standby level detection circuit illustrated in FIG. 6;

FIG. 8 is a circuit diagram showing a configuration of an active pump control circuit shown in FIG.

FIG. 9 is a circuit diagram showing a configuration of a charge pump 6a shown in FIG.

FIG. 10 is a circuit diagram showing a configuration of the oscillator shown in FIG.

FIG. 11 is a circuit diagram showing a configuration of a charge pump 9 shown in FIG.

FIG. 12 is a time chart for explaining effects of the VPP generation circuit shown in FIGS. 1 to 11;

FIG. 13 is an SDRAM according to a second embodiment of the present invention;
FIG. 3 is a circuit block diagram showing a configuration of a VPP generation circuit of FIG.

FIG. 14 is a circuit diagram showing a configuration of an active pump control circuit 71a shown in FIG.

FIG. 15 is a circuit diagram showing a configuration of a charge pump 7a shown in FIG.

FIG. 16 is a time chart for explaining effects of the VPP generation circuit shown in FIGS. 13 to 15;

FIG. 17 is an SDRAM according to a third embodiment of the present invention;
FIG. 3 is a circuit block diagram showing a configuration of a VPP generation circuit of FIG.

18 is a circuit diagram showing a configuration of an active pump control circuit 81a shown in FIG.

FIG. 19 is a block diagram showing an entire configuration of a conventional SDRAM.

20 is a circuit block diagram showing a configuration of a part of the memory array shown in FIG. 19 and a part related thereto.

FIG. 21 shows a VP included in the SDRAM shown in FIG. 19;
FIG. 3 is a circuit block diagram illustrating a configuration of a P generation circuit.

FIG. 22 is a time chart for explaining a problem of the VPP generation circuit shown in FIG. 21;

[Explanation of symbols]

1,121 active level detection circuit control logic,
2,122 Active level detection circuit, 3,123
Standby level detection circuit, 4, 70a to 70d, 71
a-71d, 80a-80d, 81a-81d Active pump control circuit, 5a-5d, 14, 31-34,
46, 47, 56, 61, 74 to 77, 83, 124a
~ 124d inverter, 6a ~ 6d, 7a ~ 7d,
9, 125a to 125d, 126a to 126d, 128
Charge pump, 8,127 oscillator, 10,11,
130, 131 pool capacity, 12 EX-OR gate, 13 delay circuit, 15, 51 AND gate, 21
~ 24,41-43 P-channel MOS transistors,
25 to 30, 44, 45, 53, 54, 63, 64 N
Channel MOS transistor, 35, 73 transfer gate, 47, 72, 82 OR gate, 52, 6
2 capacitors, 55, 84, 85 NAND gates,
86 flip-flops, 101 clock buffers,
102 control signal buffer, 103 address buffer, 104 mode register, 105 control circuit, 10
6 to 109 memory array, $ 0 to $ 3 banks, 11
0 I / O buffer, 111 row decoder, 112 column decoder, 113 sense amplifier + input / output control circuit, 1
14 column select gate, 115 sense amplifier, 116
Equalizer, MC memory cell, WL word line, B
L, / BL bit line pair, CSL column select line, IO, / I
O Data input / output line pair.

Claims (5)

[Claims] 1. A semiconductor device having an internal circuit having a standby state and an active state, comprising: an internal power supply node for applying an internal power supply potential to the internal circuit; and a potential of the internal power supply node being a predetermined target. A first detection circuit that constantly detects whether or not the potential has been reached, and sets a first control signal to an activation level if the potential has not been reached; Activated for a predetermined time, detects whether the potential of the internal power supply node has reached a predetermined target potential, and if not, sets the second control signal to an activation level A second detection circuit which is activated when the first control signal is at an activation level and has a small charge supply capability for supplying charges to the internal power supply node at a predetermined cycle; A pump, a control circuit for setting a third control signal to an activation level when at least one of the first and second control signals is at an activation level, and an activation of the third control signal A semiconductor device comprising: a second charge pump that is activated when the level is at a level and has a large charge supply capability to supply charges to the internal power supply node in response to the internal circuit being in a standby state. 2. The control circuit includes: a latch circuit that latches a level of the first control signal in response to the internal circuit being set to a standby state; and the first circuit latched by the latch circuit. The semiconductor device according to claim 1, wherein the third control signal is set to an activation level when at least one of a control signal and the second control signal is set to an activation level. 3. A signal generating circuit for setting a pump signal to an active level when the third control signal is at an active level and the internal circuit is in a standby state. And a capacitor having a predetermined capacitance value, and charges the capacitor in response to the pump signal being set to the inactive level, and sets the capacitor in response to the pump signal being set to the active level. A charge / discharge circuit for discharging a charge of a capacitor to the internal power supply node; wherein the control circuit sets a fourth control signal to an activation level in response to the first control signal being set to an activation level; A flip-flop for setting the fourth control signal to an inactive level in response to the pump signal being set to an inactive level; At least one of to the active level the third control signal if it is in active level, the semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein said third control signal is activated when said third control signal is at an activation level, and said charge supply capability for supplying charges to said internal power supply node in response to said internal circuit being activated. 4. The semiconductor device according to claim 1, further comprising a large third charge pump. 5. The semiconductor device according to claim 1, wherein said internal circuit includes a memory array, and said semiconductor device is a semiconductor memory device.