JP2001135037A - Data transfer method and data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer data in a bit unit convenient for demodulating the channel bit of an address or the channel bit of data from a decoding part in a demodulation part when transferring data by a common data bus. SOLUTION: In the transfer of data from a reading channel processor 13 to a demodulation part 14, decoding data is set to be a six channel parallel being the lowest common multiple of both data and an address and a clock whose frequency is divided into six is used so that a bit unit convenient for the address as well as is obtained in the demodulation part 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, RLL (Ru
n Length Limited) and relates to a data transfer method for transferring channel bit data obtained by decoding a reproduction RF signal read from a recording medium on which information is recorded using at least one comparator level to a demodulation unit. . Further, the present invention relates to a data reproducing device for transferring channel bit data to a demodulation unit by the data transfer method and demodulating the data in the demodulation unit.

[0002]

2. Description of the Related Art In order to enable high-density recording, address data is preformatted using a pit string, and an address information area in which the address data is recorded and a user in which the data is recorded or recorded. There is a large-capacity optical disk in which areas are alternately arranged, and grooves are formed in a meandering manner in the user area.

[0003] Even in this large-capacity optical disk, data is modulated so as to be suitable for recording like a general optical disk or a magneto-optical disk. A block code is known as one of such modulations. In this block code, a data sequence is divided into units of m × i bits (hereinafter referred to as data words), and the data words are converted into code words of n × i bits according to an appropriate coding rule. When i = 1, the code becomes a fixed length code.
Can be selected, that is, when i is equal to or greater than 2 and the conversion is performed with imax = r, which is the maximum i, a variable length code is obtained. This block-coded code is a variable-length code (d,
k; m, n; r). Here, i is called a constraint length. r
Is the maximum constraint length. Also, d and k are the minimum number of consecutive “0” s between consecutive “1s” in the code sequence and “k”.
This is the maximum number of consecutive 0s.

In the above-mentioned large-capacity optical disk, the data word of the address is represented by the R (2,7; 1,2; 4) parameter.
The data word is recorded as a code word (channel bit) by LL (2, 7) modulation, and the data word recorded in the user area is a channel bit by 1, 7 PP modulation of the parameters (1, 7, 2, 3, 2). Therefore, in the data decoding unit of the device for reproducing data from the large-capacity optical disk,
A channel bit of an address subjected to RLL (2, 7) modulation and a channel bit of data subjected to 1,7PP modulation are generated, and transferred to a demodulation unit to demodulate a data word.

In an apparatus for reproducing data from a large-capacity optical disk, a high-speed channel clock is assumed. Therefore, data transfer from a read channel processor that generates address / data channel bits to a demodulation unit is performed. Needs to be parallel data of a plurality of channels.

[0006]

The demodulation section employs a method (for (2,7) modulation) in which an address channel bit and three channel bits are two data bits, and a data channel bit and a two channel bit are used. 1
Since the data bit method (for (1,7PP) modulation) is employed, when the data bus is shared, it is not preferable for the demodulation unit to use either three-channel parallel or two-channel parallel.

In addition, the data bus is made three-channel parallel, and the channel bits to be transferred between the address part and the data part are switched between three-channel parallel and two-channel parallel, and the respective synchronous clocks (divided-by-3 clock and divided-by-2 clock) are also switched. However, since the divided clock is generated based on the divided-by-2 clock, the divided-by-3 clock becomes off-duty.
When the frequency is 0 MHz, the pulse width of the divided-by-3 clock is as short as 7.7 ns, similar to that of the divided-by-2 clock.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is convenient to demodulate either of the channel bits of an address and the channel bits of data in a demodulation unit when transferring the data through a shared data bus. It is an object of the present invention to provide a data transfer method that enables data transfer in bit units.

Another object of the present invention is to provide a data reproducing apparatus for reproducing data from a large-capacity optical disk by applying the above data transfer method.

[0010]

In order to solve the above-mentioned problems, a data transfer method according to the present invention uses address information having different modulation schemes and decoded data of recorded data obtained from a read signal of a disk-shaped recording medium. In a data transfer method for transferring data to a demodulation unit, the address information and the decoded data of the recording data are transferred by a least common multiple clock and a least common multiple parallel transfer.

According to another aspect of the present invention, there is provided a data reproducing apparatus comprising: a head for reading a signal from a disk-shaped recording medium; and a reproducing processor for performing a reproducing process on the signal from the head. Decoding processing means for decoding address information and recording data having different modulation schemes from an output of the reproduction processing means, and transferring the decoded data with a least common multiple clock and a least common multiple parallel transfer; Demodulation means for demodulating the recording data from the decoded data transferred from the processing means.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. This embodiment has an address information area formed by embossed pits,
An optical disk recording / reproducing apparatus for recording / reproducing data on / from an optical disk having a recording / reproducing area in which a wobbled groove is formed in a spiral shape. In this optical disc, the data word of the address is recorded as a code word (channel bit) by RLL (2, 7) modulation of the parameter (2, 7; 1, 2; 4), and the data word recorded in the user area is a parameter word. (1,7; 2
3; 2) Channel bits based on 1,7PP modulation. Therefore, the apparatus for reproducing data from the optical disk decodes the channel bits of the RLL (2,7) modulated address and the channel bits of the 1,7PP modulated data, and transfers these to the demodulation unit. Demodulate data words.

FIG. 1 shows the configuration of an optical disk recording / reproducing apparatus. An optical head (OP head) 11 for appropriately irradiating a laser beam for reading and writing a signal on a signal recording surface on the optical disk 10; a reproduction signal from the OP head 11; A read processor 12 that performs processing and servo detection processing; a read channel processor 13 that extracts address data and channel bit data of recording data from an output of the read processor 12;
A demodulation unit for demodulating address data and recording data by performing demodulation processing on channel bits transferred based on the data transfer method of the present invention, or a modulation unit for recording, and a digital signal including a servo processing unit A signal processing unit (DSP) 14 and a data manager unit 15 that performs predetermined data processing on demodulated data or recording data from the DSP 14 or decodes the address data.

The optical disk recording / reproducing apparatus includes a write processor 16 for performing processing for writing data for recording in accordance with a user's instruction, and an OP head 11 in response to a laser drive pulse from the write processor 16.
An LD driver 17 for driving a laser diode therein by, for example, automatic power control (APC) and a spindle circuit 18 for controlling a spindle motor 19 for rotating the optical disc 10 are provided.

This optical disk recording / reproducing apparatus has an R
Also provided is a CPU 20 for controlling the above-described units while developing a predetermined application program stored in the OM 22 or an application downloaded from the host computer via the I / F 23 in the RAM 21. The I / F 23 also functions as an interface for causing the optical disk recording / reproducing apparatus to process a recording / reproducing command from, for example, an AV system (not shown) or an image recording bitstream for recording.

The OP head 11 comprises an optical system including a laser diode LD, a reproduction IV amplifier, a two-axis actuator, and the like.

The read processor 12 includes an RF processing unit 12a and a wobble processing unit 12 which will be described in detail later.
b and servo signal detection 12c.

Next, the basic operation of the optical disk recording / reproducing apparatus during recording and reproduction will be described. First, at the time of recording, a recording command and an MPEG2 image recording stream are sent from an AV system (not shown) to the optical disk recording / reproducing apparatus via the I / F 23, for example. The command is received by the CPU 20. The CPU 20 obtains the address information from the data manager unit 15, makes the servo unit of the DSP 14 seek the OP head 11, and moves the OP head 11 to a desired address position. The recording stream is error-correction encoded by the ECC unit of the data manager unit 15. The error-corrected encoded bit stream is
The data is modulated by the modulation section of the DSP 14 into recording data. The write processor 16 performs recording compensation on the recording data, and drives the LD of the OP head 11 by the LD driver 17 at the timing from the address DECTG of the data manager unit 15 to record channel bits on the optical disc 10.

Next, at the time of reproduction, a reproduction command is sent to the CPU 20 from the AV system. The CPU 20 obtains address information from the address DEC section of the data manager section 15, makes the servo section seek the OP head 11, and moves the OP head 11 to a desired address position. A reproduction signal is obtained from the OP head 11 and the RF
Reproduction data is obtained by a PLL or the like in the processing unit 12a. The reproduction data is decoded into channel bits by the read channel processor 13 and then demodulated by a demodulation circuit inside the DSP 14. The demodulated bit stream is subjected to error correction decoding by an ECC unit in the data manager unit 15 and then converted to an I / F 23 as an image reproduction bit stream.
To the AV system via

At the time of recording and reproduction, the wobble processing unit 12b inside the read processor 12 detects a wobble signal from a read signal from the OP head 11,
A synchronizing signal is generated from the wobble signal, and the synchronizing signal is sent to the address DEC unit in the data manager unit 15.

At the time of recording and reproduction, the RF processing unit 12a in the read processor 12 performs waveform equalization processing, PLL (phase lock loop) processing, AGC processing on the reproduction signal from the OP head 11. (Auto gain control) processing and ADC (analog-digital conversion) processing are performed.

The digital output from the RF processor 12a is sent to the read channel processor 13 as RF-A / D data. The read processor 12 detects address data following the sector mark SM recorded in the address information area of the optical disc 10 and supplies the address data to the read channel processor 13. The clock wck for the address data is also supplied to the read channel processor 13. Also, the wobble processing unit 12b
A wobble signal is obtained from a reproduction signal (here, a push-pull PP signal) from the OP head 11 to generate a synchronization signal,
It is supplied to the read channel processor 2 as a reference clock. The servo signal detector 12c detects a servo of the two-axis actuator in the OP head 11 and a servo signal for performing a seek of the OP head 11, and sends the servo signal to a servo processor in the DSP 14.

The read channel processor 13 performs a bit detection process and a data correction process, and detects a channel bit of recording data and a channel bit of address data. The bit detection process performed here is a process performed by the temporary detector for internal calculation. A Viterbi detection process is performed as a main bit detection method separately from the bit detection process for the internal calculation, but the description is omitted here.

The bit detection processing for the internal operation is as follows. First, level comparison processing is performed on the digital data that has been A / D-converted by the RF processing unit 12a of the read processor 12 with the center level as a comparator level, and a determination of “1” or “0” is made at the center level. Do. Thus, when the level (amplitude value) of the digital data is equal to or higher than the compare level, the channel bit data of the logical level “1” is output. When the level of the digital data is lower than the compare level (amplitude value), It outputs channel bit data of logic level "0". When the level (amplitude value) of the digital data is equal to the comparator level, the bit detection processing is performed based on the sum of the amplitude values before and after the digital data and the comparator level, and the logic level “0” channel bit data or You may make it output the channel bit data of the logic level "1". The data correction process performs a correction process on the channel bit data obtained by the bit detection process based on a correction bit position designation signal designating the correction bit position detection. For example, (1,
7) In the modulation processing, the same sign and the middle sample level are thrs ± α for three consecutive bits from the bit detection result.
If it is within, the sign of the middle bit is inverted and corrected to 1T. 1T is detected from the bit string after the 1T correction, and the sample level before and after is detected and corrected to 2T. When the sample levels are the same, the same edge as the edge just corrected is corrected. Then, the channel bit data after the correction processing is output by the data correction processing. Here, the read channel processor 13 outputs three channel bit data of the address part and two channel bit data of the data part.

The DSP 14 is provided with a demodulation unit for performing demodulation processing as described above. Hereinafter, the code of the demodulation unit is set to 1
2, the connection relationship between the read processor 12 and the read channel processor 13 is shown in FIG. By the way, in a device for reproducing data from a large-capacity optical disk,
Since the channel clock is assumed to be fast,
The data transfer from the read channel processor 13 for generating the address / data channel bits to the demodulation unit 14 needs to be parallel data of a plurality of channels.

In this embodiment, the transfer of data from the read channel processor 13 to the demodulation unit 14 is
In order for the demodulation unit 14 to be in a bit unit that is convenient for both the address and the data, the decoded data is a 6-channel parallel, which is the least common multiple of both, and the clock is a 6-frequency-divided clock.

That is, as shown in FIG. 3, the data bus is set to be three-channel parallel, and the channel bits to be transferred between the address part and the data part are switched between three-channel parallel and two-channel parallel. If the synchronous clock is divided by 6 rather than switching also by 2 divided clocks, the pulse width becomes 23.2.
Since it is as long as 1 ns, a sufficiently safe transfer speed can be ensured even when the reference clock is as high as 130 MHz. If the data is also made to be 6-channel parallel, the demodulation unit 14
However, it is convenient if the processing is performed in six channels in parallel.

The operation inside the read channel processor 13 will be described with reference to FIGS. The three-channel clock wck based on the three-channel bit data Ad of the address decoded inside the read channel processor 13 and the synchronization clock obtained by the PLL unit of the wobble processing unit 12c
Is supplied to the 6-channel parallel conversion unit 31. Similarly, a 2-channel clock rck based on the 2-channel bit data D of the data and the synchronous clock obtained by the PLL unit of the RF processing unit 12a is converted to a 6-channel parallel conversion unit 32.
Supplied to 6-channel parallel conversion units 31 and 32
As described above, the three-channel bit data Ad of the address and its clock wck, and the two-channel bit data of data D and its clock rck are, as described above, 6-channel parallel data, which is the least common multiple of both, and 6 minutes for the clock. The clock is supplied to the data changeover switch 34 and the clock changeover switch 35 of the changeover section 33 as a clock. The switching section 33 switches the switches 34 and 35 in conjunction with each other by the data gate pulse GD. When the data gate pulse GD is H, the 6-channel parallel data of the data section and the divide-by-6 clock, and the data gate pulse GD is output. In the case of L, the address part 6
Demodulator 14 converts channel parallel data and 6-divided clock
To supply.

FIG. 5A shows the timing at which the parallel conversion unit 32 outputs the 2-channel parallel data and the divide-by-2 clock rck2 as 6-channel parallel data and the divide-by-6 clock rck6. Further, the parallel conversion unit 31 outputs two-channel parallel data and a two-frequency-divided clock.
FIG. 5B shows the timing at which wck2 is output as 6-channel parallel data and a 6-frequency-divided clock wck6. Then, the switching unit 33 switches the switches 34 and 35 according to the data gate pulse (output signal switching timing signal) GD, and outputs a signal of 6 channels parallel and a clock output (rck6 / wck6) output to the demodulation unit 14.
Is shown in FIG. 5C.

As described above, since the channel bit data is transferred from the read channel processor 13 to the demodulation unit 14 based on the data transfer method of the present invention inside the optical disk recording / reproducing apparatus of the above embodiment, the address unit and the data When the sections are transferred by a shared data bus, data can be transferred in bit units, which is convenient for demodulation by either of the demodulation sections.

In the case where the channel clock is very fast so as to exceed 100 MHz, a 6-frequency-divided clock with a duty of 50% can be easily produced from the 2-frequency-divided clock used for the internal processing of the read channel processor.

Even if the channel clock is very fast so as to exceed 100 MHz, a sufficiently safe transfer rate can be ensured with the 6-divided clock.

The present invention can be applied to, for example, a combination of EFM modulation and 1,7PP modulation in addition to the above embodiment. EFM with 8 channel bits as 14 data bits
Method, two channel bits as one data bit,
If 8 channels parallel, which is the least common multiple of the 7PP system, is used, and the synchronous clock is also a divide-by-8 clock, data transfer in a bit unit convenient for demodulating either of them is possible.

[0034]

According to the present invention, when data is transferred between a channel bit of an address and a channel bit of data on a shared data bus, data transfer in a bit unit which is convenient for demodulation by the demodulation unit is performed. Can be possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an optical disc recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a connection relationship among a read processor, a read channel processor, and a demodulation unit.

FIG. 3 is a diagram for explaining a clock in the conventional data transfer method and a clock in the data transfer method of the present invention.

FIG. 4 is a diagram showing a main part for describing an operation of the read channel processor.

FIG. 5 is a timing chart for explaining the operation of the read channel processor.

[Explanation of symbols]

11 OP head, 12 read processor, 13 read channel processor, 14 demodulation unit (DSP), 1
5 Data Manager

Claims (7)

[Claims] 1. A data transfer method for transferring, to a demodulation unit, address information having different modulation schemes and decoded data of recording data obtained from a read signal of a disk-shaped recording medium, wherein the decoded data of the address information and the recording data is provided. Data transfer method using the least common multiple clock of the two decoded data and the least common multiple parallel transfer. 2. The method according to claim 1, wherein when the modulation schemes of the address information and the recording data are different from each other and the shortest inversion interval of the channel bit is different, the parallel transfer of the least multiple is performed with the least common multiple clock. The data transfer method according to claim 1. 3. The apparatus according to claim 1, wherein the address information and the decoded data of the recording data from a disk-shaped recording medium in which an address information area and a recording / reproducing area are alternately arranged are transferred to a demodulation unit. Data transfer method described. 4. A head means for reading a signal from a disk-shaped recording medium, a reproduction processing means for performing a reproduction process on a signal from the head means, and address information having a different modulation method from the output of the reproduction processing means. Decoding processing means for decoding data, transferring the decoded data with a least common multiple clock, and transferring the least common multiple in parallel, and demodulating means for demodulating the decoded data transferred from the decoding processing means into recording data. A data reproducing apparatus characterized by the above-mentioned. 5. The decoding processing means according to claim 1, wherein when the modulation schemes of the address information and the recording data are different from each other and the shortest inversion interval of the channel bit is different, a parallel transfer of a minimum multiple with a clock of a least common multiple is performed. The data reproducing apparatus according to claim 4, wherein the data reproduction is performed. 6. The apparatus according to claim 4, wherein said head means reads a signal from a disk-shaped recording medium in which an address information area and a recording / reproducing area are alternately arranged.
A data reproducing apparatus according to claim 1. 7. The data reproducing apparatus according to claim 4, wherein said reproduction processing means performs RF processing, wobble processing and servo processing on the signal reproduced by said head means.