JP2001128364A - Series compensation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a series compensation apparatus in which the influence of harmonics is suppressed, in which the impedance of every phase is calculated and in which the impedance of every phase of a three-phase AC power transmission line is controlled according to the calculated impedance of every phase. SOLUTION: A detection voltage Vu and a detection voltage V'u across both ends of a series capacitor Cu as well as a current Iu flows in a power transmission line are sampled sequentially by a sampling circuit 42. The difference between the sampled voltage Vu and the sampled voltage V'u is found by a subtraction circuit 44. In addition, on the basis of the voltages across both ends of the capacitor by the computing operation of the subtraction circuit 44 and on the basis of the current Iu by the output of the sampling circuit 42, the fundamental-wave component of the voltages across both ends and the fundamental-wave component of the current Iu are found by a filtering circuit 46. The voltages across both ends and the current are converted into digital amount by an analog-to-digital conversion circuit 48. On the basis of the voltages and the current which are converted into digital amount, the impedance of the power transmission line is calculated by a division circuit 50. According to its calculated value, the firing phase angle of a thyristor is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a series compensator, and more particularly to a series compensator suitable for controlling the impedance of a three-phase AC transmission line for each phase.

[0002]

2. Description of the Related Art In an AC system composed of three-phase AC transmission lines, it is considered that the three-phase AC transmission line is effective for improving the steady state stability and transient stability. A series compensation system in which a series capacitor is inserted in series is employed. This system is widely used in Northern Europe, North and South America, where many long-distance transmission lines are used.

When the series compensation system is applied to an AC transmission line, if the amount of compensation is increased in order to increase the compensation effect, the electric power generated by L (inductance) of the transmission line and generator and C (capacity) of the series compensator is increased. The typical resonance frequency approaches the commercial frequency, and the torsion of the generator (SSR) becomes a problem. As a countermeasure, a thyristor controlled series capacitor (TCS) that changes the capacity of the series capacitor with a thyristor
C) was developed mainly by the United States Electric Power Research Institute (EPRI), and is being tested in the field. If accumulated overseas operation results from this demonstration test, etc., thyristor-controlled series capacitors can be used to improve voltage stability and steady state / transient stability even in Japan's power system where voltage stability is a problem under heavy load. Is likely to be used.

[0004]

SUMMARY OF THE INVENTION In controlling the impedance of an AC transmission line using a series compensation system,
Conventionally, as a control method of a thyristor control series capacitor, a three-phase control method has been studied. In this control method, control is performed using an average value or an effective value of voltages and currents for three phases. However, even if this control method is simply adopted, if the impedance of the transmission line is unbalanced among the phases due to non-twisting and load variations, the impedance of each phase cannot be controlled as specified by the command value. Also, it is not possible to suppress the imbalance or variation in the impedance of each phase. In other words, since the series capacitor is inserted in series with the transmission line, if the thyristor control series capacitor is not properly controlled, the control of each phase for suppressing imbalance will give a disturbance to the system, and May promote equilibrium. Therefore, a method of detecting the impedance for each phase and controlling the impedance of each phase according to the detected impedance has been studied. However, even if this method is simply adopted, accurate impedance cannot be calculated when the impedance of each phase is affected by harmonics.

It is an object of the present invention to calculate the impedance of each phase while suppressing the influence of harmonics, and to control the impedance of each phase of a three-phase AC transmission line in accordance with the calculated impedance of each phase. A compensating device is provided.

[0006]

In order to achieve the above object, a series capacitor inserted in each phase of a three-phase AC transmission line and an AC reactor connected in parallel to the series capacitor of each phase are provided. A switching element connected in series to the AC reactor of each phase to control a phase of a current flowing through the AC reactor of each phase in response to a firing pulse signal of each phase; and A current detecting means for detecting a current; a voltage detecting means for detecting a voltage across the series capacitor of each phase; a fundamental frequency component of a current for each phase extracted from a current detected by the current detecting means; A filtering means for extracting a fundamental frequency component of a voltage of each phase from a detection voltage of the detection means; a current of each phase extracted by the filtering means; Impedance calculating means for calculating the impedance of each phase based on the calculation of the ignition phase angle with respect to the switching element of each phase according to the deviation between the impedance command value of each phase and the calculated value of the impedance calculating means. Command value generating means for generating a command value of a control angle in accordance with each calculation result; and a firing pulse signal for each phase according to the command value of each phase generated by the command value generating means. A series compensator comprising a firing pulse signal generating means for outputting a signal to the switching element of each phase.

[0007] In configuring the series compensator,
An analog-to-digital converter for converting the current of each phase and the voltage of each phase extracted by the filtering means into a digital quantity instead of the impedance calculating means; and a digital quantity converted by the analog-to-digital conversion means. An effective value calculating means for calculating an effective value of the current of each phase from the current of the phase and calculating an effective value of the voltage of each phase from the voltage of the digital amount converted by the analog / digital converting means; It is also possible to provide an impedance calculating means for calculating the impedance of each phase according to the calculated value.

In configuring the series compensator, first voltage detecting means for detecting a voltage at one end of a series capacitor for each phase, instead of the voltage detecting means for both ends, and series capacitor for each phase. A second voltage detecting means for detecting a voltage at the other end of the first and second terminals, and a voltage between both ends of the series capacitor of each phase is calculated from a difference between a detected voltage of the first voltage detecting means and a detected voltage of the second voltage detecting means. A voltage calculating means for extracting the fundamental frequency component of the current of each phase from the current detected by the current detecting means as the filtering means, and extracting the fundamental frequency component of the voltage of each phase from the calculated value of the voltage calculating means. One having the function of extracting can be used.

In configuring each of the series compensating devices, the following elements can be added.

The impedance calculation means includes a limiter for limiting the calculated impedance value to an upper limit or a lower limit.

According to the above-described means, when extracting the impedance of each phase, the fundamental component of the current of each phase and the fundamental frequency component of the voltage of each phase are extracted.
Because the impedance of each phase is calculated based on the extracted current and voltage of each phase, it is possible to calculate the impedance that suppresses the influence of harmonics.
The impedance of each phase can be accurately calculated.
Further, a firing phase angle for the switching element of each phase is calculated according to the deviation between the calculated impedance of each phase and the impedance command value of each phase, and a control angle command value is generated according to each calculation result. Since the firing pulse signal according to the command value is given to the switching element of each phase to control the impedance of each phase, the impedance between the phases may be unbalanced due to non-twisting of the transmission line or variation of the load. Also, it is possible to stabilize the impedance of each phase and to suppress imbalance and variation of each phase.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram of a series compensator showing one embodiment of the present invention. In FIG. 1, three-phase (U-phase, V-phase, and W-phase) AC transmission lines 14, 16, and 18 connecting the AC systems 10 and 12 include transmission lines 14, 1 and 2, respectively.
6, 18 impedance (reactors 20u, 20
In order to compensate (cancel) impedances represented by v, 20w, 22u, 22v, and 22w, series capacitors Cu, Cv, and Cw are inserted in series, respectively. In each of the series capacitors Cu, Cv, Cw, AC reactors Lu, Lv, Lw are provided with thyristors Thu, Thx,
They are connected in parallel via Thv, Thy, Thw, and Thz. U-phase thyristors Thu, Thx, V-phase thyristors Thv, Thy, W-phase thyristors Thw, Thy
hz are connected in antiparallel to each other to form AC reactors Lu and L
v, Lw and series capacitors Cu, Cv, Cw, respectively. Each of the thyristors Thu to Thz is configured as a switching element that controls the phase of a current flowing through each of the reactors Lu, Lv, and Lw in response to a firing pulse signal from the control device 24, and includes series capacitors Cu, Cv, Cw, AC reactor Lu, L
It is configured as a thyristor controlled series capacitor together with v and Lw.

The AC transmission lines 14, 16 and 18 are provided with AC current detectors 26u, 26v and 26w as current detecting means for detecting the current of each phase.
AC voltage detectors 28u, 28v, 28w as first voltage detecting means for detecting voltages at one ends of the series capacitors Cu, Cv, Cw of the respective phases are connected to the AC transmission lines 14, 1
6, 18 connected to the series capacitors Cu, C of each phase.
AC voltage detectors 28u ', 28v', 28w 'as second detecting means for detecting voltages at the other ends of v and Cw are connected to the AC transmission lines 14, 16, 18. Each of the AC current detectors 26 u to 26 w and the AC voltage detectors 28 u to 28 u
The outputs of 8w 'are input to the control device 24, respectively.

As shown in FIG. 2, the control device 24 includes impedance detection circuits 30u, 30v, 30w, impedance control circuits 32u, 32v, 32w, and a switching circuit 3.
4. Synchronous signal detection circuit 36, synchronous signal creation circuit (PL
L) 38 and a pulse phase shift circuit (APS) 40. An impedance detection circuit 30u for each phase,
30v and 30w are AC voltage detectors 28u to 28w, 2
8u 'to 28w' together with series capacitors Cu and C of each phase
v and Cw, and has a function as a voltage detection means for detecting both ends of the voltage between the two terminals.
28w and the AC voltage detectors 28u 'to 28w'
From the difference between each detection voltage and the series capacitor Cu of each phase,
It is configured to have a function as voltage calculation means for calculating the voltage between both ends of Cv and Cw. Further, the impedance detection circuits 30u, 30v, and 30w of each phase include detection currents of the AC current detectors 26u to 26w and AC current detectors 28u to
It is configured to have a function as impedance calculating means for calculating the impedance of each phase based on the detected voltages of 28w and 28u 'to 28w'.

More specifically, as shown in FIG. 3, the impedance detection circuits 30u, 30v and 30w of each phase include a sampling circuit 42, a subtraction circuit 44, a filtering circuit 46, an analog / digital conversion circuit 48, and a division circuit 5
0. In FIG. 3, U
Only the configuration of the phase impedance detection circuit 30u is shown, and the V-phase and W-phase impedance detection circuits 30u are shown.
v and 30w are omitted because they have the same configuration as the U-phase impedance detection circuit 30u.

The sampling circuit 42 includes a U-phase instantaneous voltage Vu, detected by the AC current detectors 28u and 28u '.
It is configured as sampling means for sequentially sampling V′u and the instantaneous current Iu of the U phase detected by the AC current detector 26u at intervals of Δt. When sampling an analog amount of AC voltage and AC current in the sampling circuit 42, as shown in FIG.
Eight sampling data are extracted during a half cycle at a sampling frequency of z, and the data sampled by the sampling circuit 42 is input to a subtraction circuit 44 and a filtering circuit 46, respectively. The subtraction circuit 44 is configured as a voltage calculation means that calculates a difference between the voltage Vu and the voltage Vu ′ sampled by the sampling circuit 42 and obtains the calculated value as a voltage across the U-phase series capacitor Cu. The operation value of the circuit 44 is input to the filtering circuit 46. The filtering circuit 46 is configured as a filtering means for extracting the fundamental frequency component of the U-phase voltage from the operation value of the subtraction circuit 44 and extracting the fundamental wave component of the U-phase current based on the output to the sampling circuit 42. It has a function as a memory for storing input data and operation data. When filtering the input data in the filtering circuit 46, as shown in FIG. 4, eight sampled data are sequentially taken in during a half cycle.
At the next sampling time point after Δt, the oldest data among the eight data is erased, new data is taken in instead of the erased data, and filtering is always performed with the newest eight data. The filtered data is input to the analog-to-digital conversion circuit 48 as data from which harmonic components have been removed. The analog-to-digital conversion circuit 48 is configured as analog-to-digital conversion means for converting the filtered voltage data and current data into digital quantities, respectively. Is done.

The dividing circuit 50 has a function as an effective value calculating means for obtaining the effective values of the digitally converted voltage data and the current data based on the digitally converted data. It has a function as an impedance calculating means for calculating the U-phase impedance according to the effective value. Further, the division circuit 50 has a function as a limiter that limits the calculated impedance value to an upper limit value or a lower limit value.

In obtaining the effective value from the input data in the division circuit 50, the effective value of the voltage or current is calculated from the digitally converted voltage or current data X (i) (i = 1,..., 8) by the following equation. Can be obtained according to

Effective value X = [√ΣX (i) × X (i)] / 8 where i = 1 to 8 In general, when data is sampled n times in a half cycle, filtering is also performed on n data. To use
When the effective value is obtained from this data, the effective value can be obtained according to the following equation.

Effective value X = [√ΣX (i) × X (i)] / n Here, i = 1 to n By the above-described effective value calculation, the U-phase series is obtained from the instantaneous instantaneous voltage and current for each sampling. After the effective voltage value V (t) at both ends of the capacitor Cu and the effective current value I (t) flowing through the U-phase are obtained, the dividing circuit 50 performs the effective voltage value V (t) and the effective current value I (t). The instantaneous impedance Z (t) is obtained from the following equation.

Z (t) = V (t) / I (t) Here, a subtraction circuit 44 for calculating the voltage across the series capacitor Cu from the difference between the detection voltages of the AC voltage detectors 28u and 28u 'is used as a filtering circuit. In the stage preceding 46, instead of storing the data of the detected voltages of the AC voltage detectors 28u and 28u ', respectively, only the voltage of the difference between the detected voltages is stored. And the memory capacity of the filtering circuit 46 is reduced. The filtering circuit 46
The reason why the analog-digital conversion circuit 48 is provided at the subsequent stage is that even if noise is superimposed on the detection currents of the AC voltage detectors 28u and 28u 'and the AC current detector 26u, the noise is removed by the filtering circuit 46. This is because the erroneous conversion when converting the analog amount into the digital amount in the analog / digital conversion circuit 48 is minimized.

Further, the dividing circuit 50 is provided with a predetermined upper limit value and lower limit value limiter. When the detection current of the AC current detector 26u becomes zero, the impedance Z (t ) = Infinity is suppressed to a finite upper limit, and an impedance control circuit 32u described later is used.
In order to obtain a stable operation.
In this case, the upper limit value is set to, for example, a value of 3 to 10 times the normal impedance value, and the lower limit value is set to a value of -3 to -10 times the normal impedance value.
Here, the reason why the lower limit is given a negative value is to discriminate between the capacitive and inductive characteristics of the impedance. That is, as shown in FIG. 5, when the impedance of the AC transmission line is capacitive, the voltage Vc across the series capacitor Cu is delayed by 90 degrees with respect to the current i flowing through the series capacitor Cu. , The voltage VI across the series capacitor Cu with respect to the current flowing through the series capacitor Cu
Is advanced by 90 degrees. Therefore, it is determined whether the current i is capacitive or inductive based on the polarity of the voltage at the time ts1 or ts2 when the current i changes from negative to positive. In FIG. 5, when the polarity of the voltage is positive, the voltage is inductive, and when the voltage is negative, the voltage is capacitive.
In the case of ３０30 w, inductive and capacitive detections are also performed.

On the other hand, the impedance control circuits 32u, 32v and 32w shown in FIG.
And each of the impedance detection circuits 30u, 30v, 30w
The firing phase angle (β) with respect to the thyristors Thu to Thz of each phase is calculated according to the deviation from the impedance calculation value of each phase due to the calculation of the control angle, and the control angle command values (αu, αx, αv) , Αy, αw, αz). The impedance control circuits 32u, 32v, and 32w provide a firing phase angle β
Is converted to a control angle (control delay angle) α. Specifically, zero degree of the firing phase angle β corresponds to 180 degrees of the control angle α. When each thyristor is actually fired, the control timing α is set to zero degree and the ignition timing is set to the synchronization reference point. It needs to be set,
The firing phase angle β is converted to the control angle α. In this case, since there is a difference of 180 degrees between the firing phase angle β and the control angle α, the control angle α is calculated by calculating the control angle α = 2π−β, and the calculated control angle α is calculated. Output as a command value. The command values based on the outputs of the impedance control circuits 32u, 32v, and 32w are input to the pulse phase shift circuit 40 via the switching circuit 34, respectively. The switching circuit 34 controls each of the impedance control circuits 32 u to 3 u according to the output pulse of the pulse phase shift circuit 40.
The command values output from 2w are sequentially switched and output to the pulse phase shift circuit 40. The pulse phase shift circuit 40 includes a reference pulse signal S generated based on the synchronization pulse signal Sn detected by the synchronization signal detection circuit 36.
s has been entered.

The synchronizing signal detection circuit 36 includes an AC current detector I detected by the AC current detectors 26u to 26w.
u, Iv, and Iw are taken in, and a synchronous pulse signal generating means for generating a synchronous pulse signal Sn by detecting a synchronous point (zero cross point) which is a zero point of each current is formed. The signal is input to the circuit 38.

The synchronizing signal generation circuit (PLL) 40 has the configuration shown in FIG.
As shown in FIG. 5, a phase difference detection circuit (DET) 52, an operational amplifier circuit (CAL) 54, and a voltage control oscillator (OSC) 5
6. A frequency divider (DEC) 58 is provided.

The phase difference detection circuit 52 detects the phase difference Δθ between the synchronization pulse signal Sn detected by the synchronization signal detection circuit 36 and the reference pulse signal Ss output from the frequency dividing circuit 58, as shown in FIG. The signal of the detected phase difference Δθ is output to the operational amplifier circuit 54. The operational amplification circuit 54 controls and amplifies the phase difference Δθ, amplifies the same, and outputs a control voltage Ec corresponding to the phase difference Δθ. That is, the phase difference detection circuit 52 and the operational amplification circuit 54
Are configured as control voltage generation means. The control voltage Ec from the output of the operational amplifier circuit 54 is input to the control voltage oscillation circuit 56. The control voltage oscillation circuit 56
The oscillation frequency changes in proportion to the average value of the control voltage Ec,
It is configured as a voltage controlled oscillating means for outputting a pulse signal corresponding to the oscillation frequency, and this pulse signal is input to the frequency dividing circuit 58. The frequency dividing circuit 58 functions as a decoder, frequency-divides a pulse signal output from the voltage controlled oscillation circuit 56 into a pulse signal having a frequency six times the commercial frequency, and uses the frequency-divided pulse signal as a reference pulse signal Ss. It is configured as a reference pulse signal generating means for outputting. That is, in order to generate reference pulse signals for the six thyristors Thu to Thz, the frequency oscillating at a high frequency is divided to six times the commercial frequency to generate the reference pulse signal Ss. I have.

The synchronizing signal generation circuit 38 having the above configuration
When the difference (phase difference) Δθ between the synchronizing pulse signal Sn and the reference pulse signal Ss is controlled by the first-order advance / delay in the operational amplifier circuit 54, the operational amplifier circuit 54 , FIG.
Is output from the control voltage oscillation circuit 56, and a pulse signal having an oscillation frequency corresponding to the average voltage of the control voltage Ec is output. By dividing the frequency by six times, a reference pulse signal for each thyristor is generated.

Here, the frequency of the system rises and the current Iu
Is assumed to have advanced beyond the voltage, since the phase of the synchronization pulse signal Sn advances, the phase difference Δθ due to the output of the phase difference detection circuit 52 increases, and the control voltage Ec due to the output of the operational amplifier circuit 54 also increases. . Therefore, the oscillation frequency of the control voltage oscillation circuit 56 increases, and the phase of the reference pulse signal Ss by the output of the frequency dividing circuit 58 also advances. In this way, control following the frequency of the system is performed.

On the other hand, when the frequency of the system falls,
Since the phase of the synchronization pulse signal Sn is delayed, the phase difference Δθ due to the output of the phase difference detection circuit 52 decreases, and the control voltage Ec due to the output of the operational amplifier circuit 54 also decreases. Therefore, the oscillation frequency of the control voltage oscillation circuit 56 decreases,
The phase of the reference pulse signal Ss due to the output of the frequency dividing circuit 58 is also delayed. In this way, control following the frequency of the system is performed. That is, the synchronizing signal generation circuit 38 operates so that the reference pulse signal Ss output from the frequency dividing circuit 58 always follows the zero point of the system current and a certain phase difference. The reference pulse signal Ss generated by the synchronization signal generation circuit 38 is input to the pulse phase shift circuit 40.

A pulse phase shift circuit (APS) 40 shifts the reference pulse signal Ss input from the synchronizing signal generation circuit 38 according to the command value input from the switching circuit 34 to generate an ignition pulse signal. It is configured as a firing pulse signal generating means for outputting the firing pulse signal to each of the thyristors Thu to Thz.

More specifically, as shown in FIG. 8, the firing pulse signals of the thyristors Thu to Thz of each phase are U⇒Z⇒V
⇒X⇒W⇒Y, that is, thyristors Thu, T
π / 6 in the order of hz, Thv, Thx, Thw, Thy
It is late by each. For example, in the case of the U phase, the Ssu point is the generation timing of the reference pulse signal Ss generated by the synchronization signal generation circuit 38, that is, the phase of the voltage across the U-phase series capacitor Cu is 0 degree (command value α = 0 degree). ), When the command value generated by the impedance control circuit 32u is αu, in response to the reference pulse signal Ssu, the pulse Pu shifted by the command value αu is used as a firing pulse signal for the thyristor Thu as the pulse phase shift circuit 40. Output from When this firing pulse signal Pu is output, the switching circuit 34 switches the output signal,
Command value αz is output from impedance control circuit 32w. As a result, in the pulse phase shift circuit 40, π / 6
The pulse signal is switched to the next delayed reference pulse signal Ssz, and a pulse signal obtained by shifting the reference pulse signal Ssz by the command value αz is output to the thyristor Thz as the firing pulse signal Pz. When the firing pulse signal Pz is output, the pulse phase shift circuit 40 switches to the reference pulse signal Ssv delayed by π / 6 from the reference pulse signal Pz as the next pulse, and changes the reference pulse signal Ssv by the command value αv. The shifted pulse signal is output to thyristor Thv as firing pulse signal Pv. Hereinafter, similarly, the firing pulse signals Px, Pw, Py obtained by shifting the reference pulse signals Ssx, Ssw, Ssy by the command values αx, αw, αy become π /
Each thyristor Thx, Th at a timing delayed by 6
w and Thy are sequentially output.

In the above configuration, when compensating the impedance of each of the AC transmission lines 14, 16, and 18 using the series compensator, a firing phase angle for operating in a capacitive impedance region during a steady operation is obtained. In the event of a system failure, in order to suppress overvoltage generated in the series capacitors Cu to Cw, a process is performed in which each thyristor is fully conducted (full conduction) to determine a firing phase angle for operation in a capacitive impedance region. It is. In this case, as shown in FIG. 9, the firing phase angle β is determined depending on whether the impedance command value Zp input to the control device 24 indicates the capacitive impedance Zc or the inductive impedance Zl.

FIG. 9 is a diagram showing the impedance characteristics of each thyristor with respect to the firing phase angle on the horizontal axis, where the positive region indicates the capacitive impedance and the negative region indicates the inductive impedance. When the angle between 180 ° and 0 ° as the phase of the voltage across the series capacitor is represented by the firing phase angle β, when β = 0 °, no current flows through the reactors Lu to Lw. The impedance of the compensator is the same as the impedance of the series capacitors Cu to Cw, Zc0 = 1 / ωC (ω = 2πf, f; commercial frequency)
It is. Here, as the value of the firing phase angle β of the thyristor is increased, the current flowing through the reactors Lu to Lw increases, and the impedance becomes large capacitively up to the firing phase angle of βlim. βlim indicates the firing phase angle at which the series capacitor and the AC reactor resonate at the commercial frequency,
At a firing phase angle exceeding this value, the current flowing through the reactors Lu to Lw becomes larger than the current flowing through the series capacitors Cu to Cw, and the impedance of the series compensator becomes an inductive impedance. Further, as the firing phase angle β increases, the inductive impedance decreases, and each thyristor becomes fully conductive when β = 90 degrees. The impedance at this time is the parallel impedance of the AC reactor and the series capacitor, that is, the inductive impedance Z10. The impedance with respect to the firing phase angle β can be obtained by the following equation from the ratio between the fundamental wave voltage and the fundamental wave current of the transmission line.

Impedance Xtcsc = πωL / (π
ω2LC-2β + sin2β) As described above, by adjusting the firing phase angle β, the impedance of each transmission line can be adjusted in the range from the capacitive region to the inductive region.

As described above, in the present embodiment, before calculating the impedance of each phase, the voltage of each phase,
Since the fundamental component of the current of each phase is extracted from the current and the fundamental component of the current of each phase, the influence of harmonics is suppressed even when the impedance is calculated from these values. Can be accurately obtained. Further, a firing pulse signal for each phase thyristor is obtained based on the calculated deviation between the impedance of each phase and the impedance command value, and the thyristor of each phase is controlled according to the firing pulse signal. Even if there is an imbalance in the impedance between each phase due to non-twisting and load variations, the impedance of each phase can be controlled in a stable state and the imbalance and variation in each phase can be suppressed. .

[0036]

As described above, according to the present invention,
When extracting the impedance of each phase, the fundamental frequency component of the current of each phase and the fundamental frequency component of the voltage of each phase are extracted, and each phase is extracted based on the current of each phase and the voltage of each phase. Is calculated, the impedance in which the influence of harmonics is suppressed can be calculated, and the impedance of each phase can be calculated accurately. Further, a firing phase angle for the switching element of each phase is calculated according to the deviation between the calculated impedance of each phase and the impedance command value of each phase, and a control angle command value is generated according to each calculation result. Since the firing pulse signal according to the command value is given to the switching element of each phase to control the impedance of each phase, the impedance between the phases may be unbalanced due to non-twisting of the transmission line or variation of the load. Also, it is possible to stabilize the impedance of each phase and to suppress imbalance and variation of each phase.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a series compensation device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a control device.

FIG. 3 is a block diagram of an impedance detection circuit.

FIG. 4 is a waveform chart for explaining the operation of the sampling circuit.

FIG. 5 is a diagram for explaining a relationship between inductive impedance and capacitive impedance.

FIG. 6 is a block diagram of a synchronization signal generation circuit.

FIG. 7 is a waveform chart for explaining the operation of the synchronization signal generation circuit.

FIG. 8 is a waveform chart for explaining the operation of the pulse phase shift circuit.

FIG. 9 is a characteristic diagram showing a relationship between a firing phase angle and impedance.

[Explanation of symbols]

Cu, Cv, Cw Series capacitors Lu, Lv, Lw AC reactor Thu, Thx, Thv, Thy, Thw, Thz Thyristor 10, 12 AC system 14, 16, 18 AC transmission line 20u, 20v, 20w, 22u, 22v, 22w AC reactor 24 Controller 26u, 26v, 26w AC current detector 28u, 28v, 28w, 28u ', 28v'28w'
AC voltage detector 30u, 30v, 30w Impedance detection circuit 32u, 32v, 32w Impedance control circuit 34 Switching circuit 36 Synchronization signal detection circuit 38 Synchronization signal creation circuit 40 Pulse phase shift circuit 42 Sampling circuit 44 Subtraction circuit 46 Filtering circuit 48 Analog Digital conversion circuit 50 Divider circuit 52 Phase difference detection circuit 54 Operational amplifier circuit 56 Voltage controlled oscillator circuit 58 Frequency divider circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Teru Kikuchi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yasuo Morioka 3-chome Nakanoshima, Kita-ku, Osaka-shi, Osaka No. 3-22 Kansai Electric Power Co., Inc. F term (reference) 5G066 FA01 FB08 FC04 FC12 5H420 BB03 BB12 CC05 DD04 DD10 EA03 EA44 EB05 EB11 EB25 FF03 FF04 GG01 LL02 5H740 AA01 BA01 BB03 BB09 BC01 BC02 BC06 MM01 MM01MM

Claims (4)

[Claims] 1. A series capacitor inserted in series with each phase of a three-phase AC transmission line, an AC reactor connected in parallel to the series capacitor of each phase, and a series capacitor connected in series with the AC reactor of each phase. A switching element for controlling a phase of a current flowing through the AC reactor of each phase in response to a firing pulse signal of each phase; current detection means for detecting a current of the AC transmission line of each phase; Voltage detecting means for detecting the voltage across the series capacitor, and extracting the fundamental frequency component of the current of each phase from the detected current of the current detecting means, and calculating the basic voltage of each phase from the detected voltage of the voltage detecting means. Filtering means for extracting frequency components, and impedance of each phase is calculated based on the current and voltage of each phase extracted by the filtering means. Impedance calculating means, calculating a firing phase angle with respect to the switching element of each phase according to a deviation between the impedance command value of each phase and the calculated value of the impedance calculating means, and controlling the control angle according to each calculation result. Command value generating means for generating a value, and generating a firing pulse signal for each phase according to the command value for each phase generated by the command value generating means, and outputting the firing pulse signal for each phase to the switching element for each phase A series compensating device comprising: 2. A series capacitor inserted in series with each phase of the three-phase AC transmission line, an AC reactor connected in parallel with the series capacitor of each phase, and an AC reactor connected in series with the AC reactor of each phase. A switching element for controlling a phase of a current flowing through the AC reactor of each phase in response to a firing pulse signal of each phase; current detection means for detecting a current of the AC transmission line of each phase; Voltage detecting means for detecting the voltage across the series capacitor, and extracting the fundamental frequency component of the current of each phase from the detected current of the current detecting means, and calculating the basic voltage of each phase from the detected voltage of the voltage detecting means. Filtering means for extracting a frequency component, and an analog for converting each phase current and each phase voltage extracted by the filtering means into a digital quantity respectively Calculating the effective value of the current of each phase from the digital amount converted by the analog-to-digital conversion means, and calculating the effective value of each phase from the digital amount converted by the analog-to-digital conversion means; Effective value calculating means for calculating the effective value of the voltage, impedance calculating means for calculating the impedance of each phase according to the calculated value of the effective value calculating means, and the impedance command value of each phase and the calculated value of the impedance calculating means Command value generating means for calculating a firing phase angle with respect to the switching element of each phase according to the deviation and generating a command value of a control angle in accordance with each calculation result; and Generates a firing pulse signal of each phase according to the command value and outputs the firing pulse signal of each phase to the switching element of each phase. Series compensator comprising a firing pulse signal generating means point that. 3. A series capacitor inserted in series with each phase of the three-phase AC transmission line, an AC reactor connected in parallel to the series capacitor of each phase, and a series capacitor connected in series with the AC reactor of each phase. A switching element for controlling a phase of a current flowing through the AC reactor of each phase in response to a firing pulse signal of each phase; current detection means for detecting a current of the AC transmission line of each phase; First voltage detecting means for detecting the voltage at one end of the series capacitor, second voltage detecting means for detecting the voltage at the other end of the series capacitor for each phase, and the detected voltage of the first voltage detecting means. Voltage calculating means for calculating the voltage across the series capacitor of each phase from the difference between the detected voltage of the second voltage detecting means and the fundamental voltage component of the current of each phase from the detected current of the current detecting means. A filtering means for extracting and extracting a fundamental frequency component of a voltage of each phase from a calculation value of the voltage calculation means; and an analog for converting each phase current and each phase voltage extracted by the filtering means into a digital quantity. Calculating the effective value of the current of each phase from the digital amount converted by the analog-to-digital conversion means, and calculating the effective value of each phase from the digital amount converted by the analog-to-digital conversion means; Effective value calculating means for calculating the effective value of the voltage, impedance calculating means for calculating the impedance of each phase according to the calculated value of the effective value calculating means, and the impedance command value of each phase and the calculated value of the impedance calculating means The firing phase angle for the switching element of each phase is calculated according to the deviation. Command value generating means for generating a control angle command value according to each calculation result, and generating a firing pulse signal for each phase in accordance with the command value for each phase generated by the command value generating means. A series compensator comprising: a firing pulse signal generating means for outputting a firing pulse signal to the switching element of each phase. 4. The apparatus according to claim 1, wherein said impedance calculation means includes a limiter for limiting the calculated impedance value to an upper limit value or a lower limit value.
A series compensator as described.