JP2001127815A - Modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read/write data outputting an optimal modulated signal to each of IC cards, which can be accessed by respectively different amplitude transit modulated signals. SOLUTION: A modulation circuit 12 for a card reader/writer is provided with a driver DRV, a driving transistor Q composed of transistors Q1 and Q2 and a bias part 12B composed of resistors R1-R3. When a switching signal (b) is L, a voltage +V or 0 corresponding to H/L of a transmitting code (a) is impressed from the bias part to the gate of the transistor, the transistor is turned on/off and the modulated signal of modulation factor 100% is outputted from the transistor Q, to which the carrier signal is inputted. When the switching signal (b) is H level, on the other hand, a voltage +V or +(V-ΔV) corresponding to H/L of the transmitting code is impressed from the bias part to the gate of the transistor, and the modulated signal of modulation factor 100% is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a modulation circuit for modulating the amplitude of a carrier signal according to an input signal.

[0002]

2. Description of the Related Art This type of modulation circuit shifts the amplitude of a carrier signal in accordance with binary information of an input signal. Such amplitude shift keying is performed by ASK (amplitt).
For example, type A modulation that shifts the amplitude of a carrier signal to a modulation factor of 100% according to “1” or “0” indicating binary information of an input signal, and a value of an input signal “ There is type B modulation in which the amplitude of a carrier signal is shifted to a modulation factor of 10% according to "1" and "0".

FIG. 6 is a waveform chart for explaining the principle of amplitude shift keying. The modulation factor of the amplitude shift keying can be expressed as: modulation factor = {(xy) / (x + y)} × 100 (%). Note that x is an input signal 2
For example, the amplitude voltage of the carrier signal when the value of the value signal is “1” is shown, and y indicates the amplitude voltage of the carrier signal when the value of the binary signal is “0”.

Here, if the carrier signal amplitude voltage y when the binary signal value is “0” is 0 V with respect to the carrier signal amplitude voltage x when the binary signal value is “1”, then the modulation degree = {(X−0) / (x + 0)} × 100 = 100
(%), And a type A modulation signal that shifts the amplitude of the carrier signal to a modulation factor of 100% is generated as shown in FIG. Further, the ratios of the carrier signal amplitude voltages x and y when the binary signal values are “1” and “0” are 100 and 8 respectively.
Assuming 1.8, from the above equation, the modulation degree = {(100-81.8) / (100 + 81.8)} x 100}
10 (%), and as shown in FIG. 6 (c), a type B modulated signal that shifts the amplitude of the carrier signal to a modulation factor of 10% is generated.

Among the type A and type B modulation circuits, the type A modulation circuit that shifts the amplitude of a carrier signal to a modulation factor of 100% in accordance with the input signal value “1” or “0” is Is used for a non-contact IC card reader / writer for reading / writing data from / to an IC card. The non-contact IC card reader / writer writes data to the IC card and reads data from the IC card by transmitting the modulation signal of the modulation circuit to the IC card as a radio signal.

[0006]

In recent years, the amplitude of a carrier signal has been changed by a modulation factor of 1 in accordance with the input signal values "1" and "0".
A type B modulation circuit for shifting to 0% is mounted on a non-contact IC card reader / writer, and a modulation signal of the type B modulation circuit is transmitted to the IC card to read / write data from / to the IC card. That is being considered. However, an IC card reader / writer equipped with such a type B modulation circuit cannot access an IC card for a type A modulation signal already on the market. Therefore, a modulation circuit capable of accessing an IC card reader / writer for both an IC card accessed by a type A amplitude shift keying signal and an IC card accessed by a type B amplitude shift keying signal There is a demand that we want to arrange.

Accordingly, an object of the present invention is to output an optimum amplitude shift keying signal to each IC card which can be accessed by different amplitude shift keying signals, thereby enabling access.

[0008]

According to the present invention, there is provided a modulation circuit for shifting an amplitude voltage of a carrier signal in accordance with a value of a binary signal and outputting an amplitude shift keying signal. , A carrier signal and a binary signal, and a first switching signal for instructing the output of a first amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by a first voltage, and the amplitude of the carrier signal. A driver circuit for selectively inputting a second switching signal for instructing output of a second amplitude shift keying signal for shifting the voltage by a second voltage smaller than the first voltage, and an output side of the driver circuit And a control means for controlling the drive transistor, the control means controlling the drive transistor when the driver circuit receives the first switching signal. Together to output the first amplitude-shift keying signal by controlling the drive transistor in accordance with the values of the signal to the first on-state and off-state, the driver circuit is a second
When the switching signal is input, the driving transistor is controlled to the first ON state and the second ON state in accordance with the value of the binary signal to output the second amplitude shift keying signal. It is characterized by

In this case, the control means inputs one of the first and second switching signals to the first input terminal, inputs a binary signal to the second input terminal, and outputs the input switching signal. OR circuit for outputting the logical sum of the AND signal to the driver circuit via the output terminal, a first resistor having one end connected to the output terminal of the OR circuit, and one end having the other end of the first resistor , And the other end is connected to a second input terminal of the OR circuit, and one end is connected to ground,
And a third terminal whose other end is connected to a connection point of the first and second resistors.
And a bias unit for applying the potential of the connection point to the gate of the drive transistor as a bias voltage, wherein the bias unit is connected to the drive transistor when the driver circuit is inputting the first switching signal. To the gate 2
A third potential and a ground potential corresponding to the value of the value signal are applied to control the driving transistor in the first ON state and the OFF state, and when the driver circuit receives the second switching signal, the driving transistor The third potential corresponding to the value of the binary signal and the fourth potential lower than the third potential
To control the driving transistor to the first ON state and the second ON state. Further, one of the first and second switching signals is automatically output to the driver circuit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing a configuration of a non-contact IC card reader / writer to which the modulation circuit according to the present invention is applied. In FIG. 4, a non-contact IC card reader / writer (hereinafter, IC card reader) 1 includes a control unit 11 for controlling the whole of the IC card reader 1 and a carrier signal described later into a data signal output from the control unit 11. A modulation circuit 12, a demodulation circuit 13, and a matching circuit 1
4, a resonance circuit 15, and a power supply unit 16 for supplying power to the above units.

Here, the matching circuit 14 receives the output signal from the modulation circuit 12 and outputs it to the resonance circuit 15, and this output signal is efficiently transmitted from the resonance circuit 15 to
The impedance is matched with the resonance circuit 15 so that the impedance can be transmitted to the C card. The resonance circuit 15
When an antenna coil L1 serving as an inductive element and a capacitive element C1 are connected in parallel, and a modulation signal is given from a modulation circuit 12 via a matching circuit 14, resonance starts to generate a radio signal from the antenna coil L1. The signal is transmitted as a wireless signal to an IC card electromagnetically coupled to the coil L1. The demodulation circuit 13 receives a modulation signal returned from the IC card via the resonance circuit 15 in response to the transmission of the wireless signal, demodulates the modulation signal, extracts data, and outputs the data to the control unit 11. .

The control unit 11 in the IC card reader 1 is connected to the host device 2 via a serial I / F (serial interface). The control unit 11 records data received from the host device 2 on the IC card by performing data communication with the host device 2 via the serial I / F, and transmits data read from the IC card to the host device 2. I do.

FIG. 5 is a block diagram showing the configuration of the IC card which is electromagnetically coupled with the IC card reader 1. As shown in FIG. FIG.
The IC card 3 has an antenna coil L2, a wireless interface 31, a control circuit 32, and a memory 33 in which an ID and information unique to the IC card are stored.

The wireless interface 31 of the IC card 3
When the antenna coil L1 of the IC card reader 1 and the antenna coil L2 of the IC card 3 are electromagnetically coupled, the IC
A power POWER is generated from the radio signal from the card reader 1 and supplied to the control circuit 32 and the memory 33, and a clock signal CLK is generated and supplied to the control circuit, and data DATA is extracted from the radio signal. This is output to the control circuit 32. The control circuit 32 of the IC card 3
When power POWER is supplied from the wireless interface 31, the wireless interface 3 is synchronized with the clock signal CLK.
1 is read, and if the data DATA is write data to the memory 33, it is recorded in the memory 33. If the data DATA is command data for reading data in the memory 33, the data in the memory 33 is read. The data is output to the wireless interface 31.

The operation of the IC card reader 1 and the IC card 3 will be described with reference to FIGS. IC card reader 1
Generates a carrier signal of a predetermined frequency from an oscillator 40 described later provided in the modulation circuit 12 and transmits it as a radio signal via the matching circuit 14 and the resonance circuit 15. Here, when the IC card 3 is placed at a predetermined place on the IC card reader 1, the antenna coils L2 and I
The antenna coil L1 of the C card reader 1 is electromagnetically coupled, and the power POWER is supplied to the IC card 3 by the radio signal of the IC card reader 1 as described above.

The control unit 11 of the IC card reader 1 transmits data from the host device 2 to the IC card 3 through a serial I / O.
When received via F, this data is output to modulation circuit 12. Upon receiving the data from the control unit 11, the modulation circuit 12 performs amplitude shift modulation on the carrier signal according to the input data value, and transmits the carrier signal as a radio signal via the matching circuit 14 and the resonance circuit 15.

When the radio interface 31 of the IC card 3 receives a radio signal from the IC card reader 1 via the antenna coil L2, it extracts data DATA from the radio signal as described above and sends it to the control circuit 32. Output. Here, the control circuit 32 records the received data DATA from the IC card reader 1 in the memory 33 when the data is write data to the memory 33. If the data DATA is command data for reading the data in the memory 33, the data in the memory 33 is sequentially read in synchronization with the above-mentioned clock signal CLK and output to the wireless interface 31 side.

Data sequentially read from the memory 33 of the IC card 3 is transmitted as a radio signal to the IC card reader 1 via the wireless interface 31 and the antenna coil L2. Resonant circuit 15 of IC card reader 1
Receives a radio signal from the IC card 3 and outputs the radio signal to the demodulation circuit 13 as a modulation signal. The demodulation circuit 13 extracts data from the modulated signal by demodulating the modulated signal, and outputs the extracted data in the memory 33 of the IC card 3 to the control unit 11. Control unit 11
Receives the data from the demodulation circuit 13 and transmits this data to the host device 2. In this manner, the IC card reader 1 can write data to the IC card 3 and read data written to the IC card 3.

FIG. 1 is a block diagram showing a configuration of a modulation circuit according to the present invention.
Is used as a modulation circuit. As shown in FIG. 1, the modulation circuit 12 includes an oscillator 40 that generates the above-described carrier signal c having a predetermined frequency, an OR circuit OR, and a buffer circuit B.
UF, driver circuit DRV, and transistors Q1, Q
2 and resistors R1 to R3. Here, the driving transistor Q is configured by the transistor Q1 and the transistor Q2, and the bias unit 12A is configured by the resistors R1 to R3. The bias unit 12A applies a bias voltage e to the driving transistor Q. The control unit 12B is constituted by the bias unit 12A, the OR circuit OR, and the buffer circuit BUF.

The modulation circuit 12 shifts the amplitude of the carrier signal in accordance with the binary information of the input signal, and modulates the amplitude of the carrier signal in accordance with the data values "1" and "0" by a modulation factor of 100. %, And Type B modulation, in which the amplitude of the carrier signal is shifted to a modulation factor of 10% in accordance with data values "1" and "0".

The operation of the modulation circuit 12 will be described with reference to FIG. In FIG. 1, a carrier signal c of an oscillator 40 is output to one input terminal of a driver circuit DRV. Also,
The transmission code a having the data value “1” or “0” from the control unit 11 is output to one input terminal of the OR circuit OR and is output to the input side of the buffer circuit BUF. Further, the switching signal b from the control unit 11 is
Is output to the other input terminal. The OR circuit OR calculates the logical sum of the input transmission code a and the switching signal b and outputs the logical sum to the other input terminal of the driver circuit DRV. When the output of OR circuit OR is at "H" level, driver circuit DRV outputs an inverted signal of carrier signal c to transistor Q1 side, and outputs modulated wave signal d from driving transistor Q including transistors Q1 and Q2.

Here, the bias of the driving transistor Q is given from the above-mentioned bias section 12A. The bias unit 12A is connected to one end of the resistor R1 and one end of a resistor R2 having a value approximately four times the value of the resistor R1, and the other ends of the resistors R1 and R2 are connected to the output side of the OR circuit OR. And the output side of the buffer circuit BUF.
A connection point between the resistors R1 and R2 is connected to a resistor R3 having a value approximately 10 times the value of the resistor R1, and the other end is connected to the ground. The bias unit 12A includes resistors R1 and R2.
Is applied as the bias voltage e to the gate of the driving transistor Q.

When the switching signal b is at the "L" level and the transmission code a is at the "H" level (data value "1"), this "H" level signal is output via the OR circuit OR to the other of the driver circuits DRV. Since the signal is output to the input terminal, the driver circuit DRV inverts the carrier signal c input from one input terminal and outputs the inverted signal to the drive transistor Q as described above. In this case, in the bias unit 12A, assuming that the output potentials of the OR circuit OR and the buffer circuit BUF are the same, the state in which the resistors R1 and R2 are connected in parallel as shown in FIG. Therefore, the voltage at the connection point between the resistors R1 and R3 rises to the voltage value A, and this voltage is applied as a bias for the driving transistor Q, so that the driving transistor Q is turned on (first on state). Thus, a modulated wave signal d having the same amplitude as that of the inverted carrier signal from the driver circuit DRV is output to the matching circuit 14 side.

On the other hand, when the switching signal b is at the “L” level and the transmission code a is also at the “L” level (data value “0”), the “L” level signal from the OR circuit OR is output to the other terminal of the driver circuit DRV. , The output of the driver circuit DRV maintains the “H” level. In this case, a bias voltage e of substantially 0 V (ground level: voltage value C) is applied from the bias unit 12A to the driving transistor Q.
, The driving transistor Q does not turn on, and therefore outputs a high impedance signal to the matching circuit 14 as a modulated wave signal d. Thereby, the drive transistor Q shifts the amplitude of the carrier signal c by 100% in accordance with the values “1” and “0” of the transmission code a (ie, the “H” level and the “L” level of the transmission code a). The modulated signal to be output is output. That is, the modulation circuit 12 operates as a type A modulation circuit when the switching signal b is at the “L” level.

Next, when the switching signal b is at the "H" level and the transmission code a is also at the "H" level (data value "1"), these "H" level signals are passed through the OR circuit OR. The driver circuit DRV outputs an inverted signal of the carrier signal c to the drive transistor Q. In this case, since the bias unit 12A applies the same voltage value as the voltage value A as the bias of the drive transistor Q, the drive transistor Q is turned on (first on state) and the inverted carrier from the driver circuit DRV is turned on. The modulated wave signal d having the same amplitude as the signal amplitude is output to the matching circuit 14.

On the other hand, when switch signal b is at "H" level and transmission code a is at "L" level (data value "0"), OR circuit OV is connected to the other input terminal of driver circuit DRV.
Since an “H” level signal is output from R, driver circuit DRV outputs an inverted signal of carrier signal c to drive transistor Q. In this case, in the bias unit 12A, the output of the OR circuit OR is at “H” level, and the buffer circuit BUF
Is at the "L" level (ground level), so that the resistors R2 and R3 are connected in parallel as shown in FIG. 3B. Therefore, the voltage at the connection point between the resistors R1 and R2 becomes a voltage value B lower than the voltage value A described above, and this voltage is applied as a bias for the driving transistor Q. As a result, the drive transistor Q enters the second ON state, and outputs a modulated wave signal d in which the amplitude voltage of the inverted carrier signal from the driver circuit DRV is reduced by a predetermined voltage to the matching circuit 14 side.

As described above, when the switching signal b is at the "H" level, the bias voltage e to the driving transistor Q is changed in accordance with the "H" level and the "L" level of the transmission code a, whereby the driving transistor Q can output a modulated signal that shifts the amplitude of the carrier signal c to a modulation factor of 10% according to the values “1” and “0” of the transmission code a.
That is, the modulation circuit 12 operates as a type B modulation circuit when the switching signal b is at the “H” level.

When outputting a switching signal b of either “H” or “L” level to the modulation circuit 12, the control section 11 outputs the switching signal b in accordance with an instruction of a not-shown switch. That is, when the changeover switch is instructing to output a modulation signal having a modulation factor of 10%, the modulation circuit 12 outputs “H”.
A switching signal of a level is output, and when the switching switch is instructing to output a modulation signal of a modulation factor of 100%, a switching signal of an “L” level is output to the modulation circuit 12.

The control section 11 can automatically output a switching signal b of either “H” or “L” to the modulation circuit 12. That is, first, an “H” level switching signal b is output to the modulation circuit 12 to
%, And when communication by this is not possible, an "L" level switching signal b is output to the modulation circuit 12 to communicate with a modulation signal having a modulation factor of 100%. Conversely, first, an "L" level switching signal b is output to the modulation circuit 12 to make it communicate with a modulation signal having a modulation factor of 100%. The level switching signal b is output and communication is performed using a modulation signal having a modulation factor of 10%.

FIGS. 2A to 2E are time charts showing operation waveforms of each part of the modulation circuit 12 when the switching signal b shown in FIG. 1 is at "L" level. (J)
Is the modulation circuit 1 when the switching signal b is at "H" level.
3 is a time chart showing operation waveforms of respective units of FIG. FIG.
The operation of the main part of the modulation circuit 12 will be described in more detail with reference to the block diagram of FIG.

First, the block diagram of FIG. 1 and FIGS.
The situation where the modulation circuit 12 operates as a type A modulation circuit will be described with reference to the waveform diagram of FIG. Here, FIG. 2A is a waveform of a carrier signal c having a predetermined frequency output from the oscillator 40, FIG. 2B is a waveform of a transmission code a output from the control unit 11, and FIG. 2D shows the output waveform of the circuit DRV, FIG. 2D shows the bias voltage waveform of the bias unit 12A, and FIG. 2E shows the waveform of the modulated wave signal d.

The carrier signal c shown in FIG. 2A is output to the input side of the driver circuit DRV. Here, when performing type A modulation, the switching signal b is set to the “L” level as described above, and therefore, in the modulation circuit 12 in FIG. 1, the transmission code a in FIG. Since the "H" level signal is output to the driver circuit DRV when the level is at the level, the driver circuit DRV converts the carrier signal c to the signal shown in FIG.
The signal is inverted and output to the driving transistor Q as shown in FIG.

At this time, the bias unit 12A is
(A) The divided voltage + V divided by the value of the combined resistance of the resistors R1 and R2 connected in parallel and the value of the resistor R3 as shown in FIG.
(Ie, the voltage value A) is generated and applied to the drive transistor Q as the bias voltage e shown in FIG. 2D, so that the drive transistor Q turns on and the driver circuit DR
FIG. 2 having the same amplitude as the amplitude of the inverted carrier signal from V
The modulated wave signal d shown in (e) is output to the matching circuit 14 side.

In the modulation circuit 12, the switching signal b is at the "L" level, and the transmission code a in FIG.
When the signal is at the level, an "L" level signal is output from the OR circuit OR to the driver circuit DRV, so that the output of the driver circuit DRV maintains the "H" level as shown in FIG. At this time, in the bias section 12A, since each resistance end becomes 0V (ground level), a bias voltage e of 0V shown in FIG. 2D is applied to the gate of the driving transistor Q. As a result, the drive transistor Q does not turn on, and therefore outputs a high impedance signal as shown in FIG. 2E to the matching circuit 14 as a modulated wave signal d.

Therefore, when the switching signal b shown in FIG. 1 is at the "L" level and the transmission code a is at the "H" level, an inverted signal of the carrier signal c is output as the modulated wave signal d, and the transmission code a becomes " When the signal is at the “L” level, a high impedance signal is output as the modulated wave signal d. That is, when the switching signal b is at the “L” level, the modulation circuit 12 controls the amplitude of the carrier signal c when the value of the transmission code a is “1” and the amplitude of the carrier signal c when the value of the transmission code a is “0”. This is a type A modulation circuit in which the amplitude of the carrier signal c is shifted by 100%.

Next, the block diagram of FIG. 1 and FIGS.
The situation where the modulation circuit 12 operates as a type B modulation circuit according to the waveform diagram of (j) will be described. Here, FIG. 2F shows the waveform of the carrier signal c, FIG. 2G shows the waveform of the transmission code a, FIG. 2H shows the output waveform of the driver circuit DRV, and FIG. FIG. 2 (j) shows the waveform of the bias voltage waveform, and FIG. 2 (j) shows the waveform of the modulated wave signal d.

When the switching signal b shown in FIG. 1 is at "H" level,
When the transmission code a in FIG. 2G is also at the “H” level,
Since these "H" level signals are output to the driver circuit DRV via the OR circuit OR, the driver circuit DRV
V outputs an inverted signal of the carrier signal c shown in FIG. The bias unit 12A is configured as shown in FIG.
The same voltage + V as the voltage value A shown in (i) is generated as the bias voltage e of the driving transistor Q and applied to the gate of the driving transistor Q. As a result, the drive transistor Q is turned on, and the modulated wave signal d shown in FIG. 2 (j) having the same amplitude as the amplitude of the inverted carrier signal from the driver circuit DRV.
Is output to the matching circuit 14 side.

On the other hand, when the switching signal b is at the “H” level and the transmission code a in FIG. 2G is at the “L” level, the switching circuit b at the “H” level is output to the driver circuit DRV. Therefore, the driver circuit DRV outputs an inverted signal of the carrier signal c shown in FIG. At this time, as shown in FIG. 3B, the bias unit 12A applies a divided voltage (ie, the voltage value A) divided by the value of the combined resistance of the resistors R2 and R3 connected in parallel and the value of the resistor R1. A voltage value B) lower by ΔV is generated, and the bias voltage e is applied to the driving transistor Q as a bias voltage e shown in FIG. As a result, the drive transistor Q outputs the modulated wave signal d shown in FIG. 2J in which the amplitude voltage of the inverted carrier signal from the driver circuit DRV is reduced by the predetermined voltage ΔV to the matching circuit 14 side.

Here, on the drive transistor Q side, the amplitude voltage of the carrier signal c when the transmission code a is “L” level is 81 compared to the amplitude voltage of the carrier signal c when the transmission code a is “H” level. Bias unit 1 so as to be .8%.
By selecting each resistance value of 2A and generating the bias voltage e to the driving transistor Q, the driving transistor Q increases the amplitude of the carrier signal c by 100 in accordance with the “H” level and the “L” level of the transmission code a. From 8% to 81.8%
The modulation circuit 12 can output the modulation wave signal d shifted by%, so that the modulation circuit 12 functions as a type B modulation circuit.

In this embodiment, the degree of modulation is 100%
Although the modulation circuit that combines the above-mentioned modulation and the modulation with the modulation factor of 10% has been described, a modulation signal having a modulation factor other than the above can be generated by changing the bias voltage of the driving transistor Q as necessary. . In addition, the modulation degree 1
In addition to the modulation signal having a modulation factor of 00% and the modulation signal having a modulation factor of 10%, it is possible to cope with three or more different modulation schemes by newly generating a modulation signal having a modulation factor different from the above. Further, in this embodiment, an example in which the modulation circuit is applied to an IC card reader has been described, but the invention can be similarly applied to all devices having the modulation circuit.

[0041]

As described above, according to the present invention, in a modulation circuit for shifting the amplitude voltage of a carrier signal according to the value of a binary signal and outputting an amplitude shift keying signal, the carrier signal and the binary signal A first switching signal for inputting a signal and instructing the output of a first amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by a first voltage, and changing the amplitude voltage of the carrier signal to a first voltage A driver circuit for selectively inputting a second switching signal for instructing the output of a second amplitude shift keying signal for shifting by a smaller second voltage, and a driver circuit connected to an output side of the driver circuit, A driving transistor for inputting the output carrier signal; and control means for controlling the driving transistor, wherein the control means responds to the value of the binary signal when the driver circuit is inputting the first switching signal. The driving transistor is controlled to a first ON state and an OFF state to output a first amplitude shift keying signal, and when the driver circuit is receiving a second switching signal, according to the value of the binary signal. Since the drive transistor is controlled to the first ON state and the second ON state to output the second amplitude shift keying signal, if the present modulation circuit is mounted on a non-contact IC card reader, different amplitudes will be obtained. Data can be read / written by outputting an accurate amplitude shift keying signal to each IC card accessible by the shift keying signal.

Further, the control means is connected to the first input terminal by the first input terminal.
And one of the second switching signal and
A logical sum circuit for inputting a binary signal to the second input terminal and outputting a logical sum of the input switching signal and the binary signal to the driver circuit via the output terminal; And a bias section comprising a third resistor. When the driver circuit is inputting the first switching signal, the bias section supplies a third potential corresponding to the value of the binary signal to the gate of the drive transistor. A ground potential is applied to control the driving transistor in the first ON state and the OFF state, and when the driver circuit is inputting the second switching signal, a second signal corresponding to the value of the binary signal is supplied to the gate of the driving transistor. Since the driving transistor is controlled to the first ON state and the second ON state by applying the third potential and the fourth potential lower than the third potential, the amplitude can be more accurately adjusted with a simple and economical configuration. Deviation It is possible to output a tone signal.
In addition, since one of the first and second switching signals is automatically output to the driver circuit, the modulation circuit automatically outputs an accurate amplitude shift modulation signal suitable for each IC card. Can output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a modulation circuit according to the present invention.

FIG. 2 is an operation waveform diagram of each section of the modulation circuit.

FIG. 3 is a diagram showing an equivalent circuit of a bias unit in the modulation circuit.

FIG. 4 is a block diagram of a non-contact IC card reader / writer to which the modulation circuit is applied.

FIG. 5 is a block diagram of an IC card in which data is read / written by a non-contact IC card reader / writer.

FIG. 6 is an explanatory diagram of amplitude shift keying.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1: Non-contact IC card reader, 2: Upper device, 3: IC
Card, 11 control unit, 12 modulation circuit, 12A bias unit, 12B control means, 13 demodulation circuit, 14 matching circuit, 15 resonance circuit, 31 wireless interface,
32: control circuit, 33: memory, 40: oscillator, OR ...
OR circuit, DRV driver circuit, Q driving transistor, Q1, Q2 transistor, C1 capacitor element, L
1, L2 ... antenna coil.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Ichiko Okitsu 2-3-2 Shimomeguro, Meguro-ku, Tokyo F-term in Tamura Electric Co., Ltd. (Reference) 5B058 CA17 5K004 AA03 DA08 DD05

Claims (3)

[Claims] 1. A modulation circuit for outputting an amplitude shift keying signal by shifting an amplitude voltage of a carrier signal according to a value of a binary signal, wherein the carrier signal and the binary signal are input and at least the A first instruction for outputting a first amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by a first voltage
And a second switching signal instructing to output a second amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by a second voltage smaller than the first voltage. A driver circuit that is connected to an output side of the driver circuit and inputs a signal including the carrier signal output from the driver circuit; and a control unit that controls the drive transistor. At least when the driver circuit is inputting a first switching signal, the driving transistor is controlled to a first on state and an off state in accordance with the value of the binary signal, and the first amplitude shift keying is performed. And when the driver circuit is inputting the second switching signal, the driving transistors are respectively turned on in the first ON state according to the value of the binary signal. When the modulation circuit, characterized in that for outputting a second control in the on state and the second amplitude-shift keying signal for generating a voltage less than the output voltage during the first ON state. 2. The control device according to claim 1, wherein the control unit inputs one of the first and second switching signals to a first input terminal and inputs a binary signal to a second input terminal. An OR circuit that outputs the logical sum of the input switching signal and the binary signal to the driver circuit via an output terminal, a first resistor having one end connected to the output terminal of the OR circuit, A second terminal connected to the other end of the first resistor and the other end connected to a second input terminal of the OR circuit;
And a third resistor having one end connected to the ground and the other end connected to the connection point of the first and second resistors, and the potential at the connection point is applied to the gate of the drive transistor by a bias voltage. A bias unit that applies a first switching signal to the gate of the driving transistor when the driver circuit is inputting a first switching signal, and a third potential and a ground corresponding to the value of the binary signal. A potential is applied to control the drive transistor in the first on state and the off state, and when the driver circuit is receiving a second switching signal, the gate of the drive transistor is controlled according to the value of the binary signal. Applying the third potential and a fourth potential lower than the third potential to control the drive transistor to the first ON state and the second ON state. Tuning circuit. 3. The modulation circuit according to claim 1, further comprising a switching signal output unit that automatically outputs one of the first and second switching signals to the driver circuit.