JP3480394B2 - Modulation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation circuit that modulates the amplitude of a carrier signal according to an input signal.

[0002]

2. Description of the Related Art A modulation circuit of this kind shifts the amplitude of a carrier signal in accordance with binary information of an input signal. Such amplitude shift keying modulation is performed by ASK (amplit).
Udeshift keying), which is a type A modulation for shifting the amplitude of the carrier signal to a modulation degree of 100% according to "1" or "0" indicating binary information of the input signal and the value of the input signal " There is a type B modulation in which the amplitude of the carrier signal is shifted to a modulation degree of 10% according to "1" or "0".

FIG. 5 is a waveform diagram for explaining the principle of amplitude shift keying. The modulation factor of the amplitude shift keying modulation can be expressed as: modulation factor = {(x−y) / (x + y)} × 100 (%). Note that x is an input signal 2
For example, the amplitude voltage of the carrier signal when the value of the value signal is "1" is shown, and the y is the amplitude voltage of the carrier signal when the value of the binary signal is "0".

Here, when the carrier signal amplitude voltage y when the value of the binary signal is "0" is set to 0V with respect to the carrier signal amplitude voltage x when the value of the binary signal is "1", the modulation factor is obtained from the above equation. = {(X-0) / (x + 0)} * 100 = 100
(%), And as shown in FIG. 5B, a type A modulation signal that shifts the amplitude of the carrier signal to a modulation degree of 100% is generated. Further, the ratios of the carrier signal amplitude voltages x and y when the binary signal values are “1” and “0” are 100 and 8 respectively.
Assuming 1.8, the modulation factor = {(100-81.8) / (100 + 81.8)} × 100≈
10 (%), and as shown in FIG. 5 (c), a type-B modulated signal that shifts the amplitude of the carrier signal to a modulation factor of 10% is generated.

Among the above type A and type B modulation circuits, the type A modulation circuit that shifts the amplitude of the carrier signal to a modulation degree of 100% according to the input signal values "1" and "0" is , A non-contact IC card reader / writer for reading / writing data from / to an IC card. The non-contact IC card reader / writer writes data to the IC card and reads data from the IC card by transmitting the modulated signal of the modulation circuit to the IC card as a radio signal.

[0006]

In recent years, the amplitude of a carrier signal is adjusted to a modulation factor of 1 according to the values "1" and "0" of the input signal.
A type B modulation circuit that shifts to 0% is mounted on a non-contact IC card reader / writer, and the modulation signal of this type B modulation circuit is transmitted to the IC card to read / write data from / to the IC card. Is being considered. However, an IC card reader / writer equipped with such a type B modulation circuit cannot access the type A modulated signal IC cards already on the market. Therefore, the IC card reader / writer is capable of accessing both the IC card accessed by the type A amplitude shift keying signal and the IC card accessed by the type B amplitude shift keying signal. There is a desire to arrange.

Therefore, it is an object of the present invention to output an optimum amplitude shift keying signal to each IC card which can be accessed by different amplitude shift keying signals to enable access.

[0008]

In order to solve such a problem, the present invention provides a modulation circuit for shifting the amplitude voltage of a carrier signal according to the value of a binary signal and outputting the amplitude-shift modulation signal. A first signal for inputting a carrier signal and a binary signal and for instructing the output of a first amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by the first voltage
And the second switching signal for instructing the output of the second amplitude shift keying signal that shifts the amplitude voltage of the carrier signal by the second voltage smaller than the first voltage. Drive means, a first power supply section for generating a third voltage,
A second power supply section for generating a fourth voltage smaller than the third voltage, and a first power supply section arranged between the first power supply section and the driving means.
The switching means, the second switching means arranged between the second power supply section and the driving means, and the control means. The controlling means receives the first switching signal from the driving means. When the first switching means is operated, the first switching means is operated.
The third voltage of the power supply section is applied to the drive means as the power supply voltage to output the first amplitude shift keying signal, and when the drive means inputs the second switching signal, the first and second Of the switching means, the switching means corresponding to the value of the binary signal is operated, and the voltage from the power source is applied to the driving means through the operating switching means to output the second amplitude shift keying signal. It is characterized by having done.

In this case, the control means receives the binary signal at one of the input terminals and the first signal at the other input terminal.
Alternatively, when one of the second switching signals is input and the second switching means connected to the output terminal controls the operation / non-operation, and the first switching signal is input, the switching signal is inverted. A first inverter circuit that outputs the second switching signal to the logical sum circuit and outputs the second switching signal to the logical sum circuit as a first switching signal when the second switching signal is input. And a second inverter circuit for inverting and outputting the output signal of the logical sum circuit and controlling the operation / non-operation of the first switching means connected to the output terminal. Further, when the driving means inputs the first switching signal, the driving means outputs / non-outputs the carrier signal according to the value of the binary signal and outputs the carrier signal as the first amplitude shift keying signal. Further, the drive means is provided with a switching signal output means for automatically outputting one of the first and second switching signals.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a non-contact IC card reader / writer to which the modulation circuit according to the present invention is applied. In FIG. 3, a non-contact IC card reader / writer (hereinafter referred to as an IC card reader) 1 controls a control unit 11 that controls the entire IC card reader 1 and a carrier signal described later into a data signal output from the control unit 11. A modulation circuit 12 that modulates in accordance with the demodulation circuit 13, a matching circuit 1
4, a resonance circuit 15, and a power supply unit 16 that supplies power to the above units.

Here, the matching circuit 14 inputs the output signal from the modulation circuit 12 and outputs it to the resonance circuit 15, and this output signal is efficiently supplied from the resonance circuit 15 as described later.
The impedance is matched with the resonance circuit 15 so that the impedance can be transmitted to the C card. The resonance circuit 15 is
The antenna coil L1 which is an inductive element and the capacitive element C1 are connected in parallel, and when a modulation signal is applied from the modulation circuit 12 via the matching circuit 14, resonance is started and a radio wave signal is generated from the antenna coil L1. It is transmitted as a radio signal to an IC card electromagnetically coupled to the coil L1. When the demodulation circuit 13 receives a modulation signal sent from the IC card in response to the transmission of the radio signal, the demodulation circuit 13 demodulates the modulation signal, extracts data, and outputs the data to the control unit 11. .

The control unit 11 in the IC card reader 1 is connected to the host device 2 via a serial I / F (serial interface). The control unit 11 performs data communication with the higher-level device 2 via the serial I / F to record the received data from the higher-level device 2 in the IC card and transmits the data read from the IC card to the higher-level device 2. To do.

FIG. 4 is a block diagram showing the configuration of the IC card electromagnetically coupled to the IC card reader 1. Figure 4
In, the IC card 3 has an antenna coil L2, a wireless interface 31, a control circuit 32, and a memory 33 in which an ID and information unique to the IC card are stored.

Radio interface 31 of IC card 3
When the antenna coil L1 of the IC card reader 1 and the antenna coil L2 of the IC card 3 are electromagnetically coupled,
Electric power POWER is generated by the radio wave signal from the card reader 1 and supplied to the control circuit 32 and the memory 33, and a clock signal CLK is generated and supplied to the control circuit 32.
In addition, the data DATA is extracted from the radio signal to control circuit 3
2 is output. Control circuit 32 of IC card 3
When the power POWER is supplied from the wireless interface 31, the data DATA is read from the wireless interface 31 in synchronization with the clock signal CLK. If this data DATA is write data to the memory 33, the memory 33
On the other hand, when the data DATA is command data for reading the data in the memory 33, the data in the memory 33 is read and output to the wireless interface 31.

The operation of the IC card reader 1 and the IC card 3 will be described with reference to FIGS. 3 and 4. IC card reader 1
Generates a carrier signal having a predetermined frequency from an oscillator 40, which will be described later, provided in the modulation circuit 12 and transmits the carrier signal as a radio signal via the matching circuit 14 and the resonance circuit 15. Here, when the IC card 3 is placed in a predetermined place of the IC card reader 1, the antenna coils L2 and I of the IC card 3
The antenna coil L1 of the C card reader 1 is electromagnetically coupled, and the IC card 3 is supplied with electric power POWER by the radio signal of the IC card reader 1 as described above.

The control unit 11 of the IC card reader 1 transfers the data from the host device 2 to the IC card 3 to the serial I / O.
When received via F, this data is output to the modulation circuit 12. Upon receiving the data from the control unit 11, the modulation circuit 12 performs amplitude shift keying modulation on the carrier signal according to the input data value, and transmits the carrier signal as a radio signal via the matching circuit 14 and the resonance circuit 15.

When the radio interface 31 of the IC card 3 receives the radio wave signal from the IC card reader 1 via the antenna coil L2, the data DATA is extracted from the radio wave signal as described above, and is sent to the control circuit 32. Output. Here, when the received data DATA from the IC card reader 1 is the write data for the memory 33, the control circuit 32 records it in the memory 33. In addition, the data DATA
When is the command data for reading the data in the memory 33, the data in the memory 33 is sequentially read in synchronization with the above-mentioned clock signal CLK and is output to the wireless interface 31 side.

The data sequentially read from the memory 33 of the IC card 3 is transmitted as a radio signal to the IC card reader 1 side via the wireless interface 31 and the antenna coil L2. Resonant circuit 15 of IC card reader 1
When receiving the radio wave signal from the IC card 3, outputs the radio wave signal to the demodulation circuit 13 as a modulation signal. The demodulation circuit 13 demodulates the modulated signal to extract data from the modulated signal, and outputs the extracted data in the memory 33 of the IC card 3 to the control unit 11. Control unit 11
When receiving the data from the demodulation circuit 13, transmits the data to the higher-level device 2. In this way, the IC card reader 1 can write data in the IC card 3 and read the data written in the IC card 3.

FIG. 1 is a block diagram showing the configuration of a modulation circuit according to the present invention. This modulation circuit is an IC card reader 1
It is used as a modulator circuit. As shown in FIG. 1, the modulation circuit 12 includes an oscillator 40 that generates the above-described carrier signal c having a predetermined frequency, power supply units 41 and 42, OR circuits OR1 and OR2, and inverter circuits INV1 and INV.
2, driver circuit DRV, and transistors Q1 and Q2
Consists of. Here, the OR circuit OR2 and the driver circuit D
The driving means 12A is constituted by the RV and the OR circuit OR.
1 and the inverter circuits INV1 and INV2 form the control means 12B.

The modulation circuit 12 shifts the amplitude of the carrier signal according to the binary information of the input signal. The modulation circuit 12 changes the amplitude of the carrier signal according to the data values "1" and "0". This enables the type A modulation in which the carrier signal amplitude is shifted to 10% and the type B modulation in which the amplitude of the carrier signal is shifted to a modulation degree of 10% according to the data values "1" and "0".

The operation of the modulation circuit 12 will be described with reference to FIG. In FIG. 1, the carrier signal c of the oscillator 40 is output to one input terminal of the driver circuit DRV. Also,
Data value "1" or data value "0" from the control unit 11
The transmission code a is output to one input terminal of the OR circuit OR1, and the switching signal b from the control unit 11 is inverted by the inverter circuit INV1 and output to the other input terminal of the OR circuit OR1.

When the switching signal b is at "L" level, the switching signal b is inverted by the inverter circuit INV1 and given to the other input terminal of the OR circuit OR1 as a signal at "H" level. Therefore, the level of the transmission code a input to one input terminal of the OR circuit OR1 is "H",
At any level of “L” (data value “1”,
In either case of "0"), the output of the OR circuit OR1 becomes "H" level, and the transistor Q2 connected to the output terminal of the OR circuit OR1 is turned off. Also, the OR circuit O
The output of R1 is inverted by the inverter circuit INV2 and output to the transistor Q1.
Turns on. As a result, the + 5V voltage of the power supply unit 41 is always applied as the power supply voltage VDD of the driver circuit DRV via the transistor Q1.

On the other hand, when the switching signal b is "L" level,
The "L" level switching signal b is output to one input terminal of the OR circuit OR2, and the transmission code a is output to the other input terminal of the OR circuit OR2. Therefore, the OR circuit OR2 outputs the transmission code a. According to the "H" level and the "L" level of, the "H" level and the "L" level signals are output,
It is applied to the other input terminal of the driver circuit DRV. As a result, the driver circuit DRV causes the value “1” of the transmission code a,
According to "0" (that is, "H" level and "L" level of the transmission code a), the output amplitude of the carrier signal c is set to 100.
Output the modulation signal that shifts to%. That is, the modulation circuit 1
2 is type A when the switching signal b is at the “L” level.
Operates as a modulation circuit of.

Next, when the switching signal b is at the "H" level, the switching signal b at the "H" level is output to one input terminal of the OR circuit OR2, and the transmission code a is the other of the OR circuit OR2. Since it is output to the input terminal of the OR circuit OR2, the OR circuit OR2 constantly outputs the signal of the "H" level regardless of the "H" level and the "L" level of the transmission code a.
It outputs to the other input terminal of RV. Driver circuit D
Since the carrier signal c is output to one input terminal of the RV as described above, the driver circuit DRV can always output the inverted signal of the carrier signal c.

On the other hand, the "H" level switching signal b is inverted by the inverter circuit INV1 and given to the other input terminal of the OR circuit OR1 as an "L" level signal.
Therefore, the OR circuit OR1 outputs signals of "H" level and "L" level according to the "H" level and "L" level of the transmission code a of one input terminal, respectively. Thus, when the transmission code a is at "H" level, the transistor Q2 is turned off by the "H" level signal output from the OR circuit OR1 and the transistor connected to the inverter circuit INV2 for inverting the output of the OR circuit OR1. Q1 turns on. As a result, the + 5V voltage of the power supply unit 41 is applied as the power supply voltage VDD of the driver circuit DRV via the transistor Q1. Further, when the transmission code a is at "L" level, the transistor Q2 is turned on by the "L" level signal output from the OR circuit OR1,
And an inverter circuit I for inverting the output of the OR circuit OR1
The transistor Q1 connected to NV2 is turned off. As a result, the + 4.1V voltage of the power supply unit 42 is applied as the power supply voltage VDD of the driver circuit DRV via the transistor Q2.

Thus, when the switching signal b is at "H" level, the power supply voltage VDD of the driver circuit DRV fluctuates to + 5V and + 4.1V according to the "H" level and "L" level of the transmission code a. The driver circuit DR
V can output a modulation signal that shifts the output amplitude of the carrier signal c to a modulation degree of 10% according to the values "1" and "0" of the transmission code a. That is, the modulation circuit 12 operates as a type B modulation circuit when the switching signal b is at the “H” level.

When the control section 11 outputs the switching signal b of either "H" or "L" level to the modulation circuit 12, the control section 11 outputs it in accordance with an instruction from a switching switch (not shown). That is, when the changeover switch directs the output of the modulation signal having the modulation degree of 10%, the modulation circuit 12 outputs "H".
A level changeover signal is output, and when the changeover switch instructs to output a modulation signal with a modulation degree of 100%, an "L" level changeover signal is output to the modulation circuit 12.

The control section 11 can also automatically output a switching signal b of either "H" or "L" level to the modulation circuit 12. That is, first, the switching signal b of “H” level is output to the modulation circuit 12 to obtain the modulation degree 10
% Modulation signal, and if the communication by this is impossible, the switching signal b of “L” level is output to the modulation circuit 12 to communicate with the modulation signal of 100% modulation degree. On the contrary, first, the switching signal b of the “L” level is output to the modulation circuit 12 so that the modulation circuit 100 communicates with the modulation signal having the modulation degree of 100%. A level switching signal b is output and communication is performed with a modulation signal having a modulation degree of 10%.

2A to 2D are time charts showing the timings of the operation waveforms of the respective parts of the modulation circuit 12 when the switching signal b shown in FIG. 1 is at the "L" level.
(E) to (h) are time charts showing the timings of the operation waveforms of the respective parts of the modulation circuit 12 when the switching signal b is at the “H” level. The operation of the main part of the modulation circuit 12 will be described in more detail with reference to the block diagram of FIG. 1 and the time chart of FIG.

First, the block diagram of FIG. 1 and FIGS.
A situation in which the modulation circuit 12 operates as a type A modulation circuit will be described with reference to the waveform diagram of FIG. Here, FIG. 2A is a waveform of the carrier signal c having a predetermined frequency output from the oscillator 40, FIG. 2B is a waveform of the transmission code a output from the control unit 11, and FIG. 2C is a driver. The waveform of the power supply voltage VDD of the circuit DRV and FIG. 2D show the waveform of the modulated wave signal d.

The carrier signal c shown in FIG. 2A is output to the driver circuit DRV. Here, when the type A modulation is performed, the switching signal b is set to the “L” level as described above, so that in the modulation circuit 12 of FIG. 1, the transistor Q1 is turned on and the power supply section 41 of FIG. The + 5V voltage shown in c) is constantly supplied as the power supply voltage VDD of the driver circuit DRV.

Here, when the transmission code shown in FIG. 2B is at the "H" level (data value "1"), the "H"
The level signal passes through the OR circuit OR2 and the driver circuit DR
Since it is output to V, the driver circuit DRV is shown in FIG.
The inverted signal of the carrier signal c is output as shown in FIG. A signal obtained by inverting the carrier signal c becomes a modulated wave signal d and is provided to the matching circuit 14.

The transmission code shown in FIG. 2B is "L".
In the case of the level (data value “0”), the “L” level signal is output to the driver circuit DRV via the OR circuit OR2, so that the driver circuit DRV receives the carrier signal c from the oscillator 40. The carrier signal c is not output, but the "H" level signal is output as shown in FIG. This “H” level signal becomes the modulated wave signal d and is applied to the matching circuit 14.

Therefore, when the switching signal b shown in FIG. 1 is at the "L" level, the inverted signal of the carrier signal c is output as the modulated wave signal d when the transmission code a is at the "H" level, and the transmission code a is " At the L level, the "H" level signal is output as the modulated wave signal d. That is, when the value of the transmission code a is "1", the amplitude of the carrier signal c shifts by 100%, and when the value of the transmission code a is "0", the amplitude of the carrier signal c does not shift. 1
2 is a type A that shifts the amplitude of the carrier signal c from 100% to 0% according to the values "1" and "0" of the transmission code a.
Will function as a modulation circuit of.

Next, the block diagram of FIG. 1 and FIGS.
A situation in which the modulation circuit 12 operates as a type B modulation circuit will be described with reference to the waveform diagram of (h). Here, FIG. 2 (e) is the waveform of the carrier signal c, FIG. 2 (f) is the waveform of the transmission code a, FIG. 2 (g) is the waveform of the power supply voltage VDD of the driver circuit DRV, and FIG. 2 (h) is the modulation. The waveforms of the wave signal d are shown respectively.

When the switching signal b shown in FIG. 1 is at the "H" level, the switching signal b at the "H" level is output to the driver circuit DRV via the OR circuit OR2. "H" of transmission code b shown in 2 (f)
The carrier signal c from the oscillator 40 is inverted and output as shown in FIG. 2 (h) regardless of the level and the "L" level.

On the other hand, since the OR circuit OR1 shown in FIG. 1 outputs the switching signal b of "L" level inverted by the inverter circuit INV1, the OR circuit OR1 outputs "H" level of the transmission code a, "H" depending on "L" level
The level and "L" level signals are output. As a result, the transistor Q1 is turned on and off according to the "H" level and "L" level of the transmission code a, and the transistor Q2 is turned off according to the "H" level and "L" level of the transmission code a.
Turn on. As a result, when the transmission code a is at the “H” level, the + 5V voltage of the power supply unit 41 is applied to the transistor Q1.
Is applied as the power supply voltage VDD of the driver circuit DRV via the transistor Q2. When the transmission code a is at the "L" level, a voltage of about +4.1 V of the power supply unit 42 is applied as the power supply voltage VDD of the driver circuit DRV via the transistor Q2. It

That is, as shown in FIGS. 2 (f) and 2 (g), the power supply voltage VDD of the driver circuit DRV changes from 5V to 4. depending on the "H" level and "L" level of the transmission code a. It fluctuates to 1V, and this fluctuation potential difference ΔV becomes 0.9V. Therefore, the driver circuit DRV has the transmission code a.
Carrier signal c depending on the "H" level and "L" level of
The modulated wave signal d shown in FIG. 2 (h) whose amplitude voltage is shifted by ΔV is output to the matching circuit 14. Here, with respect to the amplitude voltage of the carrier signal c when the transmission code a is “H” level, the carrier signal c when the transmission code a is “L” level
So that the amplitude voltage of the driver circuit DR becomes 81.8%
If the power supply voltage VDD of V is changed, the amplitude of the carrier signal c is shifted from 100% to 81.8% by 18.2% in accordance with the “H” level and the “L” level of the transmission code a. The modulated wave signal d to be output can be output, and thus the modulation circuit 12 functions as a type B modulation circuit. In this embodiment, the driver circuit DR
When each voltage of the power supply units 41 and 42 is applied to V, it is applied using the transistors Q1 and Q2, respectively, but it may be applied using other switching means such as an analog switch. .

In this embodiment, the modulation degree is 100%.
Although the modulation circuit that combines both the modulation of 10% and the modulation of 10% has been described, a modulation signal having a modulation degree other than the above can be generated by changing the power supply voltage of the driver circuit DRV as necessary. . Also, the modulation factor is 100
% Modulation signal and a modulation signal with a modulation degree of 10%, a modulation signal with a modulation degree different from the above is newly generated.
It is also possible to support three or more different modulation schemes. In addition, although an example in which the modulation circuit is applied to the IC card reader has been described in the present embodiment, the present invention can be similarly applied to all devices having the modulation circuit.

[0040]

As described above, according to the present invention, in the modulation circuit that shifts the amplitude voltage of the carrier signal according to the value of the binary signal and outputs it as the amplitude shift modulation signal, the carrier signal and the binary signal are output. A first switching signal for inputting a signal and for instructing the output of a first amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by the first voltage; and the amplitude voltage of the carrier signal as the first voltage. Driving means for selectively inputting a second switching signal for instructing the output of a second amplitude shift keying signal that shifts by a smaller second voltage, and a first power supply for generating a third voltage. Section, a second power source section for generating a fourth voltage smaller than the third voltage, a first switching means arranged between the first power source section and the driving means, and a second power source. Second switching means disposed between the drive section and the drive section And control means, the control means,
When the driving means inputs the first switching signal, the first switching means is operated to apply the third voltage of the first power supply section as the power supply voltage to the driving means to perform the first amplitude shift keying modulation. In addition to outputting the signal, when the driving means inputs the second switching signal, the switching means corresponding to the value of the binary signal is operated among the first and second switching means to switch the operating switching means. Since the voltage from the corresponding power source section is applied to the driving means via the above to output the second amplitude shift keying signal, if the present modulation circuit is mounted on the non-contact IC card reader, different amplitude shift keying modulations are performed. Data can be read / written by outputting an accurate amplitude shift keying signal to each IC card that can be accessed by a signal.

Further, the control means has a first input terminal to which the binary signal is input, the other input terminal to which one of the first and second switching signals is input, and which is connected to the output terminal. An OR circuit for controlling the operation / non-operation of the second switching means, and when the first switching signal is input, the switching signal is inverted and output as a second switching signal to the OR circuit, and the second switching signal is also output. When a signal is input, a first inverter circuit that inverts the switching signal and outputs it as a first switching signal to a logical sum circuit, and an output signal of the logical sum circuit that is inverted and output and is connected to the output terminal Since it is composed of the second inverter circuit for controlling the operation / non-operation of the switching means, it is possible to output an accurate amplitude shift keying signal with a simple and economical structure. Further, when the driving means inputs the first switching signal, it outputs and does not output the carrier signal according to the value of the binary signal, and outputs the carrier signal as the first amplitude shift keying signal. An accurate 100% amplitude shift keying signal can be output. Further, since either one of the first and second switching signals is automatically output to the driving means, the modulation circuit automatically outputs an accurate amplitude shift modulation signal suitable for each IC card. Can be output.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a modulation circuit according to the present invention.

FIG. 2 is an operation waveform diagram of each part of the modulation circuit.

FIG. 3 is a block diagram of a non-contact IC card reader / writer to which the modulation circuit is applied.

FIG. 4 is a block diagram of an IC card in which data is read / written by a non-contact IC card reader / writer.

FIG. 5 is an explanatory diagram of amplitude shift keying.

[Explanation of symbols]

1 ... Non-contact IC card reader / writer, 2 ... Host device, 3
... IC card, 11 ... Control unit, 12 ... Modulation circuit, 12A
... Drive means, 12B ... Control means, 13 ... Demodulation circuit, 14
... matching circuit, 15 ... resonance circuit, 31 ... wireless interface, 32 ... control circuit, 33 ... memory, 40 ... oscillator, 4
1, 42 ... Power supply unit, OR1, OR2 ... OR circuit, I
NV1, INV2 ... Inverter circuit, DRV ... Driver circuit, Q1, Q2 ... Transistor, C1 ... Capacitance element, L
1, L2 ... Antenna coil.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-51361 (JP, A) Actual development Sho 59-81150 (JP, U) Actual development Sho 63-10646 (JP, U) (58) Field (Int.Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (4)

(57) [Claims] 1. A modulation circuit for outputting an amplitude shift keying signal by shifting an amplitude voltage of a carrier signal according to a value of a binary signal, wherein at least the carrier signal and the binary signal are input, A first instructing output of a first amplitude shift keying signal for shifting the amplitude voltage of the carrier signal by the first voltage
And a second switching signal for instructing the output of a second amplitude shift modulation signal that shifts the amplitude voltage of the carrier signal by a second voltage smaller than the first voltage. A first power supply section for generating a third voltage, a second power supply section for generating a fourth voltage smaller than the third voltage, and a first power supply section. At least the first switching means arranged between the driving means and the driving means, and at least the second switching means arranged between the second power source section and the driving means. Is inputting the first switching signal, the first switching means is operated to activate the first switching signal.
If the third voltage of the power supply section is applied to the drive means as the power supply voltage to output the first amplitude shift keying signal and the drive means inputs the second switching signal, the first and second Among the two switching means, the switching means corresponding to the value of the binary signal is operated to apply the voltage from the corresponding power source section to the driving means via the operating switching means, and the second amplitude shift keying signal is generated. A modulation circuit having control means for outputting 2. The control unit according to claim 1, wherein the binary signal is input to one of the input terminals,
One of the first and second switching signals is input to the other input terminal, and an OR circuit for controlling the operation / non-operation of the second switching means connected to the output terminal, and the first switching signal Is input, the switching signal is inverted and output to the OR circuit as the second switching signal, and when the second switching signal is input, the switching signal is inverted and the first switching signal is input to the OR circuit. Output as
And the second inverter circuit for inverting and outputting the output signal of the logical sum circuit and controlling the operation / non-operation of the first switching means connected to the output terminal. And a modulation circuit. 3. The drive unit according to claim 1, wherein when the first switching signal is input, the driving unit outputs or does not output the carrier signal according to a value of a binary signal. A modulation circuit which outputs as a modulation signal. 4. The modulation circuit according to claim 1, further comprising switching signal output means for automatically outputting one of the first and second switching signals to the driving means.