JP2001127727A - Connector for compressed data transmission - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit compresed data by the irreducibly minimum transmission facilities. SOLUTION: Pieces CH1 to CH4 of data inputted from input terminals 2A to 2D provided corresponding to input transmission lines A1 to A4 are put together into specific transmission units by composing means 6 and 20 and the composed data CHM are outputted from a single output terminal 4 to a single output transmission line B. Consequently, pieces of data inputted to this connector are converted into single data, which is transmitted to the output transmission line B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connector suitable for, for example, a data transmission line of a video system for business use.

[0002]

2. Description of the Related Art In recent years, a digital VTR format capable of covering various uses such as news gathering, editing, and transmission has been developed with a high image quality for a widespread era of video production and transmission. In such a format, SMPTE305M
And the like, and the data compressed by using a compression format standard such as that described above are serially transmitted.

[0003]

In the above-described data transmission path, even if data compressed by a compression format is transmitted in a composite form, a plurality of data are transmitted. One transmission path is set for transmission. For this reason, transmission efficiency cannot be said to be sufficiently high, for example, a transmission code needs to be installed for each transmission path.

Accordingly, an object of the present invention is to provide a transmission path for digital data that can be transmitted with a minimum necessary transmission facility by increasing transmission efficiency.

[0005]

According to the present invention, there is provided a connector provided on a transmission line for serially transmitting compressed data, comprising: an input terminal provided for each of a plurality of input transmission lines; Compound means for compounding a plurality of data input from the input terminal for each predetermined transmission unit;
The above-mentioned problem is solved by providing an output terminal for outputting the data compounded by the compounding means to a single output transmission line.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a connector provided on a transmission line for serially transmitting compressed data, the connector being provided for each of a plurality of input transmission lines. An input terminal, a compounding means for compounding a plurality of data input from the input terminal for each predetermined transmission unit, and an output for outputting the data compounded by the compounding means to a single output transmission line. It is characterized by having a terminal and thereby has the following operation. That is, a plurality of data input from input terminals provided corresponding to each of the plurality of input transmission paths are combined by the combining means for each predetermined transmission unit, and the combined data is combined into a single unit. Output terminal to a single output transmission line, a plurality of data are transmitted from this connector through a single output transmission line.

It is preferable that the present invention is provided on a transmission line for transmitting video data in a compressed state based on the SMPTE 305M standard. By using the transmission path, the present invention can be implemented without requiring any new equipment.

According to a third aspect of the present invention, there is provided a compressed data transmission connector according to the first or second aspect,
Serial / parallel conversion means for converting the data input from the input terminal into parallel data and outputting the parallel data to a composite means; and parallel / serial conversion means for converting the output of the composite means into a serial data and outputting it to an output terminal. Conversion means, and the composite means,
It is characterized in that data of each input transmission line input in a parallel state is compounded, thereby having the following operation. In other words, since serial data includes data depending on the data at the previous position, if multiple serial data are combined by the combining means, it may not be possible to connect well with the previous data when demodulating the combined data. There is. Therefore, in the present invention,
Since the serial data is converted into parallel data by the serial / parallel conversion means and then composited by the composite means, such inconvenience can be prevented.

According to a fourth aspect of the present invention, there is provided the compressed data transmission connector according to any one of the first to third aspects, wherein the input terminal is connected to a single main input transmission line. And a sub-input terminal provided corresponding to each of the plurality of sub-input transmission lines and receiving the sub-data from the corresponding sub-input transmission line. The means includes, for each of the sub-data input from the sub-input terminal, a write reset generation circuit for generating a write reset pulse based on the input timing, and an input timing of the main data input from the main input terminal. A read reset generating circuit for generating a read reset pulse corresponding to each of the sub input terminals based on the output timings of the sub input terminals, A memory circuit provided correspondingly to each of the memory cells and starts writing the sub data in synchronization with the corresponding write reset pulse, and starts reading the sub data in synchronization with the read reset pulse. And a data insertion circuit that inserts the sub-data read from the storage circuit into main data input from a main input terminal, thereby having the following operation. That is, the sub-data input from the sub-input terminal is written into the storage memory in response to a write reset pulse based on the input timing, and further from the storage circuit in response to a read reset pulse based on the main data input timing. After being read, the data is inserted into the main data by the data insertion circuit. At this time, the read reset pulses corresponding to the respective sub-data have their output timings shifted from each other, so that the sub-data is inserted into the main data without overlapping each other.

According to a fifth aspect of the present invention, there is provided the compressed data transmission connector according to the fourth aspect, wherein a phase comparison circuit for comparing the phase of each of the write pulse with the phase of the read pulse; Provided corresponding to each of the sub-input terminals, when the phases of both pulses match with a degree of coincidence equal to or greater than a predetermined value in the comparison result of the phase comparison circuit, the input from the sub-input terminal corresponding to the write pulse. A delay circuit for delaying the sub data and outputting the data to the storage circuit is further provided, thereby having the following operation. In other words, if the transmission phases of the main data and the sub-data are significantly different from each other, there is a large shift in the timing such that the write timing to the storage circuit overtakes the read timing. Such a shift in the read / write timing causes a disorder in the data order of the sub-data read into the data insertion circuit, so that a highly accurate insertion process cannot be performed. Therefore, in the present invention, the phase of each of the write pulse and the phase of the read pulse are compared by a phase comparison circuit, and if the phases of the two pulses match with a predetermined degree of coincidence in the comparison result, the main data It is determined that the transmission phases of the data and the sub data are significantly different from each other to such an extent that normal reading and writing cannot be performed by the storage circuit. The sub data determined as such (sub data having a transmission phase greatly shifted from the main data) is regarded as not being able to perform high-precision insertion processing, and the sub data is stored after being delayed by a delay circuit. Output to the circuit. This corrects the data order of the sub-data read by the data insertion unit, and maintains the accuracy of the insertion process.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a configuration of a connector according to an embodiment of the present invention, FIG. 2 is a perspective view showing a use form thereof, and FIG. 3 is a circuit configuration diagram thereof. .

The connector 1 is a connector provided on a serial transmission line for transmitting video data compressed according to the SMPTE 305M standard or the like. The input side of the connector 1 has a main input transmission line for transmitting main video data CH1. A1
Also, it is connected to sub-input transmission lines A2 to A4 through which a plurality of sub-video data (in the present embodiment, three types of sub-video data) CH2 to CH4 are transmitted. The output side of the connector 1 is connected to a single output transmission line B. Connector 1
Is configured to perform composite processing on main / sub-video data CH1 to CH4 input from the main input transmission line A1 and sub-input transmission lines A2 to A4, and then output the composite video data CHm to the output transmission line B. Have been.

The connector 1 has a plurality of input terminals 2A to 2D
, A circuit board 3, an output terminal 4, and a case 5. The input terminal 2A is provided corresponding to the main input transmission line A1. The input terminals 2B to 2D are
It is provided corresponding to each of 2 to A4. These input terminals 2A to 2D have terminal shapes connectable to connection terminals C1 to C4 provided at the ends of the corresponding input transmission paths A1 to A4. The circuit board 3 includes main video data CH1 and sub video data CH input from the input terminals 2A to 2D.
2 to CH4, and the video data CH2 to C
A signal processing circuit 6, which is a compound means for compounding H2, is mounted. The output terminal 4 outputs the composite video data CHm subjected to the composite processing in the signal processing circuit 6 to the output transmission line B. The output terminal 4 has a terminal shape connectable to a connection terminal D provided at an end of the output transmission line B. The case 5 houses the above-described components.

The signal processing circuit 6 includes serial decoders 7A to 7D as serial / parallel conversion circuits, FIFO memories 8A to 8C as storage circuits, a multiplexer 9 as a data insertion circuit, and write reset generation circuits 10A to 10C. And the read reset generation circuit 11
And a serial encoder 12 as a parallel / serial conversion circuit.

The serial decoders 7A to 7D are provided corresponding to the input terminals 2A to 2D, respectively.
The sub-picture data CH1 to CH4 are converted into parallel data CH1p.
~ CH4p.

The FIFO memories 8A to 8C are provided corresponding to the serial decoders 7B to 7D (sub-picture data CH2 to CH4 are processed in parallel), and are converted into parallel data by the serial decoders 7B to 7D. This is a memory circuit in which sub-picture data CH2p to CH4p are sequentially written and sequentially read.

The multiplexer 9 has a FIFO memory 8A.
-8C read out from sub-picture data CH2p-CH2
This is a circuit that inserts p into the main video data CH1p output from the serial decoder 7A to create composite video data CHmp.

Write reset generation circuits 10A to 10C
Are provided corresponding to the FIFO memories 8A to 8C, respectively, and each data group existing in the sub-picture data CH2p to CH4p output from the serial decoders 7B to 7D connected to the corresponding FIFO memories 8A to 8C. Are generated, the write reset pulses WP1 to WP3 having the same timing as the start position are generated. The generated write reset pulses WP1 to WP3 are generated.
Are supplied to the corresponding FIFO memories 8A to 8C. The above data group is a video data,
For example, a group of video data for one frame corresponds.

The read-reset generation circuit 11 outputs the FIFO memories 8A to 8C synchronized with the output timing of each data group (similar to the data group in the description of the write reset) of the main video data CH1p output from the serial decoder 7A. Read reset pulses RP1 to RP3 of the FIFO memory 8
A to 8C.

The read reset pulses RP1 to RP3 have different output timings. The pulse RP1 is stored in the FIFO memory 8A, and the pulse RP2 is output in the FIFO memory.
The pulse RP3 is supplied to the O memory 8B and the FIFO memory 8C, respectively.

The serial encoder 12 outputs the parallel composite video data CH output from the multiplexer 9.
mp is converted to composite video data CHm which is serial data and output to the output terminal 4.

Hereinafter, the operation of the connector 1 will be described with reference to the timing chart of FIG.

The main / sub input transmission lines A1 to A4 have SMP
Main / sub video data CH1 to CH4 compressed to 1 / n (n: natural number) according to a standard such as TE305M are transmitted. Here, as an example of the compression ratio, each video data is assumed to be compressed to 1/4, but it is needless to say that data compressed at other compression ratios may be used.

Each of the compressed video data CH1
As shown in FIG. 4, the data format of CH4 is a data form in which the data exists only in the data partial area FL1 from the beginning of the frame to the 1/4 time position in the data area FL for one frame. In the present embodiment, the data area FL for one frame corresponds to one predetermined transmission unit in the claims.

The main / sub-picture data CH1 to CH4 in such a data form are converted into parallel data CH1p to CH4p by a serial decoder, respectively.
The main video data CH1p is input to the multiplexer 9,
The sub-picture data CH2p to CH4p are input to the corresponding FIFO memories 8A to 8C, respectively. At this time, the main video data CH1p is supplied to the read reset generation circuit 11, and each of the sub video data CH2p to CH4p
Are the corresponding write reset generation circuits 10A to 10C
Supplied to

Write reset generation circuits 10A to 10C
Creates write reset pulses WP1 to WP3 that temporally coincide with the data head positions of the supplied sub-picture data CH2p to CH4p. Then, the write reset generation circuits 10A to 10C send the generated write reset pulses WP1 to WP3 to the corresponding FIFO memories 8A to 8C.
8C. When the write resets WP1 to WP3 are supplied, the FIFO memories 8A to 8C supply the sub-picture data CHp2 to CH4 in accordance with the pulse timing.
Write p.

The read reset generation circuit 11 recognizes the temporal length of the data area FL based on the supplied main video data CH1p, and further divides the data area FL into four equal parts based on the recognized temporal length. And 1 from the beginning of the data
A read reset pulse RP1 in which a pulse is arranged at a time position of / 4 is created and supplied to the FIFO memory 8A. Similarly, a read reset pulse RP2 in which a pulse is arranged at a time position of 2/4 from the head of the data is created and supplied to the FIFO memory 8B. Similarly, a read reset pulse RP3 in which a pulse is arranged at a time position of 3/4 from the head of the data is created, and the FIFO memory 8C
To supply.

When the read resets RP1 to RP3 are supplied, the FIFO memories 8A to 8C read the sub-picture data CH2p to CH4p in accordance with the pulse timing, and read the sub-picture data CH2p 'to CH4.
p ′ is output to the multiplexer 9.

In the multiplexer 9, the main video data CH
1p, the read sub-picture data CH2p'-CH
By inserting 4p ', composite video data CHmp is created. At this time, the read sub-picture data CH2p ′ ~
CH4p ′ corresponds to the corresponding read reset pulse RP1
To RP3, the read sub-video data CH2p ′ is stored in the data area F
It is arranged in the data partial area FL2 located between 1/4 and 2/4 of the time interval from the beginning of L. Similarly, the read sub-picture data CH3p ′ is arranged in the data partial area FL3 located between the time intervals of 時間 to ／ when viewed from the beginning of the data area FL. Similarly, the read sub-picture data CH4p ′ is arranged in the data partial area FL4 located between the time intervals of ／ to ／ when viewed from the beginning of the data area FL.

Therefore, in the composite video data CHmp, the main video data CH1p is arranged in the data partial area FL1, and the sub video data CH2 is stored in the data partial area FL2.
p, the sub-picture data CH3p is arranged in the data partial area FL3, and the sub-picture data CH3p is arranged in the data partial area FL3. That is, in the composite video data CHmp, the main / sub video data C
The data format is such that H1 to CH4 are multiplexed.

The composite video data CHmp created in this way is output from the multiplexer 9 to the serial encoder 12, where it is converted into serial data. The serially converted composite video data CHm is output from the output terminal 4 to a single output transmission line B.

In the above-described embodiment, the signal processing circuit 6 is configured on the assumption that the main / sub-picture data CH1 to CH4 are data synchronized with each other. Therefore, when the main / sub-picture data CH1 to CH4 are not synchronized, there may be a large difference in timing such that the writing timing to the FIFO memories 8A to 8C exceeds the reading timing. Such a shift in the read / write timing causes the data arrangement order of each data itself in the sub-picture data CH2p ′ to CH4p ′ read by the multiplexer 9 to be out of order, which is a factor that hinders high-accuracy composite processing. Become.

Therefore, the main / sub-picture data CH1 to CH
4 are not synchronized, the signal processing circuit 20 shown in FIG.
It may be. Note that the signal processing circuit 20 basically has the same circuit configuration as the signal processing circuit 6 in FIG.
The same or similar parts are denoted by the same reference characters and description thereof will be omitted.

The signal processing circuit 20 includes a phase comparison circuit 2
1A to 21C and a delay switching circuit 22A as a delay circuit
-22C. Phase comparison circuit 2
1A to 21C are provided corresponding to the respective FIFO memories 8A to 8C, and the corresponding FIFO memories 8A to 8C are provided.
8C is compared with the phases between WP1 to WP3 and RP1 to RP3.

The delay switching circuits 22A to 22C are interposed between the serial decoders 7A to 7C and the FIFO memories 8A to 8C.
After performing a predetermined amount of delay processing on p, the corresponding F
The data is output to the IFO memories 8A to 8C. Further, the delay switching circuits 22A to 22C determine whether or not to perform the delay processing based on the phase comparison results of the correspondingly provided phase comparison circuits 21A to 21C.

Hereinafter, the operation of the connector provided with the signal processing circuit 20 will be described. Each phase comparison circuit 21A to 21C
Now, the write pulses WP1 to WP respectively input are
3 is compared with the phases of the readout pulses RP1 to RP3. At this time, when the phase of the main video data CH1 and the sub video data CH2 to CH4 are synchronized with each other, the phases of the read reset pulses RP1 to RP3 are
As shown in FIG. 4, the phases of the write reset pulses WP1 to WP3 have phase differences S1 to S3 at a time interval of at least 1/4 frame.

On the other hand, when the sub-picture data CH2 to CH4 are not sufficiently synchronized with the main picture data CH1, the phase differences S1 to S3 become small. S3 disappears, and finally a phase difference is generated in the opposite direction of the time axis. Then, a phenomenon occurs in which the read timing for the FIFO memories 8A to 8C overtakes the write timing on the time axis. In the FIFO memories 8A to 8C, data can be read and written by the read timing being earlier in time than the write timing, and if such read / write timing misalignment occurs, normal read / write can be performed. Disappears.

In FIG. 4, the read reset pulses RP1 to RP3 and the write reset pulse W which is temporally earlier than the pulses RP1 to RP3.
The phase differences S1 to S3 between P1 to WP3 are shown, but between the read reset pulses RP1 to RP3 and the write reset pulses WP1 to WP3 positioned temporally behind the pulses RP1 to RP3. Also produces similar phase differences S1 'to S3'. Needless to say, the above-described inconvenience of the phase differences S1 'to S3' causes the same inconvenience as described above.

In order to eliminate such inconvenience, in the signal processing circuit 20, the phase comparison circuits 21A to 21C compare the phase difference between the write reset pulses WP1 to WP3 and the read reset pulses RP1 to RP3. If the phases of the two pulses match with a degree of coincidence equal to or greater than a predetermined value in the comparison result, it is determined that the data write operation and the data read operation are not synchronized with each other, and the phase match signals T1 to T3 are set to the corresponding delay switching circuit 22A ~
Output to 22C. The delay switching circuits 22A to 22C that have received the phase matching signals T1 to T3 delay the input sub-picture data CH2p to CH4p by a predetermined delay amount, and then output them to the FIFO memories 8A to 8C.
As a result, the normal read / write operation for the FIFO memories 8A to 8C is maintained, and the accuracy of the compound processing of the data in the multiplexer 9 can be increased.

In each of the above-described embodiments, the present invention is embodied in a connector used for a video data transmission path. However, the present invention is not limited to such a connector. Needless to say, the present invention can also be applied to a data transmission path.

In each of the above embodiments, the SMP
Although the present invention has been implemented in a connector used for a transmission line of compressed data compressed according to the TE305M standard, the present invention is not limited to such a connector, and data of any compression form is applicable. Needless to say, in the embodiment described above, by providing the serial decoders 7A to 7D and the serial encoder 12, the parallel data can be stored in the FIFO memory 8
A to 8C, the multiplexer 9 and the like have been used for the complex processing, but without providing the serial decoders 7A to 7D and the serial encoder 12, the serial data remains unchanged.
Needless to say, the composite processing may be performed. However, there is the following advantage by performing the compounding process using the parallel data. That is, since the serial data includes data depending on the data at the previous position, the multiplex 9
When a plurality of serial data are combined, when the combined data is demodulated later, there is a possibility that the combined data may not be well connected to the previous data. On the other hand, such a problem does not occur when the parallel data is subjected to the complex processing.

[0043]

As is apparent from the above description, according to the present invention, the following effects can be expected. That is, if the connector of the present invention is used, data transmitted through a plurality of transmission paths is converted into composite data that can be transmitted through a single transmission path by this connector, and is output. The transmission efficiency can be increased and transmission can be performed with the minimum necessary transmission equipment.

[Brief description of the drawings]

FIG. 1 is a plan view showing a schematic configuration of a connector according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a use form of the connector of the embodiment.

FIG. 3 is a circuit block diagram illustrating a configuration of a signal processing circuit that is a main part of the connector according to the embodiment.

FIG. 4 is a timing chart for explaining the operation of the connector according to the embodiment.

FIG. 5 is a circuit block diagram illustrating a configuration of a signal processing circuit that is a main part of a connector according to another embodiment of the present invention.

[Explanation of symbols]

2A to 2D input terminal 3 circuit board 4 output terminal 6 signal processing circuit 7A to 7D serial decoder 8A to 8CF
IFO memory 9 Multiplexer 10A-10C Write reset generation circuit 11 Read reset generation circuit 12 Serial encoder 20 Signal processing circuit 21A-21C Phase comparison circuit 22A-22C Delay switching circuit A1 Main input transmission path A2-4 Sub input transmission path B Output transmission Path C1 to C4 Connection terminal CH1 Main video data CH2 to 4 Sub video data CHm Composite video data WP1 to WP3 Write reset pulse RP1 to RP3 Read reset pulse

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/24 H04N 7/13 Z F-term (Reference) 5C056 FA02 HA13 JA01 JA06 5C059 KK41 RA01 RB01 RB14 RC02 RE02 RE09 SS11 TA71 TB04 TC45 TD11 UA23 UA24 UA34 5E021 FA05 FB16 FC40 MB20 5K028 AA06 AA12 AA17 EE03 KK01 KK18 SS05 SS06 SS15 SS16 5K034 AA12 CC03 DD01 HH01 HH02 HH05 HH16 KK13

Claims (5)

[Claims] 1. A connector provided on a transmission line for serially transmitting compressed data, comprising: an input terminal provided corresponding to each of a plurality of input transmission lines; and a plurality of input terminals input from the input terminal. A composite unit for composing data for each predetermined transmission unit; and an output terminal for outputting the data composited by the composite unit to a single output transmission line. connector. 2. The compressed data transmission connector according to claim 1, wherein the connector is based on the SMPTE305M standard.
A compressed data transmission connector, which is provided on a transmission path for transmitting compressed video data. 3. The connector for transmitting compressed data according to claim 1, wherein the data input from the input terminal is converted into parallel data, and then the parallel data is output to the composite device. And parallel / serial conversion means for converting the output of the composite means into serial data and outputting the output to an output terminal, and wherein the composite means converts the data of each input transmission line input in a parallel state. A connector for transmitting compressed data, wherein the connector is a composite. 4. The compressed data transmission connector according to claim 1, wherein the input terminal is a main input terminal to which the main data is input from a single main input transmission line; And a sub-input terminal that is provided corresponding to each of the sub-input transmission lines and receives the sub-data from the corresponding sub-input transmission line. A write reset generation circuit for generating a write reset pulse based on the input timing for each of the sub data, and a sub reset terminal corresponding to each sub input terminal based on the input timing of the main data input from the main input terminal. A read reset generating circuit for generating read reset pulses to be shifted at mutually different output timings; And a storage circuit that starts writing the sub data in synchronization with the corresponding write reset pulse, and starts reading the sub data in synchronization with the read reset pulse. A data composite circuit for inserting the sub data into main data input from a main input terminal. 5. The compressed data transmission connector according to claim 4, wherein a phase comparison circuit that compares a phase of each of the write pulses with a phase of the read pulse is provided corresponding to each of the sub-input terminals. When the phases of the two pulses in the comparison result of the phase comparison circuit coincide with each other with a predetermined degree of coincidence, the sub-data input from the sub-input terminal corresponding to the write pulse is delayed, and A compressed data transmission connector, further comprising: a delay circuit for outputting to the storage circuit.