JP2001127207A - Substrate for mounting semiconductor element, manufacturing method thereof and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which is high in reliability, can be miniaturized, can be reduced in its manufacturing cost and has substrates which are respectively provided with a recessed part for mounting a semiconductor element. SOLUTION: A drawable wiring body, which is constituted of copper wirings 12 which are used as wiring members, a barrier layer 11, such as a nickel alloy layer, and a copper foil 10, which is used as a carrier layer, is bonded to resin substrates 14 and 15 and at the same time, the wiring body is subjected to press processing by the projection part 13a of a metal mold 13, whereby with wirings 2 buried in the surfaces of the substrates formed, steps are provided between semiconductor elements 1 constituting both end parts of the wirings 2 and inner connection terminal parts, which are connected with the elements 1, and between external connection terminals 5 and external connection terminal parts, which are connected with the terminals 5, whereby recessed parts capable of housing the elements 1 are formed in the central parts of the said substrates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting substrate on which a semiconductor element is mounted, a method for manufacturing the same, and a semiconductor device having a semiconductor element mounting substrate on which a semiconductor element is mounted.

[0002]

2. Description of the Related Art In recent semiconductor devices, a multi-pin, small-sized package is desired due to an increase in integration degree and an increase in frequency. Therefore, in the case of the peripheral terminal type using the conventional lead frame, the package becomes large as the number of terminals increases. One of the measures is to reduce the terminal pitch.
0.4 mm or less is in a difficult situation.

As a measure against the increase in the number of terminals, there is an area array type package in which terminals are arranged in a plane. This area array package requires a wiring board for routing wiring from chip terminals to external terminal electrodes. If the external terminal electrodes are provided on the lower surface of the wiring board, the mounting surface of the chip is divided into an upper surface and a lower surface of the wiring substrate. When a chip is mounted on the upper surface of the wiring board, an interlayer connection between the upper surface and the lower surface of the wiring substrate is required. When a chip is mounted on the lower surface of the wiring board, this connection is unnecessary. However, when the chip is mounted on the lower surface of the wiring board, a concave portion is required to absorb the thickness of the chip and the thickness required for sealing.

[0004] The recess is called a cavity, and when the cavity exists on the lower surface, it is called a cavity-down structure. In order to make this structure, it is generally possible to make it by sitting the substrate or by hollowing out the substrate and bonding the bottom plate. In this structure, the wiring surface is the same,
When changing the height of the chip connection part and the external electrode, wiring of a multilayer structure is required. By these methods, it is possible to form a wiring structure that satisfies the three-dimensional positional relationship among the chip housing part, the chip connection part, and the external electrode part.

[0005]

As one of the area array type semiconductor packages, there is a ball grid array (BGA) using solder balls for connection terminals. This BG
A is higher in price than a semiconductor device using a conventional lead frame, and it is desired to reduce the price. The reason why the price is high is that the structure and manufacturing process of the semiconductor element mounting substrate are more complicated than those of the lead frame. Therefore, development of a semiconductor element mounting substrate having a simple structure and a simple manufacturing process is desired.

A wiring board used for an area array type semiconductor package is generally called an interposer. The interposer is roughly classified into a film shape and a rigid plate shape. The number of wiring layers is one, two, or three or more. In general, the manufacturing cost is low when the number of wiring layers is small.

The lowest cost can be expected from a one-layer wiring structure. When the wiring exists on at least both surfaces of the interposer, the semiconductor chip mounting portion and the external terminals can be divided into front and back surfaces. However, in an interposer having a one-layer wiring structure, the semiconductor chip mounting portion and the external terminals are on the same plane. In such a one-layer wiring structure, it is necessary to provide at least a recess having a thickness of at least about the thickness of the chip on the wiring surface side in order to accommodate the semiconductor chip, and the manufacturing method thereof has been an issue.

[0008] TAB (Tape Automated Bonding) and TCP (Ta
In the interposer and package technology called “pe Carrier Package”, semiconductor chips are installed through the center of the interposer. In the rigid board, a semiconductor chip accommodating portion is also formed by penetrating the center of the interposer, and a metal plate is adhered as a bottom plate, or a recess is formed by counterboring the center of the interposer. In such a method, the wiring is in the flat portion and not in the concave portion.

The present invention has been made in consideration of the above points, and has as its object to enable downsizing, high reliability, and low cost, and to facilitate standardization of design and manufacturing methods. An object of the present invention is to provide a semiconductor element mounting substrate on which a semiconductor element is mounted, a method of manufacturing the same, and a semiconductor device in which a semiconductor element is mounted on the semiconductor element mounting substrate.

[0010]

According to the present invention, there is provided a semiconductor element mounting substrate having a concave portion, or a semiconductor device having a semiconductor element mounted in the concave portion and sealed with a sealing resin. In the apparatus, the substrate for mounting a semiconductor element includes a wiring disposed along a surface of the substrate and a wall surface of the substrate in the recess, and the wiring includes an external connection terminal provided on the surface of the substrate on a side where the recess opens. An external connection terminal portion to be connected, an inner connection terminal portion connected to the mounted semiconductor element, and a wiring portion between the external connection terminal portion and the inner connection terminal portion, wherein the wiring is The inner connection terminal portion is embedded in the substrate surface and the substrate wall surface of the concave portion, and the inner connection terminal portion is located in the concave portion.

[0011] For example, the substrate wall surface of the concave portion has a slope extending in the direction of the bottom surface of the concave portion within a predetermined inclination angle range, and the inclination angle is 5 to 40 degrees, more preferably 10 to 40 degrees. Within the range of degrees. When the height G of the substrate wall surface of the recess and the horizontal distance L are used, the ratio L / G between the two is 1.5 <L / G <10, more preferably 2 <L / G <. 10, most preferably 3 <L / G <
The inclined structure is set so as to fall within the range of 10.

The recess is formed by, for example, a convex press molding. Further, the concave portion may be formed in a plurality of steps.

[0013] The recess may be provided with a semiconductor element accommodating portion for accommodating a semiconductor element formed by further counterboring the recess. In this case, it is preferable that the depth of the counterbore-processed semiconductor element housing portion is larger than the thickness of the semiconductor chip to be mounted.

Further, in the semiconductor element mounting substrate and the semiconductor device according to the present invention, the step between the external connection terminal on the surface of the substrate and the inner connection terminal in the recess is 0.05 mm or more. Is preferred.

The terminal of the semiconductor element mounted in the concave portion is connected to the inner connection terminal portion by wire bonding or directly connected to the inner connection terminal portion face down.

Further, in the semiconductor element mounting substrate and the semiconductor device according to the present invention, it is preferable that the wiring is provided in a wall surface region excluding a corner of the concave portion.

Further, the concave portion is formed substantially at the center of the main plane of the substrate, and the semiconductor element is mounted in the concave portion so as to be substantially at the center in the thickness direction of the semiconductor element mounting substrate. It may be. Further, a configuration may be adopted in which the semiconductor element is mounted in the recess so as to be offset from the center in the thickness direction of the substrate within 30% of the thickness of the substrate. In addition, the bottom surface area of the concave portion is set to have a width capable of accommodating a plurality of elements, wirings to the plurality of elements are formed, and a plurality of semiconductor elements and passive elements are mounted in the concave portion. Is also good.

Further, in the semiconductor element mounting substrate and the semiconductor device according to the above invention, the wiring is formed by using a wiring structure which is made of metal and can be drawn. Preferably, the possible wiring structure has a structure including at least a first metal layer forming the wiring and a second metal layer functioning as a carrier layer.

The depth of the recess is smaller than the thickness of the semiconductor element to be mounted, and the bottom surface of the recess is to be mounted from the center in the thickness direction of the substrate for mounting the semiconductor element. The counterbore processing may be performed to a depth in the range of 0.5 to 2.5 times the thickness. Further, the depth of the recess is smaller than the thickness of the semiconductor element to be mounted,
In addition, a configuration may be employed in which a resin layer is formed by subjecting the bottom surface of the concave portion to a counterbore process and curing the prepreg so that at least the exposed counterbore bottom surface is made of a nonwoven fabric. In this case, a metal plate having a thickness of 0.035 mm or more is adhered to the back surface of the resin layer in which the concave portion is formed, and the depth of the concave portion is made smaller than the thickness of the semiconductor element to be mounted.
In addition, a counterbore process is performed on the bottom surface of the concave portion to expose the metal plate. Alternatively, a metal plate having a thickness of 0.20 mm or more is adhered to the back surface of the resin layer in which the concave portion is formed, the depth of the concave portion is made smaller than the thickness of a semiconductor element to be mounted, and The bottom surface of the concave portion is subjected to a counterbore process so that the counterbore depth becomes 0.05 mm or more.

The counterboring of the resin layer may be completed before the resin layer reaches the metal plate.

According to another aspect of the present invention, there is provided a method of manufacturing a substrate for mounting a semiconductor element, the method comprising a structure including at least a first metal layer and a second metal layer functioning as a carrier layer thereof. And pressing and bonding the drawable wiring structure composed entirely of metal to the resin substrate, and at the same time, forming a concave portion having a wall surface with a slope within a predetermined inclination angle range on the resin substrate, By removing the other metal layer while leaving one metal layer, an external connection terminal portion connected to an external connection terminal provided on the surface of the substrate on the side where the concave portion is opened, and a connection to a mounted semiconductor element The wiring embedded in the surface of the substrate and the wall surface of the substrate in the concave portion, comprising: an inner connection terminal portion to be formed; and a wiring portion between the external connection terminal portion and the inner connection terminal portion. Wherein placing formed along the substrate wall surface of the recess from the surface.

Here, it is preferable that the elongation at break of the drawable wiring structure is 2% or more. Further, it is preferable that the thickness of the carrier layer constituting the drawable wiring structure is in the range of 0.010 mm to 0.050 mm. Preferably, the inclination angle range of the substrate wall surface of the recess is not less than 5 degrees and not more than 40 degrees, and the depth of the recess is at least 30% of the thickness of the semiconductor element to be housed. Further, after forming the concave portion, a counterboring process is performed on the bottom surface of the concave portion, and after the counterboring process,
The configuration may be such that the other metal layer is removed. When the counterboring process is performed in a state where there is another metal layer, the end portion can be accurately counterbored.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor element mounting substrate including a concave portion for mounting a semiconductor element and a wiring, the method comprising: And a counterboring process is performed on the bottom surface of the concave portion. At the time of the counterboring process, a part of the wiring to the mounted semiconductor element is cut, and the end of the wiring is counterbored. Characterized by reaching the edge of the recess formed by the above. The processing accuracy of the etched portion of the concave portion is improved.

According to the present invention, a recess capable of accommodating a semiconductor element can be formed, and fine wiring corresponding to a connection pitch of the semiconductor element can be formed, which is suitable for an area array type semiconductor package. Semiconductor packages using this technology include CSP (Chip Scale Package), FBGA (Fine Pitch Bal
l Grid Array), BGA (Ball Grid Array), LGA (Land Gr
id Array).

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. The present invention is not limited to the embodiments described below.

As shown in the drawings, the semiconductor device according to the present embodiment includes a semiconductor element (semiconductor chip) 1, an insulating substrate 7 having a concave portion or a through hole for mounting the semiconductor chip 1, and an insulating substrate 7. An external electrode 5 formed on the surface of the semiconductor chip 7 and electrically connected to the semiconductor chip 1 and connected to the outside at the time of mounting, and a sealing resin 4 sealing a concave portion or a through-hole portion housing the semiconductor chip 1. Is provided.

The semiconductor device of the present embodiment is further provided with a wiring 2 for electrically connecting the semiconductor chip 1 and the external electrodes 5. The wiring 2 includes an inner connection terminal portion to which a wire 3 for connecting to the semiconductor chip 1 is connected, an external terminal connection portion to which an external electrode 5 is connected, and a connection between the inner connection terminal portion and the external connection terminal portion. And a step portion is provided between the inner connection terminal portion and the external connection terminal portion.

Here, the wiring 2 connecting between the wire 3 and the external electrode 5 is continuously embedded from the surface layer portion of the substrate on which the external electrode 5 is disposed to the surface layer portion of the wall surface or the bottom surface of the concave portion. And The semiconductor chip 1, the wire 3, the connection part (inner connection terminal part) between the wire 3 and the wiring 2, and the main part or all parts of the wiring 2 are located in the recesses and are sealed with the sealing resin 4. Has been stopped.

In FIGS. 1 to 4, reference numeral 6 denotes a surface insulating layer formed on the surface of the insulating substrate 7, and in FIGS. 1 and 4, reference numeral 8 denotes a metal plate provided on the back side of the insulating substrate 7. The semiconductor device and the semiconductor element mounting substrate have a multi-layer structure including at least a first metal layer and a second metal layer functioning as a carrier layer thereof, and are all made of metal and can be drawn. At the same time as bonding to the resin substrate, forming the concave portion having a wall surface with a slope within a predetermined tilt angle range on the resin substrate,
By removing the other metal layer while leaving the metal layer, the external connection terminal portion connected to the external connection terminal provided on the surface of the substrate on the side where the concave portion is opened, and the semiconductor element mounted thereon are connected. An inner connection terminal portion, and a wiring portion between the external connection terminal portion and the inner connection terminal portion, the wiring embedded in the substrate surface and the substrate wall surface of the concave portion, from the substrate surface. It is manufactured by arranging and forming along the substrate wall surface of the concave portion.

When the wiring structure capable of being drawn is pressed and adhered to a resin substrate, and the other metal layer is removed while leaving the first metal layer, the other metal layer of the wiring which is the first metal layer is removed. The three surfaces that are not in contact with the substrate are embedded in the resin substrate, and the one surface that is in contact with the other metal layer of the wiring is exposed on the same surface as the resin substrate.
The fact that the wiring is buried in the present invention means such a thing.

In the wiring structure capable of being drawn,
The width of the wiring surface (a) in contact with another metal layer of the wiring as the first metal layer is larger than the width of the wiring surface (b) opposite to the wiring surface (a). In the present invention, the surface of the wide wiring (a) is exposed and can be used as a terminal, so that the wiring density per unit area can be increased and the density can be increased.

The wiring structure capable of being drawn may have a multilayer structure including at least a first metal layer functioning as a wiring and a second metal layer functioning as a carrier layer thereof.
A structure including a first metal layer functioning as a wiring formed by half-etching from one surface of one metal foil through a predetermined resist pattern to form a wiring and a second metal layer functioning as a carrier layer thereof may be used.

In a case where the drawable wiring structure is pressed and adhered to a resin substrate to remove the other metal layer while leaving the first metal layer, a part of the other metal layer, for example, an inner connection terminal Parts, external connection terminal parts, etc. can also be left.

The concave portion is formed by press-forming a convex shape corresponding to the concave portion. The concave portion itself or the concave portion is further counterbored to form a semiconductor element accommodating portion serving as an accommodating portion of the semiconductor chip 1. . Here, a plurality of recesses may be provided.

It is preferable that the depth of the recess or the semiconductor element receiving portion formed by counterboring the recess is larger than the thickness of the semiconductor chip 1 to be mounted.

In the case where the concave portion is counterbored, the other metal layer (carrier layer) may be removed after the counterboring process.

In the present embodiment, the inclination angle of the inclined portion where the wiring 2 is provided is a predetermined angle range set in accordance with the manufacturing conditions in the method of manufacturing the device substrate described in detail below. Inside.

More specifically, the inclination angle of the wall surface of the concave portion is 5 to 40 degrees or less, more preferably 5 to 40 degrees.
-25 degrees, more preferably 5-18 degrees. This inclination angle is determined not only by the shape of the mold projection used in the press working, but also by the physical properties of the drawable wiring structure (transfer metal foil) used to form the wiring 2 and the manufacturing conditions at the time of pressing the recess. It is determined according to the above. The tilt angle means the maximum tilt angle.

When expressed using the height G of the inclined portion and the horizontal distance L (see FIG. 1), the inclination of the semiconductor device of this embodiment is set to 1.5 <L / G <10. More preferably 2 <L / G <10, most preferably 3 <L / G
<10.

The depth of the step is preferably 30% of the thickness of the semiconductor chip 1 to be housed. Since the thickness of the semiconductor chip 1 is generally 0.2 to 0.5 mm, the depth of the step needs to be at least 0.06 to 0.15 mm.

The depth of the step differs depending on the height of the external electrode 5. As shown in FIGS. 1 to 4, when a solder ball is used for the external electrode 5, the margin varies depending on the size of the solder ball. For example, if the diameter of the solder ball is 0.7 m
When the distance is about m, low wire bonding is performed, and the height of the sealing resin 4 is suppressed to about 0.2 mm, so that the distance between the package and the mother substrate can be sufficiently maintained. However, when the diameter of the solder ball is less than 0.4 mm, it is difficult to keep the distance between the package and the mother board without providing a recess.

In addition, an LGA (Land
In a Grid Array, it is necessary to provide a wire bond connection portion in a concave portion.

In the case where a square or rectangular step is provided on the insulating substrate 7 on which the semiconductor chip 1 is mounted, the corner portion is most easily broken. In addition, even when the fracture does not occur, it is subjected to the largest deformation. Therefore, if wiring is provided in the corner portion, a problem may occur in long-term reliability, and it is preferable that no wiring be provided here. When wiring is provided at the corner, R may be provided at the corner.

The semiconductor chip 1 is mounted in the concave portion of the insulating substrate 7 so as to be located at the center with respect to the thickness direction of the substrate. Therefore, warpage of the semiconductor device when a temperature cycle occurs can be reduced.

On the other hand, when the semiconductor element is mounted offset from the center, there is a relationship between the rigidity of the substrate and the amount of curing shrinkage of the sealing resin. Can be secured.

Further, in addition to the formation of the recess by pressing, the receiving portion of the semiconductor chip 1 is further counterbored as shown in FIG. 1 or FIG. A substrate can be manufactured. The counterbore processing is generally performed on a printed wiring board, and is mechanically performed by an end mill, and the processing dimensions can be precisely controlled in both XYZ directions.

In the present embodiment, the counterbore depth needs to be within a range of 0.5 to 2.5 times the thickness of the storage chip. This is related to the ease of wire bond connection. For low loop wire bonding with a low height, it is better that the change in height between the chip side bonding position and the substrate side bonding position is small.

The state of the counterbored surface affects the adhesion to the semiconductor chip 1 and the adhesion to the sealing resin 4. When the insulating substrate 7 for mounting the semiconductor chip 1 is formed from cloth-like continuous glass fibers, the glass fibers and the resin may peel off on the counterbored surface. In such a case, the wettability of the sealing resin or the die bonding resin to the counterbored surface is poor, and the adhesive strength is weak. In the nonwoven fabric, the glass fibers are short fibers and the counterbored surface is smooth. Accordingly, the sealing resin and the die bonding resin have good wettability to the counterbore-processed surface and have a strong adhesive force. The detailed manufacturing method will be described below.

Further, a concave portion and a wiring having a thickness insufficient for accommodating a semiconductor element are formed in the center of the insulating substrate 7, and the concave portion is counterbored to cut a part of the wiring 2 at the time of counterbore. Alternatively, the configuration may be such that the end of the wiring 2 reaches the recess formed by the counterbore.

Further, as shown in FIG. 3, a recess capable of accommodating a plurality of elements and the wiring 2 are formed in the center of the insulating substrate 7.
A configuration in which a plurality of semiconductor elements, passive elements, and the like are mounted in the recess may be adopted. The wiring 2 is used for wiring between the semiconductor chips in the concave portion and for wiring between the concave portion and the outside of the concave portion.

Furthermore, if the metal plate is placed on the back side during the depression forming press, the metal parts that can function as a heat dissipation layer and the like can be integrated at the same time.

As shown in FIG. 4, the metal plate 8 attached to the back surface of the insulating substrate 7 may be counterbored to expose the metal layer on the bottom surface of the recess formed by the counterbore. When using an end mill for a counterbore for exposing a metal layer, it is necessary to cut into a metal surface. Therefore, it is necessary to make the metal plate 8 thick. When a thin metal layer is used, it is practically difficult to correct the plate thickness accuracy by end milling, but it can be manufactured by laser processing, plasma processing, resin etching, or the like alone or in combination with end milling. Alternatively, a portion requiring a counterbore may be cut out, and another substrate or a metal plate may be bonded.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

The first example will be described.

In the manufacturing method according to this embodiment, first, as shown in FIG. 5 or FIG. 6, a transfer metal foil for forming wiring including the wiring 2 has a thickness of 35 μm.
0.5 μm nickel layer 1 on m copper foil (carrier foil) 10
1 is formed by plating, and a three-layer structure foil in which a copper layer 12 of 5 μm is further formed is used. This copper foil is manufactured by Nippon Electrolysis Co., Ltd.

In the present invention, the transfer metal foil is entirely made of metal and may have a structure other than the above structure as long as it does not contain any resin or the like. That is, the transfer metal foil is formed of at least a carrier layer (in this example, copper foil 1).
0) and a wiring layer (copper layer 12 in this example), and when the carrier layer and the wiring layer are made of the same metal,
A barrier layer made of a different kind of metal (in this example, nickel alloy 1
1) is provided between layers. Note that the carrier layer is removed by etching in a later step. A part of the carrier layer may be left and used as a terminal.

Further, the metal foil for transfer has a temperature of 2 ° C. in a process temperature range (150 ° C. to 250 ° C., which is a press temperature).
% Or more (elongation at break is preferably 100% or less). In the transfer metal foil, the thickness of the carrier layer is in the range of 0.010 mm to 0.050 mm. If it is thinner, it is difficult to handle,
If it is thicker, it becomes difficult to follow the mold shape. Immediately before pressing in the transfer step, the carrier layer can be thinned by etching the front surface on which no wiring is formed.

In this embodiment, the thickness of the wiring member is 5 μm.
The m copper layer 12 was etched by forming a resist pattern by a normal photoresist method. The etchant is
Selectivity for etching copper without etching nickel is required. Alkaline etchants commonly used in the printed circuit board industry are preferred. The carrier foil 10 having a thickness of 35 μm was protected with a resist so as not to be etched.

The patterned copper foils 10 to 12 are
At a temperature of 180 ° C. and a pressure of 25 kg / cm ²
For 2 hours. FIG. 7 shows a plurality of aluminum foils 18, a three-layer patterned copper foil (copper foil 10, nickel alloy 1) between upper press mold 13 and lower press mold 17 from above.
1, copper wiring 12), a plurality of glass cloth prepregs 14, non-woven cloth prepregs 15, glass cloth prepregs 14, and a copper foil 16 as a metal plate are shown.

The protrusion 13a of the upper press die 13 has a trapezoidal cross section, a height of 0.15 mm, and a slope angle of the side surface of 45 degrees. An aluminum foil 18 having a thickness of 25 μm is placed between the mold and the copper foil 16 as a cushion layer.
I inserted and pressed. As the prepreg, Hitachi Chemical Co., Ltd. made by impregnating a glass cloth or the like with a heat-resistant epoxy resin was used.

Here, a total of eight glass cloth prepregs 14 having a thickness of 0.1 mm were used. Further, one nonwoven fabric prepreg 15 having a glass fiber thickness of 0.2 mm was used.
This nonwoven fabric prepreg was inserted between the sixth and seventh glass cloth prepregs. A large number of glass epoxy substrates manufactured under such conditions are formed individually, and a large number of identical wirings and recesses are formed. The carrier copper foil 10 was etched and removed entirely by the alkali etchant described above, and then the nickel layer 11 was etched and removed by a nickel selective etching solution.

Under the above conditions, a plate having a thickness of 1.0 mm had a concave portion having a depth of 0.15 mm, and wiring could be formed continuously on the surface layer including the concave portion. In order to further adjust the depth of this substrate from the recess with an end mill device,
It was milled to a depth of 0.55 mm and processed so that a semiconductor chip could be mounted. A solder resist layer is provided by a usual method, and nickel is 5 μm and gold is 0.5 μm in the terminal portion.
m.

Here, a semiconductor chip 1 having a thickness of 0.28 mm was bonded to the concave portion and connected by wire bonding. The semiconductor chip 1 and the wire bond portion (the inner connection terminal portion of the wire 3 and the wiring 2) were sealed with the liquid resin 4, and after mounting the solder ball 5, it was cut and separated into individual pieces to obtain a semiconductor device.

By the above manufacturing method, for example, a structure as shown in FIG. 1 is obtained. According to this structure, a relatively small package having a size close to the chip size can be manufactured, and a chip scale package can be manufactured.

A second example will be described.

In the manufacturing method according to the present embodiment, the thickness 35
A three-layer foil is prepared by forming a 0.5 μm nickel layer on a μm copper foil (carrier foil) by plating and further forming a 5 μm copper layer. This copper foil is manufactured by Nippon Electrolysis Co., Ltd.

The copper layer having a thickness of 5 μm was etched by forming a resist pattern by a usual photoresist method. The etchant must have selectivity to etch copper without etching nickel. Alkaline etchants commonly used in the printed circuit board industry are preferred. The carrier foil having a thickness of 35 μm was protected with a resist so as not to be etched.

Copper foil 10, nickel alloy 11, and copper layer 1
8 was heated and pressed at a temperature of 180 ° C. and a pressure of 25 kg / cm ² for 2 hours in the configuration shown in FIG. FIG. 8 shows the upper press die 13 and the lower press die 17.
In between, aluminum foil 18, copper foil with a three-layer pattern (copper foil 10, nickel alloy 11, copper layer 12), glass cloth prepreg 14, prepreg 1 having a plurality of hollows
9 shows a configuration in which a plurality of glass cloth prepregs 14 and a copper foil 16 as a metal plate are arranged.

The protrusion of the upper press die 13 has a height of 0.5 mm.
The inclination angle of the side surface is 30 degrees. 25μm thickness between mold and copper foil as cushion layer
And pressed.

The prepreg used was a product made by Hitachi Chemical Co., Ltd. obtained by impregnating a glass cloth with a heat-resistant epoxy resin. A prepreg was produced by hollowing out a portion corresponding to the protrusion of the press upper die 13, and the thickness corresponding to the height of the protrusion was used as a layer structure. In the case of the projection height of 0.5 mm this time, the thickness is 0.1 m
Five prepregs with a hollow of m and five prepregs without a hollow were used.

The glass epoxy substrates manufactured under the above conditions are formed in multiple pieces, and the same wiring and many concave portions are formed. The carrier copper foil 10 was etched by the above-described alkali etchant to remove the entire surface. Next, the nickel layer 11 was removed by etching with a nickel selective etching solution.

As described above, a plate having a depth of 0.5 mm
The wiring was able to be continuously formed on the surface layer including the concave portion having the concave portion of mm. A solder resist layer was provided by an ordinary method, and nickel was plated to a thickness of 5 μm and gold to a thickness of 0.5 μm on the terminal portion. The semiconductor chip 1 was bonded to the recess and connected by wire bonding. The chip and the wire bond were sealed with the liquid resin 4. After mounting the solder balls 5, the substrate was cut to obtain individual semiconductor devices.

According to the manufacturing method of the present example, a structure in which a metal plate is further attached to the back surface of the substrate as shown in FIG. 2 or 3 can be obtained. According to the structure of the present example, the inclination angle of the inclined portion is small, so that the inclined portion is long and the package size is large. However, the counterbore process is unnecessary, and the cost can be reduced. Further, as shown in FIG. 3, there is an effect that a plurality of chips can be accommodated and wiring between the chips can be formed simultaneously.

Next, a third example will be described.

In the manufacturing method according to this example, the thickness 35
A three-layer foil is prepared by forming a 0.5 μm nickel layer on a μm copper foil (carrier foil) by plating and further forming a 5 μm copper layer. This copper foil is manufactured by Nippon Electrolysis Co., Ltd.

The copper layer having a thickness of 5 μm was etched by forming a resist pattern by a known photoresist method. The etchant must have selectivity to etch copper without etching nickel. Alkaline etchants commonly used in the printed circuit board industry are preferred. The 35 μm-thick carrier foil was protected with a resist so as not to be etched.

This patterned copper foil was heated and pressed at a temperature of 180 ° C. and a pressure of 25 kg / cm ² for 2 hours in the configuration shown in FIG. FIG. 9 shows the upper press die 13 and the lower press die 1.
7, from above, an aluminum foil 18, a copper foil with a three-layer pattern (copper foil 10, nickel alloy 11, copper layer 12);
A configuration in which a plurality of glass cloth prepregs 14, 19 and a copper plate 16 'as a metal plate are arranged is shown.

The protrusion of the mold is 0.20 mm in height, and the inclination of the side surface is 30 degrees. 25μm thick aluminum foil 18 between the mold and copper foil as cushion layer
Was inserted and pressed.

The prepreg was manufactured by Hitachi Chemical Co., Ltd. in which glass cloth was impregnated with a heat-resistant epoxy resin and had a thickness of 0.1 mm.
6 prepregs were used. In the second and third prepregs 19, portions corresponding to mold projections are punched. Further, a copper plate having a thickness of 0.40 mm and subjected to an adhesion roughening treatment was arranged on the back side of the substrate, and pressed. The total thickness after pressing is 1.0 mm.

A large number of glass epoxy substrates manufactured under the above conditions are formed, and the same wirings and concave portions are formed in large numbers. This was etched on the carrier copper foil with the above-described alkali etchant to remove the entire surface. Next, the nickel layer was etched and removed with a nickel selective etching solution.

As described above, a plate having a thickness of 1.0 mm and a depth of 0.
Wiring was able to be continuously formed on the surface layer including the concave portion having a concave portion of 20 mm. This substrate was further milled to a depth of 0.65 mm by an end mill device, and processed so that a semiconductor chip could be mounted. A solder resist layer was provided by a usual method, and nickel was applied to the terminal portion at a thickness of 5 μm and gold was applied at a thickness of 0.1 μm.
It was plated to a thickness of 5 μm.

A semiconductor chip was adhered to the recess and connected by wire bonding. Liquid resin 4 for chip and wire bond
After mounting the solder balls 5, the semiconductor devices were cut and separated into individual pieces.

According to the manufacturing method of this embodiment, for example, a structure as shown in FIG. 4 is obtained. According to this structure, it is possible to provide a manufacturing method in which the heat sink can be assembled by batch press working, and low cost and high reliability can be achieved.

According to the above-described first to third examples, it is possible to reduce the size, increase the reliability, and reduce the cost, and to facilitate the standardization of the design and manufacturing method. An element mounting substrate, a method of manufacturing the same, and a semiconductor device in which a semiconductor element is mounted on a semiconductor element mounting substrate can be provided.

Next, another embodiment of the semiconductor device, the substrate and the manufacturing method according to the present invention will be described with reference to FIGS.

The semiconductor device of this embodiment is a semiconductor device in which a concave portion is provided in a part of a wiring substrate and a semiconductor chip is mounted in the concave portion, and is continuous with a surface layer portion of the wiring substrate including the concave portion of the wiring substrate. The wiring conductor is embedded.

More specifically, in a wiring board having two or more surface layers having different heights, as shown in FIG. 10, for example, as shown in FIG. Is provided, an inner connection terminal portion connected to the semiconductor chip 1 is provided on the second surface layer portion, a step of 0.05 mm or more is provided on the first surface layer portion and the second surface layer portion, and the first surface layer portion and This is a wiring board in which a wiring 2 is formed by embedding a continuous wiring conductor in a second surface portion and a surface layer in an intermediate portion thereof.

This wiring board can be realized by a manufacturing method in which a wiring conductor is provided on a metal foil such as copper and a concave portion is simultaneously formed when a resin layer is bonded to the metal foil.

Further, as a method of realizing this, in a method of manufacturing a wiring substrate in which a metal foil provided with a wiring conductor and a plurality of glass cloths impregnated with a resin are superposed and compressed to form a concave portion, the method corresponds to the concave portion. It can be manufactured by removing a part of the glass cloth in advance and then compressing it.

In another aspect of the present embodiment, in a wiring board having a concave portion, as shown in FIG. 11, for example, as shown in FIG. Provided. In the method of forming the two-step concave portion, the first step can be formed by compressing the prepreg using a mold having a convex portion to form the concave portion, and the second step can be formed by cutting.

A semiconductor device can be manufactured by providing a large number of recesses in one wiring board, mounting chips in each of the recesses, sealing with resin, mounting solder balls, and cutting and separating.

FIGS. 10 to 13 are cross-sectional views of a typical semiconductor device according to the present embodiment.

1 is a semiconductor chip, 2 is a wiring, 3 is a wire, 4 is a sealing resin, 5 is an external terminal electrode, 6 is a surface insulating layer, 7 is an insulating substrate, 8 is a metal plate, and 9 is an insulating plate. .

As shown in FIG. 11, a part of the recess may be a through hole, and the semiconductor device can be supported by a metal plate 8 and an insulating plate 9 on the back surface as shown in FIGS. .

An example of the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIG.

A three-layer structure foil is prepared by forming a 0.5 μm nickel layer 11 on a 35 μm thick copper foil (carrier foil, manufactured by Nippon Electrolysis Co., Ltd.) 10 and further forming a 5 μm copper layer. A copper layer having a thickness of 5 μm was formed into a resist pattern by a normal photoresist method and etched to form a wiring conductor 12.

The etchant needs to have selectivity for etching copper without etching nickel. Alkaline etchants commonly used in the printed circuit board industry are preferred. The carrier foil having a thickness of 35 μm was protected with a resist so as not to be etched.

Copper foil 1 with this pattern (wiring conductor 12)
0 in the configuration shown in FIG. 14 at a temperature of 180 ° C. and a pressure of 25 kg /
The mixture was heated and pressurized at 2 cm ² for 2 hours. The protrusion of the mold 13 is 0.
It is manufactured at 15 mm and the inclination of the projection is 90 degrees. As a cushion layer, a Teflon (manufactured by DuPont) sheet (not shown) having a thickness of 50 μm was inserted between the molds 13 and 17 and the copper foils 10 and 16 and pressed. Prepreg (without hollow)
No. 14 was manufactured by Hitachi Chemical Co., Ltd. in which a heat-resistant epoxy resin was impregnated in a glass cloth.

[0099] The glass epoxy substrate manufactured under such conditions is formed in multiple pieces, and the same wiring and many concave portions are formed. This was etched on the carrier copper foil with the above-described alkali etchant to remove the entire surface.

Next, the nickel layer was etched and removed with a nickel selective etching solution. With the above conditions,
A substrate having a thickness of 1 mm has a concave portion having a depth of 0.15 mm, and wiring is continuously formed on a surface layer including the concave portion. This substrate was further milled by a milling device to a depth of 0.5 mm, processed so that the semiconductor chip 1 could be mounted, and further cut into individual pieces. The semiconductor chip 1 was bonded to the recess and connected by wire bonding. The semiconductor chip 1 and the wire bond portion were sealed with a liquid resin to obtain a semiconductor device.

FIG. 1 shows another example of the manufacturing method according to the present embodiment.
This will be described with reference to FIG.

A copper foil 10 having a pattern similar to that of the example shown in FIG. 14 was prepared by using the structure shown in FIG.
It was heated and pressurized at g / cm ² for 2 hours. In this example, the protrusion of the mold 13 is manufactured with 0.5 mm and the gradient of the protrusion is 45 degrees.

As a cushion layer, a Teflon (manufactured by DuPont) sheet (not shown) having a thickness of 50 μm was inserted between the dies 13 and 17 and the copper foils 10 and 16 and pressed. As the prepreg 14, Hitachi Chemical Co., Ltd. made by impregnating a glass cloth with a heat-resistant epoxy resin was used. A prepreg 15 was produced by hollowing out a portion corresponding to a mold protrusion, and a thickness corresponding to the height of the protrusion was used as a layer structure.

When the projection height is 0.5 mm as in this example,
Five hollow prepregs 15 having a thickness of 0.1 mm and five prepregs 14 without hollow were used. A large number of glass epoxy substrates manufactured under such conditions are taken individually, and many identical wirings and concave portions are formed. This was etched on the carrier copper foil with the above-described alkali etchant to remove the entire surface. Next, the nickel layer was etched and removed with a nickel selective etching solution.

Under the above conditions, a plate having a thickness of 1 mm has a concave portion having a depth of 0.5 mm, and wiring is continuously formed on a surface layer including the concave portion. The semiconductor chip 1 was bonded to the recess and connected by wire bonding. The semiconductor chip 1 and the wire bond were sealed with a liquid resin. After mounting the solder balls 5, the substrate was cut into individual semiconductor devices.

Another example of the manufacturing method according to the present embodiment is shown in FIG.
This will be described with reference to FIG.

A copper foil 10 having a pattern similar to that of the example shown in FIG. 14 was prepared by using the structure shown in FIG.
It was heated and pressurized at g / cm ² for 2 hours. The projection of the mold 13 is manufactured with 0.5 mm and the inclination of the projection is 45 degrees. As a cushion layer, a Teflon (manufactured by DuPont) sheet (not shown) having a thickness of 50 μm was inserted between the molds 13 and 17 and the copper foils 10 and 16 and pressed. The prepreg used was made by Hitachi Chemical Co., Ltd. in which a glass cloth was impregnated with a heat-resistant epoxy resin.

Glass epoxy substrate 1 having a thickness of 0.5 mm
8 'was cut out at a portion corresponding to the mold projection. In this case, the prepreg 14 having a thickness of 0.1 mm and having no hollow is used.
Was placed between one glass epoxy substrate 18 ′ and the patterned copper foil 10, and three prepregs 14 were used below the glass epoxy substrate 18 ′.

The glass epoxy substrate manufactured under such conditions is formed in multiple pieces, and the same wiring and concave portions are formed in large numbers. This was etched on the carrier copper foil with the above-described alkali etchant to remove the entire surface. Next, the nickel layer was etched and removed with a nickel selective etching solution.

Under the above conditions, a plate having a thickness of 1 mm had a concave portion having a depth of 0.5 mm, and wiring could be formed continuously on the surface layer including the concave portion. The semiconductor chip 1 was bonded to the recess and connected by wire bonding. The semiconductor chip 1 and the wire bond were sealed with a liquid resin. After mounting the solder ball,
The substrate was cut into individual semiconductor devices.

As described above, according to the present embodiment, the semiconductor device has a simple structure and can be manufactured at a low cost by a simple manufacturing process.

Next, another embodiment of the semiconductor device, substrate and manufacturing method according to the present invention will be described with reference to FIGS. As shown in FIG. 17, the semiconductor device according to the present embodiment includes a semiconductor chip 1, an insulating substrate 7 including a semiconductor element housing for mounting the semiconductor chip 1, and a semiconductor chip formed on the surface of the insulating substrate 7. An external electrode 5 electrically connected to the semiconductor chip 1 and connected to the outside at the time of mounting; and a sealing resin 4 sealing a semiconductor element housing portion housing the semiconductor chip 1. A step is provided between a wire 3 for connection to the external electrode 5 and the external electrode 5, and a wiring 2 is provided along an inclined portion connecting the step. Reference numeral 6 in the drawing indicates a surface insulating layer formed on the surface of the insulating substrate 7.

In the semiconductor device of the present embodiment, for example, in a semiconductor element mounting substrate having a recess manufactured by the manufacturing method of FIG. Are formed in the semiconductor element accommodating portion.

The inclination angle of the wall surface of the concave portion of the substrate is gentler than 45 degrees. The inclination angle is determined by the inclination angle of the protrusion of the mold used for press molding, the balance between the rigidity of the copper foil (carrier layer) 10 used for transfer and the pressing pressure, and the like.

The semiconductor device according to the present embodiment is not limited to the example shown in FIG. 17. For example, as shown in FIG. A multilayer structure in which a ground layer 1801 is provided with a layer interposed therebetween may be employed. Further, the ground layer 180
It may be configured to include an interlayer connection portion 1802 connecting the first electrode 1 and the external electrode 5.

In the present embodiment, the method for forming the ground layer 1801 and the method for interlayer connection are not particularly limited. For example, a copper foil or a copper pattern serving as the ground layer 1801 is opposed to the formed wiring board, an insulating adhesive sheet such as a prepreg is interposed therebetween, and a prepreg is further laminated and pressed to form a multilayer-structured board. Form.

An example of a method of manufacturing a semiconductor element mounting substrate according to the present embodiment will be described with reference to FIGS.

In the manufacturing method of this embodiment, the basic structure is the same as that of the above-described two embodiments. Hereinafter, different portions will be mainly described, and description of similar portions will be omitted.

In the manufacturing method according to this embodiment, similarly to the above two embodiments, a copper foil (carrier layer) 10 having a thickness of 25 μm is used as a transfer metal foil for forming the wiring 2.
A three-layer foil composed of a copper layer 12 serving as a wiring layer and a barrier layer 11 between the carrier layer 10 and the copper layer 12 is used. In the figure, two layers 11 and 12 are also shown.

In this example, the patterned copper foils 10-1
19, as shown in FIG.
01 and the top board 1902 at a pressure of 30 kg /
cm ^TwoAnd pressurized. Here, the press upper die 13 and the press
From the drawing, one aluminum foil 1
8, 10 to 12 copper foil with a three-layer pattern
Prepreg 1905, 1906 and thickness 35 μm
Are placed.

The projection of the upper press die 13 has a trapezoidal cross section, and the side surface has a slope angle of 30 degrees.
The prepreg 1906 is provided with a window at a portion corresponding to the protrusion of the upper press die 13 and is arranged on the second sheet from the top.

Further, the manufacturing method of this embodiment is not limited to the example shown in FIG. 19, and may be configured as shown in FIG. 20, for example.

That is, the patterned copper foils 10 to 12
With a hot plate 1901 and a top board 1 at a temperature of 190 ° C.
902, and heated and pressed at a pressure of 20 kg / cm ² .
Here, a three-layer structure including, from the top, three aluminum foils 18 and a copper foil 10 having a thickness of 35 μm between a press upper die 13 and a press lower die 17 in which the inclination angle of the side surface of the protrusion is 45 degrees. Foil 10 to 12, one windowed prepreg 1906, plural prepregs 1905, and copper foil 1 having a thickness of 35 μm
6 is arranged.

According to the manufacturing method shown in FIG. 20, it is possible to manufacture a semiconductor device having a concave portion on the wall surface having a gentle inclination angle as shown in FIG.

The semiconductor device mounting substrate of the present invention is shown in FIG.
(A) In a semiconductor element mounting substrate provided with a concave portion as shown in FIG. 22 (b), a wiring is provided along the surface of the substrate and the substrate wall surface of the concave portion.
An external connection terminal portion connected to an external connection terminal provided on the surface of the substrate on the side where the concave portion opens, an inner connection terminal portion connected to the mounted semiconductor element, the external connection terminal portion, and the inner And a wiring portion between the connection terminal portion, wherein the wiring is embedded in the substrate surface and the substrate wall surface of the recess, the inner connection terminal portion is located in the recess. Semiconductor device mounting substrate.

In FIG. 21 (a) and FIG.
Is an insulating substrate, and 2 is a wiring embedded and formed in the substrate surface and the substrate wall surface of the concave portion. In the substrate for mounting a semiconductor element of FIG. 21A, a through hole is formed at the center of the concave portion. A semiconductor device using this substrate is shown in FIG.
Shown in In FIG. 21B, reference numeral 1 denotes a semiconductor element mounted in a state of being bonded to a substrate, 4 denotes a sealing resin, and 5 denotes an external connection terminal. An inner connection terminal portion of the wiring is formed in the substrate concave portion, and is sealed with a resin. This substrate can be manufactured by the method described above.

In the substrate for mounting a semiconductor element shown in FIG. 22A, the concave portions are formed at both ends, and the substrate can be manufactured by manufacturing a large number of the above-described substrates and cutting them at the concave portions. A semiconductor device using this substrate is shown in FIG.
(B). In FIG. 22B, reference numeral 1 denotes a semiconductor element mounted with a substrate bonded thereto, 4 denotes a sealing resin,
Is an external connection terminal. Inner connection terminal portions of the wiring are formed in the concave portions at both ends of the substrate, and are sealed with resin.

In the present invention, a large number of semiconductor element mounting substrates can be manufactured, that is, a large number can be manufactured by collective pressing.

FIG. 23 is a cross-sectional view showing a press structure showing a process of manufacturing a semiconductor element mounting substrate in a multi-cavity manufacturing. 13 is a press upper die on which many concave dies 13a are formed,
17 is a press lower die, 10 is a copper foil on which a large number of sets of wirings are formed, and 14 is a prepreg.

In the press configuration shown in FIG. 23, when heating and pressing are performed between the upper mold and the lower mold, a large number of convex molds 1 arranged vertically and horizontally are arranged.
With 3a, a large number of recesses can be formed at the same time, and at the same time, the wiring 12 is continuously formed from the external connection terminal portion on the substrate surface to the inner connection terminal portion in the recess through the wall surface of the recess. In this case, the external connection terminal portions on the substrate surface can receive the tension for forming adjacent recesses evenly, and can maintain the position of the plane before pressing with high accuracy (high dimensional stability). That is, by forming a large number of the semiconductor element mounting boards of the present invention, the concave portion can be formed without causing a positional shift between the external connection terminal portion and the position of the flat surface before pressing. Keeping the position of the external connection terminal portion formed on the surface of the substrate in the plane before pressing facilitates the positioning operation when a solder resist is formed at a position other than the portion where the external connection terminal is formed on the external connection terminal portion. . On the outermost side, a dummy convex 13b may be provided around the entire periphery of the upper die 13. The dummy protrusions 13b not only prevent displacement of the external connection terminal portion of the outermost substrate, but also prevent resin flow of the prepreg. 7 × 7 for multi-cavity
The above is preferred.

[0131]

As described above, according to the present invention, a press upper die having a large number of protrusions arranged uniformly in the vertical and horizontal directions, a wiring structure comprising predetermined wiring aligned with the protrusions and a carrier metal foil. A step of preparing a press structure including a body, a prepreg, and a press lower die, by pressing between a press upper die and a press lower die, forming a large number of recesses in a pressed prepreg substrate at the same time and forming the predetermined wiring Embedding into the surface of the substrate and the concave wall surface of the concave portion, removing the carrier metal foil, mounting a semiconductor element, resin sealing the concave portion, forming external connection terminals, cutting into individual pieces A semiconductor device can be manufactured by the step of separating.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a sectional configuration of a semiconductor package according to the present invention.

FIG. 2 is a cross-sectional view showing another example of a cross-sectional configuration of a semiconductor package according to the present invention.

FIG. 3 is a sectional view showing an example of a sectional structure of a semiconductor package according to the present invention on which a plurality of semiconductor elements are mounted.

FIG. 4 is a sectional view showing an example of a sectional structure of a semiconductor package according to the present invention having a high heat dissipation function.

FIG. 5 is a cross-sectional view showing an example of a cross-sectional structure of a drawable wiring structure composed entirely of metal.

FIG. 6 is a cross-sectional view showing another example of a cross-sectional structure of a drawable wiring structure made entirely of metal.

FIG. 7 shows a material composition at the time of molding press;
It is explanatory drawing which shows the example which used the nonwoven fabric prepreg in the structure.

FIG. 8 shows a material configuration at the time of molding press;
It is explanatory drawing which shows the example using the structure which hollowed out the prepreg.

FIG. 9 is a diagram illustrating a material configuration at the time of forming press for a high heat radiation structure, and is an explanatory diagram illustrating an example in which a metal plate is used on a back surface.

FIG. 10 is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 11 is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 12 is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 13 is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view showing another example of the method of manufacturing a semiconductor device (press configuration) according to the present invention.

FIG. 15 is a cross-sectional view showing another example of the method for manufacturing a semiconductor device (press configuration) according to the present invention.

FIG. 16 is a cross-sectional view showing another example of the method for manufacturing a semiconductor device (press configuration) according to the present invention.

FIG. 17 is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 18 is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 19 is a cross-sectional view showing another example of the method of manufacturing a semiconductor device (press configuration) according to the present invention.

FIG. 20 is a cross-sectional view showing another example of the method for manufacturing a semiconductor device (press configuration) according to the present invention.

FIG. 21 (a) is a cross-sectional view showing another example of the semiconductor element mounting substrate according to the present invention. FIG. 21B is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 22A is a cross-sectional view showing another example of the semiconductor element mounting substrate according to the present invention. FIG. 22B is a sectional view showing another example of the semiconductor device according to the present invention.

FIG. 23 is a cross-sectional view showing a method (press configuration) of manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element (chip), 2 ... Wiring, 3 ... Wire, 4
... sealing resin, 5 ... external electrode, 6 ... surface insulating layer, 7 ... insulating substrate, 8 ... metal plate.

[Procedure amendment]

[Submission date] September 22, 2000 (2009.2)
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (37)

[Claims] 1. A semiconductor device in which a recess is formed in a substrate for mounting a semiconductor element, a semiconductor element is mounted in the recess, and then sealed with a sealing resin. An external connection terminal portion connected to an external connection terminal provided on the surface of the substrate on the side where the concave portion opens, comprising: a wiring disposed along a substrate wall surface of the concave portion;
An inner connection terminal portion connected to the mounted semiconductor element; and a wiring portion between the external connection terminal portion and the inner connection terminal portion, wherein the wiring is formed on the substrate surface and the recessed substrate. A semiconductor device embedded in a wall surface, wherein the inner connection terminal portion is located in the concave portion. 2. The semiconductor device according to claim 1, wherein the substrate wall surface of the recess has a slope extending in the direction of the bottom surface of the recess within a predetermined inclination angle range. 3. An inclination angle of the substrate wall surface of the concave portion is 5 to 40.
3. The semiconductor device according to claim 2, wherein the temperature is within a range of degrees. 4. The ratio L / G between the height G of the inclined structure on the substrate wall surface of the recess and the horizontal distance L is 1.5 <L / G <10.
3. The semiconductor device according to claim 2, wherein 5. The semiconductor device according to claim 1, wherein said concave portion is formed by convex press molding. 6. The semiconductor device according to claim 1, wherein said recess is formed in a plurality of steps. 7. The semiconductor device according to claim 5, wherein said recess is provided with a semiconductor element accommodation portion for accommodating a semiconductor element formed by further counterboring said recess. 8. The semiconductor device according to claim 7, wherein the depth of the counterbored semiconductor element housing is larger than the thickness of the semiconductor element to be mounted. 9. The semiconductor device according to claim 1, wherein a step between the external connection terminal located on the substrate surface and the inner connection terminal in the recess is 0.05 mm or more. 10. The semiconductor device according to claim 1, wherein the terminal of the semiconductor element mounted in the recess and the inner connection terminal are wire-bonded. 11. The semiconductor device according to claim 1, wherein a terminal of the semiconductor element is directly connected face-down to said inner connection terminal portion. 12. The semiconductor device according to claim 1, wherein said wiring is provided in a wall surface region excluding a corner of said concave portion. 13. The semiconductor device according to claim 13, wherein the recess is formed at a substantially center position of a main plane of the substrate, and a semiconductor element is mounted in the recess so as to be substantially at a center with respect to a thickness direction of the substrate for mounting the semiconductor element. The semiconductor device according to claim 1, wherein: 14. The semiconductor device according to claim 1, wherein a semiconductor element is mounted in said recess so as to be offset within 30% of a thickness of said substrate from a center in a thickness direction of said substrate. apparatus. 15. The semiconductor device according to claim 15, wherein the recess has a width enough to accommodate a plurality of devices in a bottom surface region, and wiring to the plurality of devices is formed. 2. The device according to claim 1, wherein the device is mounted.
13. The semiconductor device according to claim 1. 16. The wiring according to claim 16, wherein the wiring is entirely made of metal.
The drawable wiring structure is formed using a drawable wiring structure. The drawable wiring structure is a first metal layer forming the wiring and a second metal layer functioning as a carrier layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer structure including at least the following. 17. A semiconductor element mounting substrate having a concave portion for mounting a semiconductor element, comprising: wiring arranged along a surface of the substrate and a substrate wall surface of the concave portion, wherein the wiring has an opening in the concave portion. An external connection terminal portion connected to an external connection terminal provided on the surface of the substrate on the side;
An inner connection terminal portion connected to the mounted semiconductor element; and a wiring portion between the external connection terminal portion and the inner connection terminal portion, wherein the wiring is formed on the substrate surface and the recessed substrate. A semiconductor element mounting substrate embedded in a wall surface, wherein the inner connection terminal portion is located in the concave portion. 18. The semiconductor device to be mounted, wherein the depth of the recess is smaller than the thickness of the semiconductor device to be mounted, and the bottom surface of the recess is to be mounted from the center in the thickness direction of the semiconductor device mounting substrate. 18. The substrate for mounting a semiconductor element according to claim 17, wherein the substrate is counterbored to a depth within a range of 0.5 to 2.5 times the thickness of the semiconductor element. 19. The concave portion has a depth smaller than the thickness of the semiconductor element to be mounted, and has a counterbore processing applied to the bottom surface of the concave portion, so that at least the exposed counterbore bottom surface is made of a nonwoven fabric. The substrate for mounting a semiconductor element according to claim 17, further comprising a resin layer formed by curing a prepreg. 20. A back surface of the resin layer in which the concave portion is formed,
18. The substrate for mounting a semiconductor element according to claim 17, wherein the substrate is formed by bonding a metal plate. 21. An all-metal drawable wiring structure having a multilayer structure including at least a first metal layer and a second metal layer functioning as a carrier layer thereof is pressed against a resin substrate. At the same time, the recess is formed on the resin substrate with a wall having a slope within a predetermined inclination angle range, and the other metal layer is removed while leaving the first metal layer. An external connection terminal connected to an external connection terminal provided on the surface of the substrate on an opening side, an inner connection terminal connected to a semiconductor element to be mounted, the external connection terminal and the inner connection terminal; A wiring embedded in the substrate surface and the substrate wall surface of the concave portion, the wiring being configured from the substrate surface along the substrate wall surface of the concave portion. Manufacturing method of mounting substrate. 22. The method for manufacturing a semiconductor element mounting substrate according to claim 21, wherein the elongation at break of the drawable wiring structure is 2% or more. 23. The carrier layer constituting the drawable wiring structure has a thickness of 0.010 mm to 0.05 mm.
22. The method according to claim 21, wherein the distance is in a range of 0 mm. 24. The inclination angle range of the substrate wall surface of the concave portion is 5
22. The method according to claim 21, wherein the depth is not less than 40 degrees and not more than 40 degrees, and the depth of the recess is not less than 30% of the thickness of the semiconductor element to be housed. 25. A method of manufacturing a semiconductor element mounting substrate comprising a recess for mounting a semiconductor element and wiring, wherein the depth of the recess is smaller than the thickness of the semiconductor element to be mounted, and In the counterbore processing, a part of the wiring to the mounted semiconductor element is cut, and the end of the wiring reaches the edge of the recess formed by the counterbore. A method for manufacturing a substrate for mounting a semiconductor element, comprising: 26. The semiconductor element mounting according to claim 21, wherein after forming the concave portion, a counterboring process is performed on a bottom surface of the concave portion, and after the counterboring process, the other metal layer is removed. Method of manufacturing substrates. 27. The substrate for mounting a semiconductor element according to claim 17, wherein a substrate wall surface of said concave portion has a gradient extending in a direction of a bottom surface of said concave portion within a predetermined inclination angle range. 28. An inclination angle of the substrate wall surface of the concave portion is 5-4.
28. The substrate for mounting a semiconductor element according to claim 27, wherein the angle is within a range of 0 degrees. 29. The height G of the inclined structure of the substrate wall surface of the concave portion
And the ratio L / G of the horizontal distance L is 1.5 <L / G <1.
28. The substrate for mounting a semiconductor element according to claim 27, wherein the value is within a range of 0. 30. The substrate for mounting a semiconductor element according to claim 17, wherein said concave portion is formed by convex press molding. 31. The substrate for mounting a semiconductor element according to claim 17, wherein said recess is formed in a plurality of steps. 32. A semiconductor device accommodating portion for accommodating a semiconductor element formed by further counterboring the concave portion, wherein the concave portion is provided.
The substrate for mounting a semiconductor element according to the above. 33. The semiconductor element mounting substrate according to claim 32, wherein the depth of the counterbored semiconductor element housing portion is larger than the thickness of the semiconductor element to be mounted. 34. The semiconductor element mounting device according to claim 17, wherein a step between said external connection terminal portion on said substrate surface portion and said inner connection terminal portion in said concave portion is 0.05 mm or more. substrate. 35. A press upper die having a number of protrusions arranged uniformly in the vertical and horizontal directions, a wiring structure comprising a predetermined wiring aligned with the protrusions and a carrier metal foil, a prepreg, and a press lower die. A step of preparing a press configuration including: pressing between a press upper die and a press lower die to simultaneously form a large number of recesses on a substrate that is a pressed prepreg, and connect the predetermined wiring to the substrate surface and the recesses. Embedding in a substrate wall, removing the carrier metal foil, mounting a semiconductor element, resin-sealing the concave portion, forming an external connection terminal, and cutting and separating into individual pieces. A method for manufacturing a semiconductor device. 36. The method of manufacturing a semiconductor device according to claim 35, wherein a dummy projection is formed on the periphery of the upper press die. 37. A semiconductor element mounting substrate having a concave portion, comprising: wiring arranged along the substrate surface and the substrate wall surface of the concave portion, wherein the wiring is provided on the substrate surface on the side where the concave portion opens. An external connection terminal connected to the external connection terminal
An inner connection terminal portion connected to the mounted semiconductor element; and a wiring portion between the external connection terminal portion and the inner connection terminal portion, wherein the wiring is formed on the substrate surface and the recessed substrate. A semiconductor element mounting substrate embedded in a wall surface, wherein the inner connection terminal portion is located in the concave portion.