JP2001127126A - Method of evaluating semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply a normal test voltage to another silicon oxide films even when dielectric breakdown occurs in one of silicon oxide films. SOLUTION: A plurality of MOS capacitor elements T1, T2,..., Tn are formed on a silicon wafer S. A prescribed dc voltage is applied to the gate electrode G of each of the MOS capacitor elements T1, T2,..., Tn. Also, the silicon wafer 2 is grounded by the contact of a rear-surface contact CP. Then, a prescribed test voltage E is applied to a silicon oxide film M formed between the gate electrode G and the silicon wafer S so that dielectric breakdown is evaluated over time. In this method, resistors R1, R,..., Rn for regulating current are inserted in series into the silicon oxide films M of the respective MOS capacitor elements T1, T2,..., Tn.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a semiconductor device formed on a semiconductor wafer and evaluating the time-dependent dielectric breakdown of a semiconductor oxide film.

[0002]

2. Description of the Related Art For example, in a semiconductor device having a MOS structure, a silicon oxide film (semiconductor oxide film) has an oxide film breakdown voltage (TZDB: Time Zero Dielectric Breakdown) and a time-dependent dielectric breakdown (TDDB: Time Dependent Dielectric).
Breakdown) is evaluated. In the evaluation test of the time-dependent dielectric breakdown, as shown in FIG. 1, a DC voltage of a DC power supply P is applied to a gate electrode G of a MOS capacitor element T formed on a silicon wafer S (semiconductor wafer) via an ammeter A. The silicon wafer S is grounded (GND) by applying and applying the back contact CP, and the DC voltage of the DC power supply P is applied to the silicon oxide film M formed between the gate electrode G and the silicon wafer S. Is the test voltage E
Is applied.

Although FIG. 1 shows only one MOS capacitor element T, a plurality of MOS capacitor elements T, T,... Capacitor elements T, T, ...
The test voltage E is applied to the silicon oxide films M at the same time. After the test voltage E is applied to each silicon oxide film M in this way, the measurement value of each ammeter A is checked at a predetermined time interval, and at which timing the silicon oxide film M of any MOS capacitor element T Whether or not dielectric breakdown has occurred is obtained as evaluation data.

[0004]

The test voltage E is set so as to satisfy a predetermined evaluation criterion. However, if the silicon oxide film M of any of the MOS capacitor elements T breaks down, the test voltage E is set. MOS capacitor element T
Causes a large DC current to flow rapidly. That is, the DC power supply P and GND are connected via the gate electrode G → the silicon oxide film M or the silicon wafer S → the back contact CP.
DC current sharply increases during the period. As a result, a voltage drop occurs in the contact resistance R _CP between the silicon wafer S and the back surface contact CP, so that the potential of the silicon wafer S rises and the other MOS capacitor element T which does not cause dielectric breakdown is generated. There is a problem that a normal test voltage E is not applied to the silicon oxide film M. Therefore, it is not possible to continue a normal evaluation test of dielectric breakdown with time for the silicon oxide film M of the other MOS capacitor element T.

The present invention has been made in view of such a problem, and it is possible to apply a normal test voltage to another silicon oxide film even if dielectric breakdown occurs in one of the silicon oxide films. It is intended to provide a method for evaluating a semiconductor device.

[0006]

In order to achieve the above object, according to the present invention, for a plurality of semiconductor elements formed on a semiconductor wafer, a predetermined DC voltage is applied to a gate electrode of each semiconductor element, and A method of evaluating a dielectric breakdown with time by applying a predetermined test voltage to a semiconductor oxide film formed between the gate electrode and the semiconductor wafer by grounding the wafer by contacting a back surface contact,
A means of interposing a current limiting means in series with the semiconductor oxide film of each semiconductor element is employed. In the above means, a current limiting resistor may be used as the current limiting means.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for evaluating a semiconductor device according to the present invention will be described with reference to the drawings. In the following description, the same components as those already described in the related art are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 is an equivalent circuit of a test apparatus for simultaneously testing a plurality (n) of MOS capacitor elements T1, T2,..., Tn formed on the silicon wafer S (semiconductor wafer). As shown in this figure, in this embodiment, DC power supplies P1, P2,..., Pn and ammeters A1, A2,.
, An are connected in series, respectively, and these DC power supplies P1, P2,..., Pn and ammeters A1, A2,.
A current limiting resistors R1, R2,..., Rn (current limiting means) having the same resistance value are interposed between An and An. That is, each MOS capacitor element T1,
The test voltage E is applied to the silicon oxide film M of T2,..., Tn through current limiting resistors R1, R2,.

In this figure, RG1, RG2,.
, RGn is the resistance of each gate electrode G, RS1, RS2, ...,
RSn is the substrate resistance (that is, the resistance of the silicon wafer S) of each of the MOS capacitor elements T1, T2,.
, Cn are the MOS capacitor elements T1, T
2,..., Tn are capacitors showing the capacitance of the silicon oxide film M (semiconductor oxide film) of Tn. Further, each MOS capacitor element T1, T2,.
The contact resistance R _CP of the back contact _CP is, as shown in FIG.
1, T2,..., Tn are connected in series at the contact a.

Each of the MOS capacitor elements T1 and T1 formed on the silicon wafer S by using such a test apparatus
When evaluating the time-dependent dielectric breakdown of the silicon oxide film M of 2,..., Tn, the DC power supplies P1, P2,..., Pn are simultaneously turned on, and the test voltage E is applied to each gate electrode G. You. That is, the test voltage E is simultaneously applied to the capacitors C1, C2,..., Cn to start the test. The measured values of the ammeters A1, A2,..., An are checked at predetermined time intervals, and at which timing the silicon oxide film M of any of the MOS capacitor elements T1, T2,. Is obtained as evaluation data.

Here, when the silicon oxide film M of any of the MOS capacitor elements breaks down, that is, when any of the capacitors C1, C2,... In the MOS capacitor element of the destroyed silicon oxide film M, a direct current flows from the gate electrode G to the silicon wafer S by rapidly increasing. For example, if the silicon oxide film M of the MOS capacitor element T1 has a dielectric breakdown, the capacitor C1 is broken, the DC current I1 current limiting resistor R1 → ammeter A1 → resistor RG1 → resistor RS1 → R _CP DC power supply P1 and GND
Flows between

[0012] As a result, the voltage drop due to the DC current I1 in contact resistance R _CP occurs, the potential Va of the contact a is increased. However, in the present embodiment, since the current limiting resistor R1 is interposed, the current value of the DC current I1 is suppressed, and the rise of the potential Va is suppressed. Test voltage E
Is provided with a specified value (specified voltage range) having a predetermined width. The resistance value of the current limiting resistor R1 is set so that the test voltage E does not deviate from the specified voltage range due to a decrease due to an increase in the potential Va. Have been.

In the above embodiment, the simplest current limiting means is a current limiting resistor R1, R2,..., Rn.
However, as a circuit means for limiting the direct current, there are various current limiting circuits using a transistor as a current control element in addition to such a resistor. Therefore,
Such current limiting circuits may be used as current limiting means.

[0014]

As described above, according to the semiconductor device evaluation method of the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, since the current limiting means is inserted in series with the semiconductor oxide film of each semiconductor element, it is possible to suppress a DC current flowing when dielectric breakdown of the semiconductor oxide film occurs. It is possible, so that a change in the potential of the semiconductor wafer due to the contact resistance between the semiconductor wafer and the back contact is suppressed. Therefore, a normal test voltage can be continuously applied to another semiconductor oxide film that has not caused dielectric breakdown, that is, the dielectric breakdown with time can be continued for another semiconductor oxide film. (2) According to the second aspect of the present invention, since the current limiting resistor is used as the current limiting means, it is possible to suppress the DC current flowing when the breakdown of the semiconductor oxide film occurs by an extremely simple method. .

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a conventional method for evaluating a semiconductor device.

FIG. 2 is an equivalent circuit showing one embodiment of the present invention.

[Explanation of symbols]

A1, A2, ..., An ... Ammeter CP ... Backside contact C1, C2, ..., Cn ... Capacitor G ... Gate electrode I1 ... DC current P1, P2, ..., Pn DC power supply R1, R2,..., Rn... Current limiting resistors (current limiting means) RG1, RG2,..., RGn... Gate electrode resistances RS1, RS2,. _CP contact resistance S silicon wafer (semiconductor wafer) M silicon oxide film (semiconductor oxide film) T1, T2,..., Tn MOS capacitor element

Claims (2)

[Claims] A plurality of semiconductor elements formed on a semiconductor wafer, wherein a predetermined DC voltage is applied to a gate electrode of each semiconductor element, and the semiconductor wafer is grounded by contacting a back contact. A predetermined test voltage is applied to a semiconductor oxide film formed between the semiconductor oxide film and the semiconductor wafer to evaluate dielectric breakdown with time, and a current limiting means is inserted in series with the semiconductor oxide film of each semiconductor element. A method for evaluating a semiconductor device, comprising: 2. The method according to claim 1, wherein a current limiting resistor is used as the current limiting means.