JP2001119695A - Device for reducing block noise - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a block noise reducing device with a simple configuration. SOLUTION: An isolated differential point extraction circuit 1 performs differential processing of an input video signal, subsequently outputs isolated differential data at an isolated differential point, and a filter circuit 2 generates correction data, on the basis of it. Then, an adder 4 performs addition processing of a signal obtained by delaying the input image signal for a prescribed time and the correction data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block noise reduction apparatus for reducing block noise generated when encoding and decoding a video signal in pixel block units.

[0002]

2. Description of the Related Art When a video signal is compression-coded, a plurality of pixels adjacent in the horizontal and vertical directions are regarded as one rectangular block (hereinafter, referred to as a pixel block), and the correlation between adjacent pixels in the pixel block is determined. There is widely known a compression encoding system that performs compression encoding in units of pixel blocks using the height of the image data. After passing through a recording medium or a transmission path, a compressed video signal that has been compression-encoded by such a compression encoding method is subjected to a decoding process complementary to that at the time of encoding in units of pixel blocks, The original video signal is restored.

[0003] In such a compression encoding and decoding method, when it is desired to reduce the information amount of a video signal on a recording medium or a transmission path, the compression ratio is set to a high value, and the video signal is set to a high quality. If you want to keep it
The compression ratio is set lower.

[0004] However, when the compression ratio is set to be high and the amount of information is kept small, a gradation difference may occur between pixel blocks and adjacent blocks. In particular, in a video signal portion having a gradual gradation change, the gradation difference between adjacent blocks becomes more noticeable. Note that such noise due to the gradation difference between adjacent blocks is generally called block noise.

[0005] Further, in a video signal reproduced through a recording medium, block noise may be generated due to, for example, contamination or wear of the recording / reproducing head. Easy to see on screen. As a method for reducing such block noise generated on a screen, a method described in Japanese Patent Application Laid-Open No. HEI 3-17491 or Japanese Patent Application Laid-Open No. HEI 8-149470 has been devised.

[0006]

However, in the above-described block noise reduction method, there is a problem that the circuit scale becomes very large in any of the methods.

[0007]

SUMMARY OF THE INVENTION In order to solve the above problems, a block noise reduction apparatus according to the present invention provides a block for reducing block noise in a video signal compressed and decompressed in units of predetermined rectangular blocks. A noise reduction device for performing differential processing on an input video signal to obtain a differential signal and extracting and outputting an isolated differential point in the differential signal; and performing a filtering process on an output of the isolated differential point extracting means. Filter means for outputting a correction signal for correcting a signal level difference at a boundary between a rectangular block in which block noise has occurred and an adjacent block; delay means for delaying the input video signal by a predetermined time; And an adding means for adding the output of the delay means to the output of the delay means.

[0008] The block noise reduction apparatus according to the present invention further comprises block noise detection means for detecting the amount of block noise in frame units based on the output of the isolated differential point extraction means, and the block noise detection means detects the amount of block noise. The on / off of the block noise reduction processing is switched according to the amount of block noise that has been performed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining a block noise reduction apparatus according to the present invention. Reference numeral 1 denotes an isolated image which performs a differentiation process on an input video signal and extracts and outputs an isolated differential point in the differentiated signal. A differential point extracting circuit, 2 is a filter circuit for filtering the output of the isolated differential point extracting circuit 1, 3 is a delay circuit for delaying an input video signal by a predetermined time and output, and 4 is an output of the filter circuit 2. And an output of the delay circuit 3.

FIG. 2 is a diagram for explaining an example of a method of extracting an isolated differential point in the isolated differential point extraction circuit 1, and FIG. 3 is a diagram showing an example of a configuration of the filter circuit 2. In the isolated differential point extraction circuit 1, impulse data is obtained by applying a logical filter to the differential signal obtained by performing the differential processing as shown in the figure. That is, the differential values of adjacent pixels in the input video signal are compared with each other, and only the differential value protruding from the adjacent pixel is output as an isolated differential point. In the case of FIG. 2, only the prominent value c is output.

On the other hand, as shown in FIG. 3, the filter circuit 2 includes a plurality of delay elements 2a to 2d and two delay elements 2a to 2d for delaying the output of the isolated differential point extraction circuit 1 by one pixel and outputting the result.
Multiplier 2 which outputs a predetermined weight to the output of
e to 2f, the output of the isolated differential point extraction circuit 1 and the multiplier 2e
Adders 2i that add and output all the outputs of
It comprises a 1/6 processing circuit 2j for converting the output of the adder 2i to a 1/6 value and outputting it.

The delay amount of the delay circuit 3 is set so that the input video signal is delayed by two pixels and output, and the timing with the output of the filter circuit 2 is adjusted. The output of the filter circuit 2 and the delay circuit 3
Are added by the adder 4.

Hereinafter, the operation of the block noise reduction device shown in FIG. 1 will be described with reference to the waveform diagram shown in FIG.
In the figure, (a) is the input video signal, (b) is the output of the isolated differential point extraction circuit 1, (c) is the output of the filter circuit 2,
(D) shows the output of the delay circuit 3, and (e) shows the output of the adder circuit 4. In this block noise reduction device,
In the case where a gradation difference, that is, block noise occurs at a block boundary between adjacent blocks as shown in (a), the steep step is smoothed to generate a video signal in which block noise is hardly noticeable. It is intended to be. Although the video signal actually input to the isolated differential point extraction circuit 1 is a digital signal, the description will be made using an analog waveform for easy understanding.

When video data having a gradation difference as shown in FIG. 4A is input to the isolated differential point extraction circuit 1, the isolated differential point extraction circuit 1 extracts a differential signal therein, and As described above, only the differential value protruding from an adjacent pixel is output as an isolated differential point by the logical filter.

That is, when the value of | cd | is larger than the value of | de | and the value of | bc | is larger than the value of | ab |, b ≦ c ≦ d and If neither b ≧ c ≧ d, the value of c at that time is output. The isolated differential point extraction circuit 1 outputs a value of 0 in other states. In addition,
The method of extracting isolated differential points is not limited to this method.
It goes without saying that other methods may be used.

The isolated differential data output from the isolated differential point extraction circuit 1 is input to the filter circuit 2 as shown in FIG. As shown in FIG. 3, a plurality of delay elements 2a to 2d are provided in the filter circuit 2, and the output of each pixel output from the isolated differential point extraction circuit 1 is sequentially delayed by each delay element. Each of the isolated differential data corresponding to the five pixels is weighted in a predetermined manner.

That is, the output of the delay element 2a has a value of 2,
The output of the delay element 2b is multiplied by a value of 3, the output of the delay element 2c is multiplied by a value of (-2), and the output of the delay element 2d is multiplied by a value of (-1). Give weight. Then, after the output of the isolated differential point extraction circuit 1, the output of the multiplier 2e, the output of the multiplier 2f, the output of the multiplier 2g, and the output of the multiplier 2h are added by the adder 2i, the 1/6 processing circuit 2j By reducing the output value to 1/6, correction data is obtained as shown in FIG.

On the other hand, the delay circuit 3 outputs video data as shown in FIG. 4D obtained by delaying the video data shown in FIG. 4A by two pixels, and the adder circuit 4 outputs the video data shown in FIG.
The video data is output as shown in FIG. 4E obtained by adding the correction data as shown in FIG. 4C and the video data as shown in FIG. 4D.

As described above, in the noise reduction device according to the present invention, the correction circuit that generates the gradation difference at the block boundary of the input video signal is generated by the filter circuit 2 and added to the input video signal. The steep steps at the block boundaries are smoothed.

Next, another embodiment of the noise reduction device according to the present invention will be described. FIG. 5 is a block diagram for explaining a block noise reduction device according to another embodiment. For the same configuration as the block noise reduction device shown in FIG.
The same reference numerals are given and the description thereof is partially omitted.

In the block noise reduction device shown in FIG. 5, a block noise detection circuit 5 and a switch 6 are provided between the isolated differential point extraction circuit 1 and the filter circuit 2. The input of the switch 6 is switched according to the detection result, and the on / off of the block noise reduction processing is switched.

FIG. 6 is a block diagram showing an example of the block noise detection circuit 5, which detects block noise by utilizing the fact that isolated differential points due to block noise have high correlation in the horizontal and vertical directions. . Here, the isolated differential data output from the isolated differential point extraction circuit 1 is input to a first comparator 5a, and the first comparator 5a compares the specified value held therein with the isolated differential data. If the isolated differential data is larger than the specified value, a value of 1 is output. If the isolated differential data is smaller than the specified value, a value of (−1) is output.

The output of the first comparator 5a is input to the adder 5b, and the output of the first comparator 5a is added to the value obtained by delaying the output of the adder 5b by 16 pixels by the delay element 5c. You. That is, in the block noise detection circuit shown in FIG.
When one pixel block is composed of a total of 256 pixels, or a macro block is formed by arranging two pixel blocks each composed of a total of 64 pixels of 8 pixels in the horizontal direction and 8 pixels in the vertical direction in the horizontal and vertical directions. The delay element 5c
Is set to 16 pixels.

When the output of the adder 5b is equal to or more than a certain value, the first limiter 5d outputs the value while providing a predetermined upper limit value, and the second comparator 5e outputs the value. The output of the limiter 5d is compared with a specified value held therein, and the value of 1 is output when the output of the first limiter 5d is larger than the specified value, and the value of (-1) is output when the output of the first limiter 5d is smaller than the specified value. I do. By the processing up to the second comparator 5e, the number of places where the gradation difference of the video signal generated in one horizontal line is large in 16 pixel cycles is added in the horizontal direction, and the correlation of the horizontal direction is reduced. An integrated value of a certain isolated differential point is output.

Next, the output of the second comparator 5e is input to the adder 5f, and the output of the adder 5f is changed to 1 by the delay element 5g.
The value delayed by the horizontal line period and the second comparator 5
The output of e is added. In this manner, the output of the second comparator 5e is delayed by one horizontal line period to perform integration in the vertical direction, and the output of the adder 5f is input to the second limiter 5h.

When the output of the adder 5f is equal to or more than a certain value, the second limiter 5h outputs the value while providing a predetermined upper limit, and the third comparator 5i outputs the value of the second limiter 5h. Of the second limiter 5h is larger than the specified value, and the value of (-1) is output when the output of the second limiter 5h is smaller than the specified value. By the processing up to the third comparator 5i, the number of places where the gradation difference of the video signal generated in the vertical direction in one screen is large is cumulatively added in the vertical direction, and the correlation is made in both the horizontal and vertical directions. The integrated value of the isolated differential point with is output.

The counter 5j is connected to the third comparator 5
By counting the output of i and outputting the count number for each screen, the number of isolated differential points occurring in one screen and having a correlation in both the horizontal and vertical directions is output. The output of the counter 5j is output after being delayed by one screen (frame) by the delay element 5k, and further delayed by one screen (frame) by the delay element 5m.

In this way, the count values for three screens (frames) are input to the median circuit 5n, and the intermediate value among the three values is output to the fourth comparator 5p. And
The fourth comparator 5p outputs a value of 1 when the output value of the median circuit 5n is larger than a specified value, and outputs a value of 0 when the output value is equal to or smaller than the specified value. The output signal controls the switch 6.

That is, while the block comparator has a large amount of block noise and the fourth comparator 5p outputs a value of 1, the switch 6 selects and outputs the isolated differential data from the isolated differential point extracting circuit 1 and outputs the isolated differential data in frame units. During a period in which the block noise is small and the fourth comparator 5p outputs a value of 0, the switch 6 outputs a 0-level signal, and as a result, the block noise reduction processing is turned off.

In the block noise reduction circuit according to this embodiment, the output of the counter 5j is not input to the fourth comparator 5p, but the intermediate value of the counter values for three frames is input to the comparator 5p. For example, even when the video signal is an MPEG compression signal for performing inter-frame compression, the switch 6 can be favorably switched.

That is, when an intra-frame compressed image exists once in a plurality of frames as in the case of an MPEG compressed signal, block noise is low only in the intra-frame compressed image, and block noise is low in other frames by inter-frame compression. May occur frequently. In such a case, by providing a small hysteresis characteristic, it is possible to prevent chattering in which the switch 6 is frequently switched. By performing such switching of the switch 6, it is possible to accurately and stably reduce the block noise.

As described above, according to the block noise reduction device according to the present embodiment, by switching the switch 6, the block noise reduction processing is performed on the frame with much block noise, and the frame with little block noise is processed. In addition, since the block noise reduction processing is not performed, image quality deterioration due to the block noise reduction processing can be minimized.

Further, since the switch 6 is prevented from being frequently switched, the frame subjected to the block noise reduction processing and the frame not subjected to the block noise reduction processing are not frequently switched, so that the frame is more stable. The obtained video signal can be obtained.

[0034]

According to the present invention, an isolated differential point is extracted from an input video signal, and a correction signal for correcting a signal level difference at a block boundary is generated using the data of the isolated differential point. Since a steep step at a block boundary is removed based on the above, there is an effect that a block noise reduction device can be provided with a simple configuration.

In addition, since block noise reduction processing is performed on a frame having a large amount of block noise, and block noise reduction processing is not performed on a frame having a small amount of block noise, deterioration in image quality due to the block noise reduction processing is minimized. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a block noise reduction device according to the present invention.

FIG. 2 is a diagram illustrating an example of an isolated differential point extraction method in an isolated differential point extraction circuit.

FIG. 3 is a diagram illustrating an example of a configuration of a filter circuit.

FIG. 4 is a diagram for explaining signal waveforms output by each component of the block noise reduction device according to the present invention.

FIG. 5 is a block diagram illustrating a block noise reduction device according to another embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a block noise detection circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 isolated differential point extraction circuit 2 filter circuits 2 a to 2 d, 5 c, 5 g, 5 k, 5 m delay elements 2 e to 2 h multiplier 2 i adder 2 j 1/6 processing circuit 3 delay circuit 4 addition circuit 5 Block noise detection circuit 5a, 5e, 5i, 5p Comparator 5d, 5h Limiter 5n Median circuit 5j Counter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C021 PA32 PA36 PA38 PA53 PA58 PA62 PA66 PA67 PA75 PA76 PA87 RA06 RB05 RB07 RB08 SA22 SA25 YA01 YC08 5C059 KK03 MA00 MA05 PP05 PP06 PP07 TA68 TA69 TB04 TB08 TC01 TC10 TC33 TD05 TD12

Claims (2)

[Claims] 1. A block noise reduction device for reducing block noise in a video signal that has been compressed and decompressed in units of predetermined rectangular blocks, wherein the differential signal is obtained by differentiating an input video signal to obtain a differential signal. An isolated differential point extracting means for extracting and outputting an isolated differential point, and performing a filter process on an output of the isolated differential point extracting means to obtain a signal level difference at a boundary between a rectangular block in which block noise is generated and an adjacent block. Filter means for outputting a correction signal to be corrected; delay means for delaying the input video signal for a predetermined time; and addition means for adding the output of the filter means and the output of the delay means. Block noise reduction device. 2. The image processing apparatus according to claim 1, further comprising: a block noise detecting unit configured to detect an amount of block noise in a frame unit based on an output of the isolated differential point extracting unit, wherein a block is provided in accordance with the amount of block noise detected by the block noise detecting unit. 2. The block noise reduction device according to claim 1, wherein on / off of the noise reduction processing is switched.