JP2001118843A - Integrated circuit and process for depositing high-aspect ratio functional gap fill thereof - Google Patents

Integrated circuit and process for depositing high-aspect ratio functional gap fill thereof

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Publication number
JP2001118843A
JP2001118843A JP2000242829A JP2000242829A JP2001118843A JP 2001118843 A JP2001118843 A JP 2001118843A JP 2000242829 A JP2000242829 A JP 2000242829A JP 2000242829 A JP2000242829 A JP 2000242829A JP 2001118843 A JP2001118843 A JP 2001118843A
Authority
JP
Japan
Prior art keywords
integrated circuit
low
dielectric
deposited
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000242829A
Other languages
Japanese (ja)
Inventor
Mahjoub Ali Abdelgadir
アリ アブデルガディル マジャブ
Sakusena Bibekku
サクセナ ビベック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
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Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of JP2001118843A publication Critical patent/JP2001118843A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an extra large-scale integrated circuit having a high aspect ratio function by using a technology for forming low-k dielectric ILDs having such an integrated circuit structure that avoids the harmful trend of high density plasma enhanced CVD (HDP-CVD) and, at the same time, reduces the occurrence of voids; a process for depositing a low-k dielectric material in the extra large- scale integrated circuit; and an integrated circuit manufactured by using the process. SOLUTION: An integrated circuit manufacturing technology by which a protective layer is deposited on the conductive elements of a specific layer in a multilayered integrated circuit is disclosed. A low-k dielectric layer is deposited on a protective film forming material layer by, preferably, HDP-CVD. The disclosed process fills up the gap of <300 nm between metallic functions with a high aspect ratio conductive function (>=3). By means of the fluorine embodied in the embodiment, the interline capacitance CL-L of the low-k dielectric film is reduced by 10% as compared with the conventional non-doped dielectric material.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は集積回路の製造工程
およびその集積回路に係わり、特に高アスペクト比機能
を有する超大規模集積回路、大集積回路に低−ｋ誘電体
材料を堆積工程およびこれを用いて製造される集積回路
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit manufacturing process and an integrated circuit, and more particularly to an ultra-large scale integrated circuit having a high aspect ratio function, a process of depositing a low-k dielectric material on a large integrated circuit, and a method of manufacturing the same. The present invention relates to an integrated circuit manufactured using the same.

【０００２】[0002]

【従来の技術】集積回路の小型化や集積化する技術的挑
戦に合わせて、機能サイズの減少やラインスペースの低
減がなされている。そのような挑戦のひとつは、層間
（または、ライン間）キャパシタンス（ＣＬ−Ｌ）を最
小にし、導電体間に適当なギャップフィルを設けること
である。キャパシタンスは導電体間に存在する材料の誘
電率と直接比例しているので、集積回路の層間誘電体
（ＩＬＤ）として用いられる材料の誘電率を減少させる
と、導電体間の寄生キャパシタンスを減じることができ
る。フッ素ドープ二酸化けい素（ＳｉＯＦ）フィルム、
例えば、フッ化珪素ガラス（ＦＳＧ）が、しばしば、低
誘電率（低−ｋ）ＩＬＤとして使用される。小型化と集
積化の別の技術的挑戦は、機能間にボイドが発生するの
を減少させることである。その隣接する機能の距離に対
する機能の高さの比（アスペクト比として知られてい
る）がかなりのものになるとき、このことは特に本当で
ある。多くの堆積技術では、隣接する機能（ギャップフ
ィリング）間のギャップを埋めることは困難であり、し
ばしば機能間にボイドが生じる。層間誘電体（ＩＬＤ）
のボイドは、ボイド内に不純物を捕獲するのを止めて、
信頼性の問題をもたらすばかりでなく、次の平坦化ステ
ップや他の工程中にボイドが開放されると、金属ライン
で破壊が発生することになる。2. Description of the Related Art In response to the technical challenge of miniaturization and integration of integrated circuits, the function size and line space have been reduced. One such challenge is to minimize interlayer (or line-to-line) capacitance (CL-L) and provide adequate gap fill between conductors. Since capacitance is directly proportional to the dielectric constant of the material present between conductors, reducing the dielectric constant of the material used as the interlevel dielectric (ILD) of an integrated circuit will reduce the parasitic capacitance between the conductors Can be. Fluorine-doped silicon dioxide (SiOF) film,
For example, silicon fluoride glass (FSG) is often used as a low dielectric constant (low-k) ILD. Another technical challenge of miniaturization and integration is to reduce the occurrence of voids between functions. This is especially true when the ratio of the height of a feature to the distance of its neighboring features (known as the aspect ratio) becomes significant. With many deposition techniques, it is difficult to fill the gap between adjacent features (gap filling), and voids often occur between features. Interlayer dielectric (ILD)
Void stops capturing impurities in the void,
In addition to introducing reliability issues, opening the voids during the next planarization step or other process will cause breakage in the metal lines.

【０００３】[0003]

【発明が解決しようとする課題】従って、ギャップフィ
リングを行うことにより、ボイドの発生を減少できるこ
とを保証することが要求されている。層間誘電体のギャ
プフィル能力を高める技術の一つは、高密度プラズマ化
学気相堆積（ＨＤＰ−ＣＶＤ）である。ＨＤＰ−ＣＶＤ
は、プラズマを発生させ、ウェーハに材料を堆積する技
術である。ＨＤＰ−ＣＶＤは、スパッタリング構成要素
を有し、プラズマの存在により発生し、また、 ＨＤＰ
−ＣＶＤはｒｆバイアスにより活性化され、ウェーハに
応用される。そして、ＨＤＰ−ＣＶＤは、低温堆積能力
と良好なギャップフィル能力のような一定の利点を持っ
ており、ＨＤＰ−ＣＶＤは、誘電体材料の堆積工程中に
スパッタリングをし、金属をエッチング（このようなス
パッタリングと金属をエッチングはしばしばクリピング
といわれる）することができる。従って、必要なもの
は、上述した従来のＨＤＰ−ＣＶＤの有害な傾向を避け
ると同時に、ボイド（よいギャップフィル）の発生を減
じる集積回路構造の低−ｋ誘電体ＩＬＤｓを形成する技
術である。Accordingly, there is a need to ensure that void filling can be reduced by performing gap filling. One technique for increasing the gapfill capability of interlayer dielectrics is high density plasma chemical vapor deposition (HDP-CVD). HDP-CVD
Is a technique for generating plasma and depositing a material on a wafer. HDP-CVD has a sputtering component and is generated by the presence of a plasma.
-CVD is activated by the rf bias and applied to the wafer. And HDP-CVD has certain advantages such as low temperature deposition capability and good gap fill capability, and HDP-CVD sputters and etches metals during the deposition process of dielectric material (such as The proper sputtering and etching of the metal is often referred to as clipping). Therefore, what is needed is a technique for forming low-k dielectric ILDs with integrated circuit structures that avoids the harmful tendencies of conventional HDP-CVD described above, while reducing the occurrence of voids (good gap fill).

【０００４】[0004]

【課題を解決するための手段】本発明は、導電性エレメ
ントに低−ｋ誘電体を形成する工程と集積回路を製造す
る工程に関するものである。この製造工程は、導電性エ
レメントに保護層を形成する工程と、続いて保護層に低
−ｋ層形成する工程を含む製造工程である。保護層は、
低−ｋ誘電体の堆積中に導電性エレメントを保護する。
低−ｋ誘電体層は、導電性エレメント間のボイドの発生
を減少させるギャップフィル工程を用いて堆積される。SUMMARY OF THE INVENTION The present invention relates to a process for forming a low-k dielectric on a conductive element and a process for manufacturing an integrated circuit. This manufacturing process is a manufacturing process including a step of forming a protective layer on the conductive element and a step of subsequently forming a low-k layer on the protective layer. The protective layer is
Protect conductive elements during deposition of low-k dielectric.
The low-k dielectric layer is deposited using a gap fill process that reduces the occurrence of voids between the conductive elements.

【０００５】[0005]

【発明の実施の形態】本発明は、低−ｋ誘電体層の形成
に先行して、導電性エレメントに保護層を形成するもの
である。この保護導電性エレメントは、低−ｋ誘電体の
堆積中に導電性エレメントが被害を受けるのを保護し、
導電性エレメントの間にボイドが形成されるのを減少さ
せるような方法で低−ｋ層を堆積することができる。そ
のような構造を図３に示す。基板３０１は導電性エレメ
ント３０２の上に堆積されている。保護材料層３０３は
導電性エレメント３０２を覆うように堆積され、さら
に、低−ｋ誘電体層は保護膜材料層３０３を覆うように
堆積されている。導電体エレメント３０２は高アスペク
ト比を有し、通常の技術により基板３０１上に堆積され
る。DETAILED DESCRIPTION OF THE INVENTION The present invention forms a protective layer on a conductive element prior to forming a low-k dielectric layer. The protective conductive element protects the conductive element from damage during deposition of the low-k dielectric,
The low-k layer can be deposited in such a way as to reduce the formation of voids between the conductive elements. Such a structure is shown in FIG. Substrate 301 is deposited on conductive element 302. A passivation material layer 303 is deposited over the conductive element 302, and a low-k dielectric layer is deposited over the passivation material layer 303. Conductor element 302 has a high aspect ratio and is deposited on substrate 301 by conventional techniques.

【０００６】保護層３０３は導電性エレメント３０２を
腐食から保護するのに重要であり、さらに、低−ｋ誘電
体層３０４を堆積することに起因する破損傾向から保護
するために重要である。低−ｋ誘電体層３０４は、２個
の導電性エレメント３０２間の領域のギャップフィルを
改良する技術を用いて堆積される。最後に、保護層２０
３と低−ｋ層がその場で堆積される。この工程の成果に
より、簡単に上述した低誘電体率層間誘電体（ＩＬＤ）
が導電性エレメントを害することなく、導電性エレメン
ト間に実現する。基板３０１は具体例としては半導体ま
たは誘電体である。導電体エレメント３０２は基板３０
１に対して高くなっており、集積回路の具体例としての
相互接続体であり、そのアスペクト比は３または、それ
より大きい。[0006] The protective layer 303 is important to protect the conductive element 302 from corrosion and is also important to protect against the tendency to break due to the deposition of the low-k dielectric layer 304. The low-k dielectric layer 304 is deposited using a technique that improves the gap fill of the region between the two conductive elements 302. Finally, the protective layer 20
3 and low-k layers are deposited in-situ. The result of this process is that the low dielectric constant interlayer dielectric (ILD)
Are realized between the conductive elements without harming the conductive elements. The substrate 301 is specifically a semiconductor or a dielectric. The conductor element 302 is the substrate 30
It is an interconnect that is higher than 1 and is an example of an integrated circuit having an aspect ratio of 3 or greater.

【０００７】導電性エレメントは、金属、金属スタッ
ク、または集積回路産業において使われる他の導電性の
材料である。機能間ギャプフィルが望まれている集積回
路に種々応用できることは明白であるが、例示として
は、エレメント３０２はＡｌＣｕ金属接続体である。保
護層３０３は、具体例としては、非ドープシリコンガラ
ス（ＵＳＧ）であるが、低−ｋ誘電体層の堆積工程中に
導電性エレメントを保護するのに適する材料であればい
ずれでもよい。さらに、本実施形態の低−誘電体はＦＳ
Ｇであるが、低−ｋ層間誘電体であれば、他の材料を使
用することも本発明の範囲内にある。[0007] The conductive element is a metal, metal stack, or other conductive material used in the integrated circuit industry. Obviously, various applications are possible in integrated circuits where inter-function gap fill is desired, but by way of example, element 302 is an AlCu metal interconnect. The protective layer 303 is, for example, undoped silicon glass (USG), but may be any suitable material for protecting the conductive elements during the deposition process of the low-k dielectric layer. Further, the low-dielectric of this embodiment is FS
G, but other materials that are low-k interlayer dielectrics are within the scope of the invention.

【０００８】図１は本発明の基本的な工程フロー図であ
る。ステップＩは基本的なウェーハ加熱工程である。ス
テップＩＩは保護層の堆積工程である。ステップＩＩＩ
は低−ｋ堆積初期工程である。ステップＩＶは主低−ｋ
層堆積工程である。図２（ａ）および図（ｂ）は例示的
工程パラメータを入れた連続工程の実施形態を示す。図
２（ａ）および図２（ｂ）で開示した工程パラメータ範
囲は±２０％の誤差を見込む。例えば、ステップ（ｅ）
の予想されるＢＲＦ出力の範囲は、６４０Ｗから９６０
Ｗ迄である。FIG. 1 is a basic process flow chart of the present invention. Step I is a basic wafer heating step. Step II is a step of depositing a protective layer. Step III
Is a low-k deposition initial step. Step IV is the main low-k
This is a layer deposition step. 2 (a) and 2 (b) show an embodiment of a continuous process with exemplary process parameters. The process parameter ranges disclosed in FIGS. 2A and 2B allow for an error of ± 20%. For example, step (e)
The expected BRF power range of 640W to 960W
Up to W.

【０００９】水素はＨＤＰ−ＣＶＤフィルムには不適当
な要素であり、フィルム中の水素の含有量は、堆積温度
に反比例するので、基板３０１を適切に予熱する必要が
あり、予熱により保護層の堆積初期における水素の急激
な増加を最小にすることができる。これにより、しばし
ばぶら下がって結合し、従って好ましくないトラップと
して作用する過剰な水素を減じことができる。図１に示
すように、ステップ（ａ）は、初期における電源だけを
加熱するステップのパラメータである。例えば、アプラ
イドマテリアル−５２００センチュラウルチマ 高密度
プラズマ化学堆積システムは、頂上（Ｔ）および側面
（Ｓ）コイルｒｆ励振ソース（ＳＲＦとして示す）によ
り持続されるソースプラズマを有する堆積チャンバとし
て用いられる。[0009] Hydrogen is an unsuitable factor for HDP-CVD films, and the content of hydrogen in the film is inversely proportional to the deposition temperature, so that the substrate 301 must be appropriately preheated. The rapid increase of hydrogen in the early stage of deposition can be minimized. This can reduce excess hydrogen, which often hangs and binds, thus acting as an undesirable trap. As shown in FIG. 1, step (a) is a parameter of the step of heating only the power supply in the initial stage. For example, the Applied Materials-5200 Centura Ultima high density plasma chemical deposition system is used as a deposition chamber with a source plasma sustained by a top (T) and side (S) coil rf excitation source (shown as SRF).

【００１０】加熱ステップは、例えばプラズマからの放
射により、ウェーハを加熱する放射加熱ステップであ
る。すなわち、このステップでのウェーハの変形をなく
し、加熱は金属層３０２に有害な衝撃を与えるようなイ
オン衝撃によるものではない。基板を適当に加熱した
後、このステップにウェーハのそりを伴うスパッタリン
グを避けように保護層３０３の堆積を行う。このステッ
プのパラメータの実施例を図２ａのステップ（ｂ）に示
す。保護層３０３の最終的な厚さは１５０Åのオーダに
なる。この保護層３０３は導電性エレメント３０２を低
−ｋ誘電体材料の中で使用される材料の腐食から効果的
に保護し、さらに、非保護高密度プラズマ化学堆積工程
中にしばしば発生する切り取りを防止するのに重要であ
る。The heating step is a radiation heating step of heating the wafer by, for example, radiation from plasma. That is, the deformation of the wafer in this step is eliminated, and the heating is not due to the ion bombardment that gives a harmful bombardment to the metal layer 302. After the substrate has been appropriately heated, a protective layer 303 is deposited in this step to avoid sputtering with warpage of the wafer. An example of the parameters of this step is shown in step (b) of FIG. 2a. The final thickness of the protective layer 303 is on the order of 150 °. This protective layer 303 effectively protects the conductive element 302 from corrosion of the materials used in the low-k dielectric material, and also prevents cuts that often occur during unprotected high density plasma chemical deposition processes. Important to do.

【００１１】非ドープシリコンガラスを非常に厚くする
ことは目的にそぐわず、またエレメント２０２間の所望
の低−ｋ材料に有害な衝撃になるので、ある厚さに保護
層３０３を維持し、エレメント３０２を適切に保護する
ことは重要であり、この層は必要最小限の厚さにしてお
くことが必要である。本実施形態において、堆積条件、
すなわち非ドープシリコンガラス製の保護膜２０３の厚
さと特性は、導電性エレメント２０２を自由フロンおよ
びＦＳＧ層２０４の堆積工程中にフッ化水素酸の組成物
による腐食から保護する。さらに、ここに開示した実施
形態では、アルゴンスパッタを用い、適切なギャップフ
ィルを確実に行う。[0011] Making the undoped silicon glass very thick is not purposeful and also has a detrimental impact on the desired low-k material between the elements 202, so that the protective layer 303 is maintained at a certain thickness, Proper protection of 302 is important and this layer should be kept to a minimum thickness. In this embodiment, the deposition conditions
That is, the thickness and properties of the protective film 203 made of undoped silicon glass protect the conductive element 202 from corrosion by the hydrofluoric acid composition during the step of depositing the free Freon and FSG layers 204. Furthermore, in the embodiment disclosed herein, an appropriate gap fill is reliably performed by using argon sputtering.

【００１２】当業者には周知のように、金属のような導
電性エレメントを曝すことは、ＨＤＰ−ＣＶＤ工程のア
ルゴンスパッタリング工程中、特に前もってセットされ
た初期のバイアス無線周波数（ＢＲＦ）中に、切り取ら
れ易い。保護膜２０３を堆積した後、低−ｋ層２０４の
堆積が開始される。図２ａおいび図２ｂに示すような実
施形態のステップ（c）ないし（ｇ）に示す低−ｋ層の
堆積の初期段階では、頂上（Ｔ）、側面（Ｓ）およびバ
イアス（ＢＲＦ）コイルを注意深く制御する必要があ
る。As is well known to those skilled in the art, exposing a conductive element, such as a metal, can be accomplished during the argon sputtering step of the HDP-CVD step, particularly during a preset initial bias radio frequency (BRF). Easy to cut off. After depositing the protective film 203, deposition of the low-k layer 204 is started. In the initial stages of low-k layer deposition shown in steps (c) to (g) of the embodiment as shown in FIGS. 2a and 2b, the top (T), side (S) and bias (BRF) coils are It needs to be carefully controlled.

【００１３】基板の温度特性およびＨＦの形態を維持
し、水素の増加を最小にするように頂上（Ｔ）、側面
（Ｓ）コイルを発振状態にして、最初にバイアスコイル
を切る。さらに、最初にＢＲＦを切り、保護層２０３お
よび最後に導電体エレメント２０４に被害を与える物理
的スパッタリング要素を避ける。低−ｋ層が適切な厚さ
になった後、頂上と側面コイルパワーを減少させ、適当
な基板温度を維持した状態でＢＲＦパワーを低水準に切
替える。一旦保護層２０３が堆積され、開始の低−ｋ堆
積層２０４が完了すると、低−ｋ堆積層２０４の主要堆
積ステップが開始される。The top (T) and side (S) coils are oscillated to minimize the increase in hydrogen while maintaining the temperature characteristics of the substrate and the HF morphology, and the bias coil is first turned off. In addition, the BRF is cut first to avoid physical sputtering elements that damage the protective layer 203 and finally the conductor element 204. After the low-k layer has the proper thickness, the top and side coil powers are reduced and the BRF power is switched to a lower level while maintaining the proper substrate temperature. Once the protective layer 203 has been deposited and the starting low-k deposition layer 204 has been completed, the main deposition steps for the low-k deposition layer 204 begin.

【００１４】本実施形態のプロセスパラメータはステッ
プ（ｈ）ないしステップ（ｉ）で示される。層２０４の
主堆積工程中、ＢＲＦパワーを増加し、低−ｋ誘電体層
の基底を保護層の上に堆積させ、低−ｋ層の主堆積工程
中、ケミカルエッチングと物理的スパッタリング要素か
ら導電体を確実に保護する。さらに本実施形態では、他
の前駆体、シランおよび酸素に対する前駆体、ＳｉＦ４
の比率は初期（または、昇温中）および主ＦＳＧ堆積工
程を含み連続する工程中、注意深く維持される。これに
よりフッ素の集中が確実になり、適切に所望の低−ｋ特
性を得ることができるが、最終製品に有害な移動および
腐食特性を増大させない。詳述した本発明は、当業者が
種々変化、修正して実施できることは明らかである。The process parameters of this embodiment are represented by steps (h) to (i). During the main deposition step of layer 204, the BRF power is increased, and the base of the low-k dielectric layer is deposited on the protective layer, and during the main deposition step of the low-k layer, conductive from chemical etching and physical sputtering elements Protect your body. Further, in this embodiment, other precursors, precursors to silane and oxygen, SiF4
Is carefully maintained during the initial (or elevated) and subsequent steps, including the main FSG deposition step. This ensures the concentration of fluorine and properly achieves the desired low-k properties, but does not increase the detrimental migration and corrosion properties of the final product. It is apparent that the present invention described in detail can be implemented by those skilled in the art with various changes and modifications.

【００１５】本発明の顕著な特徴は、集積回路の導電性
機能間の良好なギャップフィルとして低−ｋ誘電体を堆
積する能力を有するものであり、低−ｋ誘電体はお互い
に極めて近接し、また、高アスペクト比を有する。本発
明の恩恵を受け、当業者が容易に行える変化、修正は本
発明の範囲に属する。A salient feature of the present invention is that it has the ability to deposit a low-k dielectric as a good gap fill between the conductive features of an integrated circuit, the low-k dielectrics being very close to each other. , And also have a high aspect ratio. Variations and modifications which can be easily made by those skilled in the art with the benefit of the present invention belong to the scope of the present invention.

【００１６】[0016]

【発明の効果】本発明によれば、集積回路の導電性機能
間の良好なギャップフィルとして低−ｋ誘電体を堆積す
る能力を有するものであり、低−ｋ誘電体はお互いに極
めて近接し、高アスペクト比機能を有する超大規模集積
回路、大集積回路に低−ｋ誘電体材料を堆積工程および
これを用いて製造される集積回路を提供することができ
る。In accordance with the present invention, the ability to deposit a low-k dielectric as a good gap fill between the conductive functions of an integrated circuit, the low-k dielectrics being very close to each other. It is possible to provide a very large scale integrated circuit having a high aspect ratio function, a process of depositing a low-k dielectric material on a large integrated circuit, and an integrated circuit manufactured using the same.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係わる堆積工程のフローチャートであ
る。FIG. 1 is a flowchart of a deposition process according to the present invention.

【図２】図２（ａ）および図２（ｂ）は本発明に係わる
実施形態の低−ｋ誘電体材料の堆積工程のフローチャー
ト図である。FIGS. 2 (a) and 2 (b) are flow charts of a deposition process of a low-k dielectric material according to an embodiment of the present invention.

【図３】本発明に係わる実施形態の集積回路の断面図で
ある。FIG. 3 is a cross-sectional view of the integrated circuit according to the embodiment of the present invention.

【符号の説明】[Explanation of symbols]

２０２ 導電性エレメント ２０３ 保護膜 ２０４ 低−ｋ堆積層（ＦＳＧ層） ３０１ 基板 ３０２ 導電性エレメント ３０３ 保護材料層 ３０４ 低−ｋ誘電体層 202 Conductive element 203 Protective film 204 Low-k deposition layer (FSG layer) 301 Substrate 302 Conductive element 303 Protective material layer 304 Low-k dielectric layer

───────────────────────────────────────────────────── フロントページの続き (71)出願人 596077259 600 Ｍｏｕｎｔａｉｎ Ａｖｅｎｕｅ, Ｍｕｒｒａｙ Ｈｉｌｌ， Ｎｅｗ Ｊｅ ｒｓｅｙ 07974−0636Ｕ．Ｓ．Ａ. (72)発明者 マジャブ アリ アブデルガディル アメリカ合衆国、32828 フロリダ、オー ランド、フィッツウィリアム ウェイ 507 (72)発明者 ビベック サクセナ アメリカ合衆国、32822 フロリダ、オー ランド、ベント パイン ドライブ 5729、アパートメント 306 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Majab Ali Abdelgadir United States, 32828 Florida, Orlando, Fitzwilliam Way 507 (72) Inventor Vivec Saxena United States, 32822 Florida, Orlando, Bent Pine Drive 5729, Apartment 306

Claims (22)

【特許請求の範囲】[Claims] 【請求項１】少なくとも１個の高くなった機能上に保護
層を堆積するステップと、前記保護層上に低−k誘電体
を堆積するステップとを有することを特徴とする集積回
路の製造工程。1. A process for fabricating an integrated circuit, comprising: depositing a protective layer on at least one elevated function; and depositing a low-k dielectric on the protective layer. . 【請求項２】請求項１の集積回路の製造工程において、
前記低−k誘電体を堆積するステップは、高密度プラズ
マ化学堆積法（ＨＤＰ−ＣＶＤ）により行われることを
特徴とする集積回路の製造工程。2. The integrated circuit according to claim 1, wherein:
Depositing the low-k dielectric by high density plasma chemical deposition (HDP-CVD). 【請求項３】請求項２の集積回路の製造工程において、
前記ＨＤＰ−ＣＶＤは、スパッタリング要素およびエッ
チング要素を有することを特徴とする集積回路の製造工
程。3. The integrated circuit according to claim 2, wherein:
The process of manufacturing an integrated circuit, wherein the HDP-CVD has a sputtering element and an etching element. 【請求項４】請求項１の集積回路の製造工程において、
前記低−k誘電体は、フッ化珪素ガラスであることを特
徴とする集積回路の製造工程。4. The integrated circuit according to claim 1, wherein:
The process for manufacturing an integrated circuit, wherein the low-k dielectric is silicon fluoride glass. 【請求項５】請求項１の集積回路の製造工程において、
前記保護層は、非ドープシリコンガラスであることを特
徴とする集積回路の製造工程。5. The integrated circuit according to claim 1, wherein:
The process for manufacturing an integrated circuit, wherein the protective layer is made of undoped silicon glass. 【請求項６】請求項１の集積回路の製造工程において、
前記保護層は、スパッタリング要素を用いずに行われる
ことを特徴とする集積回路の製造工程。6. The process for manufacturing an integrated circuit according to claim 1,
The process of manufacturing an integrated circuit, wherein the protective layer is performed without using a sputtering element. 【請求項７】請求項１の集積回路の製造工程において、
ステップ（ｂ）は、その場で行われることを特徴とする
集積回路の製造工程。7. The integrated circuit according to claim 1, wherein:
Step (b) is a process for manufacturing an integrated circuit, which is performed on the spot. 【請求項８】請求項１の集積回路の製造工程において、
少なくとも１個の導電体エレメントはアスペクト比が
２.０を超えることを特徴とする集積回路の製造工程。8. The integrated circuit according to claim 1, wherein:
A process for manufacturing an integrated circuit, wherein the at least one conductive element has an aspect ratio greater than 2.0. 【請求項９】請求項１の集積回路の製造工程において、
少なくとも１個の導電体エレメントは基板上に堆積さ
れ、かつ前記基板はステップ（ｂ）の一部分でバイアス
されることを特徴とする集積回路の製造工程。9. The integrated circuit according to claim 1, wherein:
A process for producing an integrated circuit, characterized in that at least one conductive element is deposited on a substrate, said substrate being biased in part of step (b). 【請求項１０】少なくとも１個の高くなった機能上に非
ドープシリコンガラスの保護膜を堆積するステップと、
前記保護層上に低−k誘電体をその場堆積するステップ
とを有することを特徴とする集積回路の製造工程。10. Depositing a protective film of undoped silicon glass over at least one of the raised features;
In-situ depositing a low-k dielectric on said protective layer. 【請求項１１】請求項１０の集積回路の製造工程におい
て、前記低−k誘電体は、フッ化珪素ガラスであること
を特徴とする集積回路の製造工程。11. The integrated circuit manufacturing process according to claim 10, wherein said low-k dielectric is silicon fluoride glass. 【請求項１２】請求項１０の集積回路の製造工程におい
て、少なくとも１個の導電体エレメントは基板上に堆積
され、かつ前記基板は前記保護膜の堆積に先行して放射
により加熱されることを特徴とする集積回路の製造工
程。12. The process of claim 10 wherein at least one conductive element is deposited on a substrate and said substrate is heated by radiation prior to depositing said protective film. Manufacturing process for integrated circuits. 【請求項１３】請求項１０の集積回路の製造工程におい
て、ステップ（ａ）は、スパッタリング要素を用いずに
行われることを特徴とする集積回路の製造工程。13. The integrated circuit manufacturing process according to claim 10, wherein the step (a) is performed without using a sputtering element. 【請求項１４】請求項１０の集積回路の製造工程におい
て、前記導電性エレメントは金属機能であることを特徴
とする集積回路の製造工程。14. An integrated circuit manufacturing process according to claim 10, wherein said conductive element has a metal function. 【請求項１５】請求項１０の集積回路の製造工程におい
て、少なくとも１個の導電体エレメントは基板上に堆積
され、かつ前記ステップ（ｂ）は前記基板にｒｆバイア
スをかけ、スパッタリング要素で実行されることを特徴
とする集積回路の製造工程。15. The integrated circuit fabrication process of claim 10, wherein at least one conductive element is deposited on a substrate, and said step (b) is performed with a rf bias on said substrate and with a sputtering element. A process of manufacturing an integrated circuit. 【請求項１６】少なくとも１個の堆積された導電性エレ
メントを有する基板と、少なくとも１個の前記導電性エ
レメント上に堆積された保護層と、前記保護層上に堆積
された低−ｋ誘電体層とを有することを特徴とする集積
回路。16. A substrate having at least one deposited conductive element, a protective layer deposited on at least one said conductive element, and a low-k dielectric deposited on said protective layer. And an integrated circuit. 【請求項１７】請求項１６の集積回路において、前記保
護層は、非ドープシリコンガラス（ＵＳＧ）であること
を特徴とする集積回路。17. The integrated circuit according to claim 16, wherein said protective layer is undoped silicon glass (USG). 【請求項１８】請求項１６の集積回路において、前記低
−k誘電体は、フッ化珪素ガラスであることを特徴とす
る集積回路。18. The integrated circuit according to claim 16, wherein said low-k dielectric is silicon fluoride glass. 【請求項１９】請求項１６の集積回路において、前記少
なくとも１個の導電性エレメントは金属ランナであるこ
とを特徴とする集積回路。19. The integrated circuit according to claim 16, wherein said at least one conductive element is a metal runner. 【請求項２０】請求項１６の集積回路において、前記導
電性層はアスペクト比が２.０以上であることを特徴と
する集積回路。20. The integrated circuit according to claim 16, wherein said conductive layer has an aspect ratio of 2.0 or more. 【請求項２１】少なくとも１個の堆積された金属ランナ
を有する基板と、前記基板上に堆積された非ドープシリ
コンガラス層と、前記非ドープシリコンガラス上に堆積
されたフッ化珪素ガラス層とを有することを特徴とする
集積回路。21. A substrate having at least one deposited metal runner, an undoped silicon glass layer deposited on said substrate, and a silicon fluoride glass layer deposited on said undoped silicon glass. An integrated circuit, comprising: 【請求項２２】請求項２１の集積回路において、前記少
なくとも１個の堆積された金属ランナは、前記導電性層
のアスペクト比が２.０以上であることを特徴とする集
積回路。22. The integrated circuit according to claim 21, wherein said at least one deposited metal runner has an aspect ratio of said conductive layer of 2.0 or more.
JP2000242829A 1999-08-19 2000-08-10 Integrated circuit and process for depositing high-aspect ratio functional gap fill thereof Pending JP2001118843A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645859B1 (en) 2002-01-04 2003-11-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
CN100380624C (en) * 2005-02-24 2008-04-09 台湾积体电路制造股份有限公司 Hdp-cvd methodology for forming pmd layer
JP7433302B2 (en) 2018-09-21 2024-02-19 ラム リサーチ コーポレーション LOW-K ALD gap fill method and materials

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US5661334A (en) * 1996-01-16 1997-08-26 Micron Technology, Inc. Inter-metal dielectric structure which combines fluorine-doped glass and barrier layers
US5937323A (en) * 1997-06-03 1999-08-10 Applied Materials, Inc. Sequencing of the recipe steps for the optimal low-k HDP-CVD processing
US6274933B1 (en) * 1999-01-26 2001-08-14 Agere Systems Guardian Corp. Integrated circuit device having a planar interlevel dielectric layer
US6165915A (en) * 1999-08-11 2000-12-26 Taiwan Semiconductor Manufacturing Company Forming halogen doped glass dielectric layer with enhanced stability

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645859B1 (en) 2002-01-04 2003-11-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
CN100380624C (en) * 2005-02-24 2008-04-09 台湾积体电路制造股份有限公司 Hdp-cvd methodology for forming pmd layer
JP7433302B2 (en) 2018-09-21 2024-02-19 ラム リサーチ コーポレーション LOW-K ALD gap fill method and materials

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