JP2001117960A - Logic simulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately reflect delay caused by the parasitic capacity of the same wiring layer on the logic simulation of an integrated circuit. SOLUTION: When another cell and wiring are not located adjacent to each of cells to be used for logic design, a signal delay time is measured as a first delay time (S10). Besides, the additional layout graphic of the same wiring layer is located adjacent to each of cells (S11) and a signal delay time in this case is measured as second delay time (S12). The first and second delay times are registered in a delay library 12 (S13). Corresponding to the presence/absence of the adjacent layout graphic (S14), any one of first and second delay times is selected as the delay time of each cell provided in the integrated circuit (S15) and logic simulation is performed (S16).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ASIC, for example.
The present invention relates to a logic simulation method used for timing verification of an integrated circuit such as (Application Specific IC).

[0002]

2. Description of the Related Art In recent years, in semiconductor manufacturing, miniaturization techniques in element processing have been advanced. As the miniaturization progresses, the delay time of the transistor element itself of the logic cell decreases, but the output load capacitance of the logic cell does not necessarily decrease because the capacitance between adjacent wirings increases due to the miniaturization of the wiring. For this reason, the proportion of the delay time depending on the wiring in the delay time of the entire circuit relatively increases due to miniaturization. Therefore, in order to perform accurate delay analysis and timing verification on an integrated circuit, it is necessary to accurately estimate a wiring capacitance in consideration of adjacent wiring.

An example of a conventional delay analysis method is described in, for example, Japanese Patent Application Laid-Open No. 9-293787. In this conventional example, the layout of an LSI composed of a plurality of cells is analyzed using a library including delay information due to parasitic capacitance between a pass-on-cell line and an intra-cell line,
Calculate the delay time. The library describes the correlation between the grid utilization rate and the delay value of the pass-on-cell wiring, and
The grid usage rate in each wiring area is obtained from the layout information of the above, and the library is referred to based on the grid usage rate to obtain a delay in consideration of the parasitic capacitance between the on-cell wiring and the intra-cell wiring.

[0004]

However, conventionally,
There were the following problems.

FIG. 11 is a graph showing the relationship between the wiring capacitance and the design rule. With the development of microfabrication technology,
In integrated circuits, wiring widths are becoming increasingly narrower and wiring spacings are becoming even smaller. For this reason, as shown in FIG. 11, according to a recent design rule (1 μm or less), the capacitance between the same wiring layers is larger than the capacitance between different wiring layers which is the ground capacitance (“VLSI system design”). -Fundamentals of Circuits and Mounting-"p. 148, Maruzen Co., Ltd., March 1995). However, in the above-described delay analysis according to the conventional example, although the wiring capacitance caused by the on-cell wiring is considered, the parasitic capacitance between the same wiring layers is not considered at all.

[0006] Further, with the increase in the scale of the LSI, a hierarchical design in which the function of the entire LSI is divided into a plurality of functional blocks and a logical design and a layout design are performed for each functional block has become mainstream in the LSI design. . In such a hierarchical design, since wiring between functional blocks has not been performed yet at the stage of the floor plan for arranging the functional blocks, wiring between the functional blocks and wiring within the functional blocks are performed after the wiring between the blocks is performed. There is a possibility that the delay time changes due to the parasitic capacitance between them. For this reason, LS
In the timing verification of the entire I, unexpected operation failure inside the block may occur, and design rework may be required.

In view of the above problems, it is an object of the present invention to accurately reflect a delay caused by a parasitic capacitance of the same wiring layer as a logic simulation method.

It is another object of the present invention to accurately reflect a parasitic capacitance between a wiring in a functional block and a wiring between functional blocks in correspondence with a hierarchical design as a logic simulation method.

[0009]

According to a first aspect of the present invention, there is provided a logic simulation method in which, for each cell used for logic design, other cells and wiring are not adjacent to each other. Measuring the delay time between input and output signals in the case as a first delay time
Measuring step, a figure adding step of arranging an additional layout figure of the same wiring layer as that of the cell adjacent to the layout figure of each cell, and input / output when the additional layout figure is arranged adjacent to each cell. A second method for measuring a delay time between signals as a second delay time
Measuring step, registering the first and second delay times as delay times of the respective cells in a delay library, and determining the delay time of each cell included in the integrated circuit as a delay time of a layout pattern adjacent to the cell. A delay selecting step of selecting either the first delay time or the second delay time according to presence or absence, and performing a logic simulation of the integrated circuit using the selected delay time.

According to the first aspect of the present invention, the first delay time when the other cell and the wiring are not adjacent to each other and the second delay time when the additional layout graphic of the same wiring layer is adjacently arranged are delayed. Registered in the library.
Then, as the delay time of each cell included in the integrated circuit, one of the first delay time and the second delay time is selected according to the presence or absence of a layout graphic adjacent to the cell. Therefore, the delay due to the parasitic capacitance of the same wiring layer is accurately reflected in the logic simulation.

According to a second aspect of the present invention, the additional layout figure in the logic simulation method of the first aspect is a figure representing the internal layout of the cell.

In the third aspect of the present invention, the graphic adding step in the logic simulation method according to the second aspect includes the step of preferentially selecting a frequently used cell and adding the graphic representing the internal layout of the selected cell. It shall be used as a layout figure.

[0013] According to the invention of claim 4, in the invention of claim 2,
The logic simulation method further comprises the step of classifying each cell used in the logic design according to the degree of wiring congestion inside the cell, and the figure adding step includes the steps of: It shall be used as the additional layout figure.

[0014] In the invention of claim 5, according to claim 1,
In the logic simulation method, the additional layout graphic is a graphic representing a wiring, and the second measuring step measures the second delay time by changing a distance between the cell and the graphic representing the wiring. Then, the correspondence between the distance and the second delay time is determined. In the delay selecting step, when a layout graphic adjacent to the cell exists, the correspondence determined in the second measurement step is determined. The second delay time obtained based on the distance between the cell and the adjacent layout figure is determined as the delay time of the cell.

According to a sixth aspect of the present invention, as a method of performing a logic simulation on a logic-designed integrated circuit, the shape and arrangement of the functional blocks included in the integrated circuit and the general wiring path between the functional blocks are floorplanned. Determining, the step of designing the internal layout of each arranged functional block, the step of adding virtual wiring to the wiring area between the functional blocks, and the inside of each functional block taking into account the added virtual wiring. Performing a delay analysis.

According to the invention of claim 6, the virtual wiring is added to the wiring area between the functional blocks as a result of the floor plan, and the added virtual wiring is taken into account in the delay analysis inside each functional block. Therefore, at the stage of designing the functional block, it is possible to consider the parasitic capacitance between the wiring in the functional block and the wiring between the functional blocks.

According to a seventh aspect of the present invention, the logic simulation method according to the sixth aspect includes a step of obtaining a wiring congestion degree in a wiring region of the integrated circuit from a result of determining a general wiring path by a floor plan; In the virtual wiring addition step, it is determined whether or not a virtual wiring is added in each wiring area according to the wiring congestion degree.

Further, in the invention according to claim 8, the virtual wiring adding step in the logic simulation method according to claim 7 adds a virtual wiring to a wiring area having the highest wiring congestion degree.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a flowchart showing a flow of processing in a logic simulation method according to a first embodiment of the present invention.

First, in step S10 as a first measurement step, for each cell used for logic design,
The propagation delay time of the input / output signal when there is no other cell or wiring adjacent to the cell is measured as the first delay time. The cell graphic data 10 stores the layout graphic of each cell, and each layout graphic expresses a layout graphic of transistors and wirings inside the cell.

FIG. 2 is a diagram showing an example of a layout graphic of a cell. In FIG. 2, a cell 21 includes a gate pattern 22 of a transistor and a wiring pattern 23 connecting a source region of the transistor. In step S10,
The first delay time is measured by extracting the wiring resistance and the wiring capacitance of the circuit from the cell layout graphic as shown in FIG. 2 and executing a circuit simulation. The wiring capacitance extracted in step S10 is limited to the inter-graphic capacitance inside the cell, such as the capacitance between the gate graphic 22 and the wiring graphic 23.

In step S11 as a figure adding step, a figure representing the internal layout of another cell in the same wiring layer as this cell is added adjacent to the cell whose first delay time was measured in step S10. Place as a figure. The additional graphic data 11 stores a layout graphic of a cell to be additionally arranged.

FIG. 3 is a diagram showing a layout figure as a result of arranging layout figures 31A and 31B of other cells adjacent to the cell 21 of FIG. In FIG. 3, reference numeral 32 denotes a layout figure of a gate of a transistor in a layout figure 31A of another cell, and reference numeral 33 denotes a wiring figure for connecting a source region of a transistor in a layout figure 31A of another cell.

In step S12 as a second measurement step, the propagation delay time of the input / output signal in the case where the layout graphic is adjacent to the cell in which the layout graphic of another cell is adjacently arranged in step S11 is set to the second. Measured as the delay time. That is, the second delay time is measured by extracting the wiring resistance and the wiring capacitance of the circuit of the cell 21 from the layout graphic as shown in FIG. 3 and executing a circuit simulation.

The wiring capacitance used in step S12 includes the gate figure 22 of the cell 21 and the adjacent cell 31.
A wiring capacitance between cells is added, such as a capacitance C1 between the gate graphic 32 of A and a capacitance C2 between the gate graphic 22 of the cell 21 and the wiring graphic 33 of the adjacent cell 31A. For this reason, for example, the capacitance of the gate figure 22 of the transistor included in the cell 21 increases, so that the second delay time of the cell 21 measured here is longer than the first delay time measured in step S10. Become.

Then, step S as a registration step
At 13, the first delay time measured at step S10 and the second delay time measured at step S12 are registered as delay parameters of the cell 21 in the delay library 12 used for logic simulation.

Steps S10 to S13 are executed for each cell, whereby a delay library 12 in which the first and second delay times are registered as delay parameters of each cell is generated.

In step S14, the block layout 13 of the integrated circuit in which a plurality of cells are arranged is read, and each cell included in the integrated circuit is searched for an adjacent layout graphic. In step S15, the second delay time measured in step S12 is selected as the delay time for the cell adjacent to the layout graphic, and the first delay measured in step S10 is selected for the cell not adjacent to the layout graphic in step S12. Select the delay time as the delay time. Step S14, S1
5 constitutes a delay selection step. Then, in step S16, a logic simulation of the integrated circuit is executed using the delay time selected for each cell.

Here, in steps S11 and S12, only the delay time when the layout graphic of another cell is adjacent to both sides of the cell is extracted as the second delay time. Alternatively, a delay time in the case of being adjacent to only one side may be extracted as the second delay time. In steps S11 and S12, when the second delay time is measured for the case where the layout graphic of another cell is adjacent to both sides of the cell, the case where it is adjacent only to the right side, and the case where it is adjacent only to the left side, step S14 is performed. In the case where there is an adjacent layout graphic, the delay time can be selected depending on whether the adjacent layout graphic is on both sides of the cell, only on the right side, or only on the left side.

In step S11, a cell which is frequently used may be preferentially selected, and a graphic representing the internal layout of the selected cell may be arranged as an additional layout graphic.

In this case, the cell layout figure is made adjacent to the second delay time measurement.
In step S11, rectangular graphics 41A and 41B representing wiring as shown in FIG. 4 may be adjacent to each other as additional layout graphics. In this case, step S12
, The second delay time is measured by changing the distance between the figures 41A and 41B and the cell 21, and the correspondence between this distance and the second delay time is determined. FIG. 5 is a graph showing an example of such a correspondence relationship. In step S14, when there is a layout graphic adjacent to a certain cell, the distance between the cell and the adjacent layout graphic is obtained. In step S15, based on the correspondence shown in the graph of FIG. A second delay time corresponding to the distance is calculated, and this is determined as the delay time of the cell. This makes it possible to more accurately reflect the influence of the adjacent wiring on the logic simulation.

The wiring capacitance of the cell for measuring the second delay time changes depending on the wiring congestion inside the cell adjacent thereto. Therefore, by classifying the cell type according to the degree of wiring congestion inside the cell and measuring the second delay time for each cell type, more accurate measurement of the second delay time becomes possible.

FIG. 6 is a flowchart showing the flow of processing in a logic simulation method according to a modification of the present embodiment. In FIG. 6, cells adjacent to each other for the measurement of the second delay time are classified according to the wiring congestion inside the cells.

In step S21, the cells are classified according to the degree of internal wiring congestion. This classification is performed according to the magnitude of the capacitance value generated between the cell 51 and the graphic 52, as shown in FIG. The result of the classification is registered in the group data 15. In step S11, the layout graphic of the representative cell of each group included in the group data 15 is used as the layout graphic of the adjacent cell, and the second delay time is measured in each case. In step S15, when an adjacent cell exists in a certain cell, a group to which the adjacent cell belongs is specified with reference to the group data 15, and a second delay time corresponding to the group is selected.

As described above, according to the present embodiment, the first and second delay times that differ depending on the presence / absence of the adjacent cells and wirings are registered in the delay library, and the data after layout are used to determine the presence / absence of the adjacent cells and wirings. By selecting a delay time according to and performing a logic simulation,
A highly accurate logic simulation that accurately reflects the parasitic capacitance between adjacent cells and wirings can be performed.

(Second Embodiment) FIG. 8 is a flowchart showing a flow of processing in a logic simulation method according to a second embodiment of the present invention.

First, in step S31, for the integrated circuit to be designed, the shape and arrangement of each functional block and the schematic wiring path between the functional blocks are determined by the floor plan.

FIG. 9 is a diagram showing an example of the layout of the integrated circuit obtained in step S31. In the layout shown in FIG. 9, three functional blocks 71A, 71B and 71C are provided. In addition, a wirable area is represented using a graph including a combination of the branch 72 and the node 73 as indicated by a broken line, and the schematic wiring is performed using this graph. For example, the signal terminals 74a,
Assuming that general wiring is performed between the signal terminals 74b,
a and 74b are the closest nodes 73a and 73b, respectively.
And the wiring path 75 is represented by a branch 72 on the graph.
a, 72b, 72c, and 72d.

Next, in step S32, the degree of wiring congestion is calculated. From the result of the schematic wiring as shown in FIG. 9, the number of wirings passing through each branch 72 on the graph is counted,
The number of wirings passing through each branch 72 is defined as the wiring congestion degree in the wiring area at the position of the branch 72. Then, the obtained wiring congestion degree is output as wiring congestion degree data 61.

Next, in step S33, the layout of each functional block is performed. In the example of FIG. 9, a plurality of cells constituting the functional blocks 71A, 71B and 71C are arranged, and layout data of wiring connecting the cells is generated.

Next, in step S34, an additional graphic representing a virtual wiring is arranged in one of the wiring areas corresponding to the branch 72. Here, the wiring congestion degree data 61 is read, and the presence or absence of the addition of the virtual wiring in each wiring area is determined according to the wiring congestion degree. For example, assuming that the wiring congestion in the wiring area at the position of the branch 72 on both sides of the functional block 71A is high, as shown in FIG.
Additional graphics 81A and 81B are generated on both sides of 1A. The virtual wiring may be added to a region where the area of the integrated circuit is determined, for example, a wiring region with the highest wiring congestion.

Next, in step S35, a logic simulation is performed on the inside of each functional block. For example, with respect to the function block 71A shown in FIG. 10, taking into account the additional figures 81A and 81B, the resistance and capacitance of the wiring inside the function block are extracted, and a logical simulation is performed to determine whether the circuit inside the function block operates normally. Verify by If there is a functional block that does not operate normally, the process returns to step S33, and the block layout is executed again.

In step S36, a wiring process between a plurality of functional blocks is executed. In step S37, the resistance and capacitance of the wiring between the functional blocks are extracted.
In step S35, a logic simulation of the entire integrated circuit is executed together with the resistance and capacitance of the wiring inside each functional block already extracted.

As described above, according to the present embodiment, the parasitic capacitance between the wiring inside the functional block and the wiring outside the functional block is considered from the schematic wiring path obtained by the floor plan. Can predict a delay variation due to the existence of the inter-block wiring, and therefore can execute a high-precision logic simulation without design rework corresponding to the hierarchical design.

[0046]

As described above, according to the present invention, it is possible to accurately reflect the parasitic capacitance between adjacent cells and wirings in the same wiring layer in a theoretical simulation.

Further, according to the present invention, it is possible to predict a delay variation due to the existence of the inter-block wiring at the block design stage, so that a high-precision logic simulation without design rework corresponding to a hierarchical design can be executed. it can.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a process flow in a logic simulation method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout graphic of a cell.

FIG. 3 is a diagram in which a layout graphic of another cell is arranged adjacent to the cell of FIG. 2;

FIG. 4 is a diagram in which a layout graphic representing a wiring is arranged adjacent to the cell of FIG. 2;

FIG. 5 is a graph showing a relationship between a second delay time and a distance between a cell and an adjacent layout graphic.

FIG. 6 is a flowchart illustrating a flow of processing in a logic simulation method according to a modification of the first embodiment of the present invention.

FIG. 7 is a diagram for explaining a classification method based on a wiring congestion degree.

FIG. 8 is a flowchart illustrating a flow of processing in a logic simulation method according to a second embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of a layout of an integrated circuit obtained by a floor plan.

FIG. 10 is a diagram showing an example in which additional graphics are arranged.

FIG. 11 is a graph showing a relationship between a wiring capacitance and a design rule.

[Explanation of symbols]

12 Delay library 21, 51 cell 31A, 31B Graphic representing internal layout of cell (additional layout graphic) 41A, 41B Graphic representing wiring (additional layout graphic) 71A, 71B, 71C Functional block 75 Schematic wiring path 81A, 81B Virtual wiring

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Claims (8)

[Claims] A first measurement step of measuring, as a first delay time, a delay time between input / output signals when other cells and wiring are not adjacent to each other used for a logic design; A figure adding step of arranging an additional layout figure of the same wiring layer as the cell adjacent to the layout figure; and, for each of the cells, a delay time between input / output signals when the additional layout figure is arranged adjacent to the layout figure. A second measuring step of measuring the delay time as a second delay time; a registering step of registering the first and second delay times as a delay time of each cell in a delay library; a delay time of each cell included in the integrated circuit. A delay for selecting either the first delay time or the second delay time according to the presence or absence of a layout graphic adjacent to the cell. Logic simulation method and a selection step, using the delay time selected, and performing logic simulation of the integrated circuit. 2. The logic simulation method according to claim 1, wherein the additional layout graphic is a graphic representing an internal layout of a cell. 3. The logic simulation method according to claim 2, wherein, in the graphic adding step, a frequently used cell is preferentially selected, and a graphic representing an internal layout of the selected cell is used as the additional layout graphic. A logic simulation method characterized by the following. 4. The logic simulation method according to claim 2, further comprising the step of classifying each cell used for logic design according to the degree of wiring congestion inside the cell, wherein the figure adding step includes: A logic simulation method, wherein a layout graphic of a representative cell is used as the additional layout graphic. 5. The logic simulation method according to claim 1, wherein the additional layout graphic is a graphic representing a wiring, and wherein the second measuring step determines a distance between the cell and the graphic representing the wiring. The second delay time is measured separately, and the correspondence between the distance and the second delay time is obtained. The delay selecting step includes the steps of: Based on the correspondence obtained in the second measurement step,
The logic simulation method according to claim 1, wherein the second delay time obtained according to the distance between the cell and the adjacent layout graphic is determined as the delay time of the cell. 6. A method for performing a logic simulation on a logic-designed integrated circuit, wherein a shape and arrangement of functional blocks included in the integrated circuit and a schematic wiring path between the functional blocks are determined by a floor plan. The steps of designing the internal layout of each placed functional block; the step of adding virtual wiring to the wiring area between the functional blocks; Performing a delay analysis. 7. The logic simulation method according to claim 6, further comprising a step of obtaining a wiring congestion degree in a wiring area of the integrated circuit from a result of determining a general wiring path based on a floor plan. A logic simulation method characterized by determining whether virtual wiring is added in each wiring area according to the congestion degree. 8. The logic simulation method according to claim 7, wherein in the virtual wiring adding step, a virtual wiring is added to a wiring region having a highest degree of wiring congestion.