JP2001111754A - Self-diagnostic method for processing section group - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a self-diagnostic method for a processing section group by which self-diagnosis can efficiently be conducted in the case of diagnosing a device having a plurality of processing sections. SOLUTION: Processing sections as a 1st video board 234, a 2nd video board 235, a color board 236, a digital filter board 237 and a medium tone processing board 238 are placed in the processing sequence of image data. A dark shading memory 601 in the 1st video board 234 is used in common for a pattern generator, which generates a self-diagnosis signal. A diagnosis memory in the medium tone processing board 238 stores a signal whose processing is finished and a CPU 331 compares the signal with a signal obtained in the normal case and decides that any of the boards is faulty when they do not match. In this case, an existing element of the boards is used as a pattern generator in the sequence from the last processing section and each board can be diagnosed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis method for a processing unit group used in an image forming apparatus such as a copying machine, a facsimile machine, a printer, and an image reading apparatus such as a scanner. The present invention relates to a method for self-diagnosis of a group of processing units, which is capable of efficiently performing self-diagnosis by an apparatus having a configuration in which are connected in signal processing.

[0002]

2. Description of the Related Art In recent years, various apparatuses for image processing have been actively developed, and digital copiers for digitally processing images and scanners for reading originals have become widespread in offices and the like. I have. At the same time, there has been an increasing demand for improving the processing speed of these apparatuses for image recording and reading, and for processing larger sized originals. To satisfy such demands, higher-speed image processing is required.

When high-speed image processing is demanded as described above, it is difficult to realize such an image processing apparatus by conventional image processing that relies on software for various processes. Therefore, there is a need to devise each part for performing image processing by hardware, and to increase the substantial processing speed by parallelizing the processing. Accompanying this, there is a tendency that the scale of hardware further increases and the number of various substrates for image processing also increases.

However, in such an image processing apparatus, if any failure occurs even in a part of an enormous number of circuits, a failure such as deterioration of image quality or operation of the apparatus itself occurs. Therefore, conventionally, a system has often been used in which the device itself diagnoses each substrate when the device is started up. Such a self-diagnosis system (Diag
As a nostics system, there is a system provided with a pattern generator for performing self-diagnosis for each board. However, in such a case, since the pattern generator is provided on each substrate, there is a problem that the hardware is further increased and that the cost of the entire apparatus is considerably burdened. As a solution to such a problem, there is a technology in which a CPU (central processing unit) is arranged on one board, and various components are checked using the CPU.

FIG. 38 shows the latter self-diagnosis method and an image processing apparatus using this method.
1655 is described. The image processing apparatus shown in this figure includes an imaging unit (IU) 101 that performs an image reading process. A color video signal 102 output from the imaging unit 101 is input to an analog substrate 103, where the signal is converted into a digital signal 104 after performing automatic gain control and the like. This digital signal 104
Is input to a CPU (Central Processing Unit) board 105.
The CPU board 105 performs color separation, synthesis, or shading correction.

Image data 1 output from CPU board 105
06 is a first image processing system (IPS) substrate 10
7 and the second image processing system board 108, and the desired image processing is performed by these. The reason why the first and second image processing system boards 107 and 108 are prepared for image processing is to reduce the cost of replacing the board when a failure occurs. May be constituted by the above substrate. The processed image data 109 is sent to an image output terminal (IOT) 110 to record (copy) the image.
Will be performed.

In this image processing apparatus, the CPU board 105
It is also connected to the film projector 111 and the user interface 112. The film projector 111 is a device for projecting a film image on a platen (not shown), so that an image can be recorded on the image output terminal 110. The user interface 112 is configured by a control panel including a display device such as a CRT and a liquid crystal display and an input device such as a numeric keypad, so that the user can instruct recording and editing.

Next, the self-diagnosis of the image processing apparatus having the above configuration will be described. The CPU board 105 has a CPU
114 is mounted. The CPU has a software module for performing self-diagnosis. Then, when a predetermined operation is performed from the user interface 112, a check of the D / A converter, the pattern generator, and the like is sequentially performed for each corresponding substrate.

FIG. 39 shows the contents displayed on the display device of the user interface during the self-diagnosis. As shown in the figure, the upper part of the display screen 121 indicates that the self-diagnosis mode (DIAGNOSTIC MODE) is set, and below that, each mark 12 of START (start), STOP (stop) and EXIT (exit) is displayed.
2 to 124 are displayed. When the START mark 122 is pressed, a self-diagnosis for checking, for example, the D / A converter is started.

FIG. 40 shows a circuit configuration when a self-diagnosis is performed on the D / A converter. This D
In the self-diagnosis mode for the / A converter, the CPU 114
Is supplied to the D / A converter 131, and the analog signal after the D / A conversion is supplied to the comparator 13
1 is supplied to one input terminal. At this time, a predetermined reference voltage V _TH is input to the other input terminal of the comparator 132. The output side of the comparator 132 is connected to the other end of the light emitting diode 134 having one end connected to the pull-up resistor 133. For this reason,
If the CPU 114 supplies a digital signal having a value that raises or lowers the threshold level of the comparator 132 to the D / A converter 131, the light emitting diode 134
Flashes accordingly. The operator performing the self-diagnosis checks the blinking and checks the D / A converter 131.
Is normal.

When the diagnosis for the D / A converter 131 has been completed in this way, the operator operates the EXIT shown in FIG.
The user selects the mark 124 to exit the mode for checking the D / A converter 131, and starts the next self-diagnosis. In this way, the diagnosis of each part of the information processing device is performed. When the operator wants to end the self-diagnosis on the way, the operator can use the ST shown in FIG.
What is necessary is just to press the OP mark 123.

[0012]

However, in the latter self-diagnosis method using the latter self-diagnosis system,
Only a simple check of each component, such as a check of a failure of the D / A converter, could be performed. For this reason, when checking complicated processing such as a circuit portion that performs image processing, it is necessary to rely on a self-diagnosis method using the former self-diagnosis system including a pattern generator for each substrate. . In such a case, as described above, there is a problem that the scale of the hardware is unnecessarily increased, and the cost of the apparatus is significantly increased.

Although the self-diagnosis of boards for processing image data has been described above, the same applies to the self-diagnosis of these boards in an apparatus that sequentially processes certain information by using a plurality of boards or processing units. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a self-diagnosis method for a group of processing units that can perform an efficient self-diagnosis when diagnosing an apparatus having a plurality of processing units.

[0015]

According to the first aspect of the present invention,
A self-diagnosis method for a processing unit group including a plurality of processing units for sequentially processing signals, wherein a self-diagnosis is performed on the entire processing unit group, and a failure is generated as a result of the self-diagnosis on the entire processing unit group. And individually diagnosing which of the processing units in the processing unit group is out of order when found.

That is, according to the first aspect of the present invention, the self-diagnosis is first performed in the step of performing the self-diagnosis for the entire processing unit group including a plurality of processing units. Thus, the diagnosis can be terminated without performing the diagnosis, which is efficient. Only when a failure is found as a result of the self-diagnosis of the entire processing unit group, an individual diagnosis of which of the processing units in the processing unit group has failed is disclosed.

According to a second aspect of the present invention, there is provided a self-diagnosis method for a processing unit group comprising a plurality of processing units for sequentially processing signals, wherein the first processing unit in the processing unit group is sequentially executed by subsequent processing units. A step of generating diagnostic data to be processed by a diagnostic data generating unit arranged in a first processing unit; and a case in which the processed data in which the diagnostic data is sequentially processed and the plurality of processing units are all normal. Comparing the check data obtained in step (a), determining that one of the plurality of processing units is faulty when the comparison results do not match, and faulting one of the plurality of processing units. When it is determined that the individual diagnostic data is generated in the individual diagnostic data generators arranged in each of the plurality of processing units in order from the last processing unit of the processing unit group to the first processing unit. Comparing the processed data obtained by processing the individual diagnostic data with the individual check data obtained when all the processing units subsequent to the processing unit in which the individual diagnostic data were generated are normal. Judging that the circuit between the individual diagnostic data generator that generated the individual diagnostic data and the individual diagnostic data generator that generated the individual diagnostic data immediately before when the results did not match is faulty; It is characterized by having.

That is, in the invention according to the second aspect, the diagnostic data generator arranged in the first processing unit of the processing unit group generates the diagnostic data sequentially processed by the subsequent processing units, and the diagnostic data is The sequentially processed data is compared with the check data obtained when all of the plurality of processing units are normal. If the comparison results do not match, one of the plurality of processing units has failed. To judge. If it is determined that any of the plurality of processing units is faulty, the individual diagnostic data is sequentially sent from the last processing unit to the first processing unit in the processing unit group. Are generated by the individual diagnostic data generators arranged in each case, and are obtained when all of the processed data after processing the individual diagnostic data and the processing units after the processing unit where the individual diagnostic data were generated are normal. By comparing the individual check data obtained, the individual diagnostic data generator that generated the individual diagnostic data at the stage where the comparison results do not match and the individual diagnostic data generator that generated the individual diagnostic data immediately before Circuit is determined to be faulty. Also in the present invention, the processed data in which the diagnostic data is sequentially processed is compared with the check data obtained when the plurality of processing units are all normal. Thus, the diagnosis can be terminated without performing the procedure, which is efficient. When the comparison results do not match, individual diagnostic data is generated in order from the last processing unit in the processing unit group, and the processed data obtained by processing the individual diagnostic data is compared with the check data. Therefore, the failed processing unit can be easily checked.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

(Overview of Digital Copier)

FIG. 2 shows the appearance of a digital copying machine to which the self-diagnosis method of the processing section group according to one embodiment of the present invention is applied. The digital copier includes an image scanner unit 220 equipped with a page memory (not shown) for reading an original (not shown) with a full-color image sensor and storing image data subjected to various image processing and image editing.
A print unit 221 prints the image data stored in the image scanner unit 220 in two colors. The image scanner unit 220 is provided with a control panel for the user to specify the number of copies, various image processing / editing functions, and the like, so that a desired copy can be obtained by the designation. .

(Configuration of Image Scanner Unit)

FIG. 3 shows the configuration of the image scanner unit. The image scanner unit 220 has an image sensor 231 using a charge-coupled device (hereinafter, referred to as a CCD). The image sensor 231 is mounted on a CCD drive board 232. In the subsequent stage of the CCD drive substrate 232, an analog substrate 233,
First video board 234, second video board 235, color board 236, digital filter board (DF board)
237 and a halftone processing substrate 238 are provided.
An area recognition board 239 is connected to the color board 236, and an editing board 241 for performing image editing is connected to the halftone processing board 238.

The first video board 234 to the halftone processing board 238, the area recognition board 239 and the editing board 2
41 and a first CPU (central processing unit) for controlling them
The board 244 is a VM that is one of the system bus standards.
They are connected to each other by an E bus 245 and housed in an image processor system (IPS) rack 246.

Image processor system rack 246
The data processing substrate 251 is connected to the next stage of the halftone processing substrate 238 disposed at the end of the data processing substrate 238. The data processing board 251 is connected to a second CPU board 252 and a page memory board 253 on which a page memory is arranged. Also, a control panel 254 for operation by the operator is provided on the second CPU board 252.
Is connected. The data processing board 251 outputs the processed image data 255 to the printing unit 221 (see FIG. 2), and receives a control signal 256 from the printing unit 221. Also, the second CPU board 2
52 is a first CPU board 2 via a control data line 257
44, and to a control unit of a printing unit to be described later via a control data line 258.

FIG. 4 shows a specific configuration of the printing unit. The print unit 221 includes a data separation unit 261 that inputs image data 255 from the image scanner unit 220. A first-color image data memory 262 and a second-color image data memory 263 are provided at the next stage of the data separation unit 261, and store image data of the first color and the second color, respectively. The first color laser driving unit 2 is provided after the first color image data memory 262.
64, and a second-color laser driving unit 265 is arranged at the subsequent stage of the second-color image data memory 263, respectively.
The laser is driven by each color. The control section 266 is connected to the second CPU board 252 (FIG. 3) of the image scanner section 220 via the control data line 267. Further, the control signal 256 is sent to the data processing board 251 (FIG. 3) of the image scanner unit 220.

FIG. 5 schematically shows the image scanner section shown in FIG. Image scanner unit 220
Are original feed rollers 302 and 303 arranged at a predetermined interval above the original conveying path, and rollers 304 and 305 arranged correspondingly below the original conveying path below the original conveying path.
And The original 306 is formed by these rollers 302 to
The sheet 305 is conveyed to the left in FIG. The platen glass 3 is located almost at the center of the document conveyance path.
07 is placed thereon, on which platen row et al.
Are arranged so as to be in contact with this.

The original 30 is placed under the platen glass 307.
6, a light source 309 for illuminating the reading position 6 and a convergent rod lens array 310 for forming reflected light of the document on the image sensor 231 are arranged. The image sensor 231 is mounted on the CCD drive board 232 shown in FIG. Further, a sensor 315 for detecting insertion of the document 306 is provided in the document insertion portion of the image scanner unit 220. Further, the platen roller 3
08 around the platen roller 3
A reference plate 312 rotatable about a central axis 08 is provided.

FIG. 6 shows the structure of this reference plate. The reference plate 312 has a black surface 313 serving as a reference for a black level when reading an image, and a white surface 314 serving as a reference for a white level (background). These black surfaces 313
The white surface 314 can be selectively interposed between the platen glass 307 and the platen roller 308.

FIG. 7 shows an arrangement structure of the image sensor. Image sensor 2 used in this embodiment
Reference numeral 31 denotes a full-color contact type sensor, which includes first to fifth line-type sensor chips 321 to 3 arranged in a staggered manner.
It consists of 25.

In this embodiment, a group of the first, third and fifth sensor chips 321, 323, and 325 and the remaining second
The reading of the image in the main scanning direction is not interrupted at the boundary between the group and the group of the fourth sensor chips 322 and 324. 1st, 3rd
In addition, between the fifth sensor chip 321, 323, 325 and the remaining second and fourth sensor chips 322, 324, their arrangement positions are shifted by an interval Δx in a direction perpendicular to the scanning direction. The process of converting the image data read by these five line-type sensor chips 321 to 325 into image data obtained by reading the same line of the document 306 (FIG. 5) is performed by a circuit in a first video board 234 described later. ing.

FIG. 8 shows a state of a pixel arrangement in a chip constituting the image sensor. In order to realize full color, the first to fifth line-type sensor chips 321 to 325 shown in FIG. 7 include a pixel 326B for reading blue image data, a pixel 326G for reading green image data, and a red pixel 326G. Pixel 3 for reading image data
26R are arranged in this order repeatedly.

(Description of First CPU Board)

FIG. 9 specifically shows the structure of the first CPU board. The first CPU board 244 has a CP
U331, timer 332, read only memory (hereinafter referred to as ROM) 333, random access memory (hereinafter referred to as RAM) 334, VME bus interface (hereinafter referred to as VME bus I / F). 33
5, an output control unit 336, an input control unit 337, and a serial communication unit 338. These are connected to each other by a bus 339. VME bus I / F 335 is V
The ME bus 245 (see FIG. 3) is connected, and the serial communication unit 338 is connected to the control data line 257 (see FIG. 3). The first CPU board 244 controls each board in the image processor system rack 246 and executes the second CPU board 25 by executing a program stored in the ROM 333 using the RAM 334 as a work area.
2 (see FIG. 3). Note that the first CPU board 244 is provided with a clock generation unit 340 for supplying a clock signal to each unit.

A description will be given with reference to FIG. In the image scanner unit 220 shown in FIG. 3, the user can control the desired number of copies and various image processing / editing by using the control panel 254.
, The CPU on the second CPU board 252 sends various image processing / editing information selected on the control panel 254 to the CPU 331 on the first CPU board 244 through the control data line 257. The CPU on the second CPU board 252 sends information such as the paper size selected by the control panel 254 to the control unit 266 of the print unit 221 through the control data line 267 (FIG. 4).

In the first CPU board 244 shown in FIG. 9, various image processing / editing information sent through the control data line 257 is taken into the first CPU board 244 via the serial communication section 338. The decryption is performed by the CPU 331. The CPU 331 sends various parameters (control data) corresponding to the image processing / editing information to the VME bus I /
Each board 23 in the image processor system rack 246 through the F335 and the VME bus 245 shown in FIG.
4 to 241 are set in predetermined registers and RAM.

Next, the image scanner unit 2 shown in FIG.
When the operator inserts the document 306 at 20, the sensor 3
15 turns on. The CPU 331 is the first CPU in FIG.
This is detected through the input control unit 337 of the board 244. Then, an original feed motor (not shown) is driven, and the original 306 is conveyed by the original feed rollers 302 and 303. When the document 306 in the transport state reaches the platen roller 308, the light is irradiated by the light source 309 and the reflected light of the document 306 enters the image sensor 231.
In this state, the original is read by the image sensor 231 driven by the CCD drive board 232 shown in FIG. 3, and the CCD video signal 341 is sequentially processed by the analog board.

(Description of Analog Board)

FIG. 10 specifically shows the analog board shown in FIG. Analog board 233 is a CC
A sample and hold unit 351 for receiving a CCD video signal 341 from the D drive substrate 232 (FIG. 3) and extracting a valid image signal therefrom, and a sample and hold unit 3
Gain control unit 35 provided in the subsequent stage of 51
2, dark correction unit 353, offset control unit 3
54 and an analog-digital conversion (hereinafter, referred to as A / D conversion) section 355 and digital-analog conversion (hereinafter, referred to as D / A conversion) data 356 from the first video board 234 (FIG. 3). Is converted into a digital signal and the gain control unit 352 and the offset control unit 35
And a D / A conversion unit 357 for setting the D / A conversion number for the D.4. Image data 35 output from A / D converter 355
8 is an image processor system rack 2 shown in FIG.
46.

By the way, in this digital copying machine, before the reading of the original is started, when the power of the image scanner unit 220 shown in FIG. 5 is turned on, the black surface 313 of the reference plate 312 shown in FIG. This is to be read. Then, the offset value of the offset control unit 354 (FIG. 10) is automatically set from the CPU 331 to the D / A conversion unit 357 so that the read value at this time becomes a predetermined value (automatic offset control). : AOC).

Next, the white surface 314 of the reference plate 312 shown in FIG. 6 is put out on the platen glass and read, and the gain value of the gain control unit 352 is adjusted so that the read value at this time becomes a predetermined value. D / A from CPU 331
It is automatically set in the conversion unit 357 (automatic gain control: AGC). Since such adjustments have been made in advance, the actual original read data becomes video data having a sufficient dynamic range without saturation, is digitized by the A / D converter 355, and is converted into image data 358. It is sequentially sent to the first video board 234 (FIG. 3). Further, the dark correction unit 353 uses an output signal of a shield bit (light-shielded pixel) of the image sensor 231 to remove an output change due to the dark current.

(Description of First Video Board)

FIG. 11 shows a specific example of the first video board shown in FIG. First video board 234
Is a CCD gap correction unit 361 which receives image data 358 output from the analog substrate 233 shown in FIG. 3 and corrects a gap between the first to fifth line-type sensor chips 321 to 325 shown in FIG. It has. CCD
An RGB separation unit 362 and a dark shading correction unit 363 are provided in the subsequent stage of the gap correction unit 361. Further, the first video board 234 is provided with a control unit 364 for controlling these units 361 to 363 and a clock generation unit 365 for supplying a clock signal to these units.

The control section 364 is connected to the VME bus 245, and through this, the analog board 2 shown in FIG.
D / A conversion data 356 is sent to the second video board 235 (FIG. 3), and a control signal 367 is output to the second video board 235 at the subsequent stage. Further, the clock generation unit 365 sends a drive clock signal 368 to the analog board 233. The drive clock signal 368 is sent to the CCD drive board 232 (FIG. 3) via the analog board 233.

As described above, the image sensor 231 used in this embodiment is composed of five sensor chips 321 to 325 arranged in a staggered pattern as shown in FIG. Then, the two chip groups are shifted by the interval Δx. Therefore, five sensor chips 321-32
The CCD gap correction unit 361 performs a process of converting the data read by step 5 into data obtained by reading the same line of the document. In the CCD gap correction unit 361,
Specifically, the second and fourth sensor chips 322, 32
The data read in step 4 is delayed by using a memory and converted into read data of the same line.

FIG. 12 shows a pixel data string output from the CCD gap correction unit. The pixel data output from each of the pixels 326B, 326G, 326R shown in FIG. 9 is represented by B ₁ , G ₁ , R ₁ , B ₂ , G ₂ , R ₂ ,.
.., B _N , G _N , and R _N are repeated in the order of B (blue), G (green), and R (red) as shown in FIG.

FIG. 13 shows the output of the RGB separation unit. Here, FIG.
A blue pixel data string output from the RGB separation unit 362 is shown, and FIG. 2B is a green pixel data string. FIG. 3C shows a red pixel data string. The RGB separation unit 362 performs the process of converting the serial image data of B, G, and R shown in FIG. 12 into the pixel data strings of B, G, and R, respectively.

The pixel data separated into B, G, and R are sequentially sent to the dark shading correction unit 363 in FIG. 11, where dark shading correction is performed. The dark shading correction is performed by performing an automatic offset control and an automatic gain control operation when the power of the image scanner unit 220 (FIG. 4) is turned on prior to the reading of the original, and thereafter, the image data obtained by reading the black surface 313 is processed for each pixel. This is a process of subtracting the black plane read data stored for each pixel from the image data of each pixel when the document is actually read, which is stored in a built-in memory. The image data 369 sequentially processed by the first video board 234 in this manner is sent to the second video board 235.

(Description of Second Video Board)

FIG. 14 specifically shows the structure of the second video board. The second video board 235 stores image data 369 from the first video board 234 (FIG. 3).
, And RGs provided sequentially in the subsequent stage of the bright shading correction unit 371.
B position deviation correction unit 372, sensor position deviation correction unit 373
And the data block dividing unit 374,
To 374, and a controller 376 for controlling
Generator 37 for supplying a clock signal to 〜374
7 is provided. The control unit 376 is connected to the VME bus 245, and receives a control signal 367 from the first video board 234 (FIG. 3).
A control signal 378 is sent to the control signal.
The clock generator 377 sends a control clock signal 379 to each subsequent substrate.

The image data 369 sent to the second video board 235 is first converted to a bright shading correction section 371.
Performs bright shading correction. As with the dark shading correction, the image data obtained by reading the white surface 314 is stored in a memory for each pixel after the automatic offset control and the automatic gain control operation in the same manner as the dark shading correction. This is a process of normalizing (dividing) by the white surface read data for each pixel that has stored the image data of the pixel.

The image data subjected to the light shading correction and the dark shading correction is supplied to a light source 309 (FIG. 5).
The image data is free from the influence of the light quantity distribution and the sensitivity variation of each pixel. Also, the CPU 331 (FIG. 9)
The offset value and the gain value of the automatic offset control and the automatic gain control can be set, and the memories of the bright shading correction unit 371 and the dark shading correction unit 363 can be read and written by the CPU 331 via the VME bus 245. The CPU 331 can perform automatic offset control, automatic gain control, and light / dark shading correction control.

In the image sensor 231 (FIG. 3) used in this embodiment, the pixels 326B, 326G, and 326R are arranged in order in the main scanning direction as shown in FIG. , R, the actual document reading position is shifted. This means that the next color substrate 236
R, G, B
Needs to be corrected so that the reading position of the image is the same virtual point. This correction is performed by the RGB position shift correction unit 372.
It is. Correction of the RGB positional deviation, for example, when on the basis of the position of the pixel 326G ₂ in FIG. 8, the virtual B data location of the pixel 326G _2, the virtual R data, and the respective operations of the image data of the pixel 326B _2, B ₃ ,
It is obtained from the calculation of the image data of the pixels 326R ₁ and R ₂ .

The operation up to this point has been described with respect to the image sensor 2.
31 has been carried out as if it were one, but in fact, as already described, are using three image sensors 231 _{1 to 231 3} to read the wide original. Although these three image sensors 231 _{1 to} 231 ₃ are mounted so as to be able to read the same line (the same sub-scanning position) of the document, they actually shift in the sub-scanning direction. The sensor position shift correction unit 3 corrects this shift.
73. The sensor position shift correction is performed in substantially the same way as the CCD gap correction, by delaying the image data of each sensor by an arbitrary time using a memory, so that the image data of the _three image sensors 231 _{1 to} 231 ₃ are connected at the joint. To make adjacent images in the main scanning direction on the document.

In the case of a high-speed wide-width digital copying machine, it is necessary to process image data at high speed. However, RAMs, digital integrated circuits, and the like have limitations in high-speed operation. Therefore, in the present embodiment, the output image data of the sensor displacement correcting unit 373 is divided into a plurality of blocks in the main scanning direction by the data block dividing unit 374.

FIG. 15 shows how the output image data is divided in the main scanning direction. Here, for example, the output image data of one image sensor 231 is 2
The document 306 is divided into two blocks as shown in FIG.
Of dividing the read data to the total of six blocks b ₁ ~b _6, thereby performing parallel processing of each block b ₁ ~b ₆ in the next stage. Such image data 382 divided into blocks b ₁ ~b ₆ in the are sent sequentially to the color circuit board 236.

(Description of Color Substrate)

FIG. 16 specifically shows a color substrate. The color substrate 236 includes a hue determination unit 391 for inputting image data 382 from the second video substrate 235 shown in FIG. 3, a ghost cancel unit 392 provided in the subsequent stage of the hue determination unit 391, and a buffer memory 393. , A color editing unit 394 and a density correction unit 395. The control unit 396 includes these units 391 to 395
Is controlled. The control unit 396 is connected to the VME bus 245 and has the second
Of the control signal 378 from the video board 235 and the control signal 401 from the area recognition board 239 (FIG. 3),
Control signals 411 and 412 are sent to the digital filter board 237 (see FIG. 3) and the area recognition board 239, respectively.

The image data 382 input to the color substrate 236 is an R, G, B color image signal. The color of the image on the document is determined by the hue determination unit 391, and the color code is coded. A signal and density data are generated. The ghost cancel unit 392 at the next stage corrects the color code signal generated by the hue determination unit 391. This is because, as a result of the misregistration correction of the three colors RGB on the second video board 235 (FIG. 3), an erroneous hue judgment is performed at, for example, an edge portion of a black image on a document, and a color code other than an achromatic color is generated. This is because there are cases where
The ghost canceling unit 392 performs a process of converting a color code (ghost) for which such erroneous hue determination has been performed into an achromatic color code. Since the change pattern of the color code when a ghost occurs is known in advance, the color code is changed to an achromatic color when the pattern coincides with this pattern.

The density data and color code signal thus generated are sequentially stored in the buffer memory 393. On the other hand, the color code signal 421 obtained from the ghost cancel unit 392 is sent to the area recognition board 239 shown in FIG. In the present embodiment, various edits can be performed in real time on an area surrounded by a marker written on a document using a marker pen, and the area surrounded by the marker is detected. This is the area recognition substrate 239.

After describing the area recognition substrate 239, the remaining portion of the color substrate 236 will be described.

(Description of Area Recognition Substrate)

FIG. 17 shows a specific example of the area recognition board. The area recognition board 239 includes a marker flag generator 431 that inputs the color code signal 421 from the color board 236 described with reference to FIG. In the subsequent stage of the marker flag generation unit 431, a parallel-serial conversion (hereinafter, referred to as PS conversion) unit 432 and an area recognition unit 4 are sequentially provided.
33 and a serial-parallel conversion (hereinafter, referred to as SP conversion) unit 434. The control unit 436 controls these units 431 to 434. The control unit 436 is connected to the VME bus 245, inputs a control signal 412 from the color board 236, and sends a control signal 401 to the color board 236.

The color code signal 421 sequentially sent from the color substrate 236 is a signal for each block. First, the marker flag generation unit 431 determines whether or not the image is a marker image from a color code, and generates a marker flag if the image is a marker image. Next, the PS conversion unit 432 converts the marker flag subjected to the block processing into a signal of one line. An area recognizing section 433 recognizes an area surrounded by markers from the one-line marker flag obtained in this manner, and generates an area signal indicating the inside of the area. The generated area signal is S
The image data is again divided for each block by the P conversion unit 434, and is sequentially output to the color editing unit 394 of the color substrate 236 shown in FIG.

The buffer memory 3 is provided on the color substrate 236.
The reason why the region 93 is provided is that it takes time to recognize the region with the region recognition substrate 236, and during this time, the color code signal and the density data are stored and the region recognition substrate 236 is stored.
This is in order to match the timing with the area signal 438 from.

The block-divided area signal 438 sent from the area recognition board 239 in this way is
4 is input. The control signal 401 transmitted from the control unit 436 in FIG. 17 is input to the control unit 396. The control unit 396 stores the density data and the color code signal of the corresponding pixel in the buffer memory 3 in synchronization with the area signal 438.
93 and send it to the color editing unit 394.

The digital copying machine of this embodiment is a two-color copying machine.
The user can specify which of the colors to print. Further, it is possible to specify which color image on the document is to be erased by the drop color flag. By using this function, for example, the image data obtained by reading the marker itself does not need to be reproduced, and is therefore implicitly deleted. The function relating to the designation of two colors or the drop color can be performed only within or outside the area specified by the marker. In addition, a BKG enable flag for controlling on / off of the background removal can be generated, and it can be specified whether the background removal performed in the next stage is performed inside or outside the area. The color editing unit 394 generates these flags.

The flag, the density data and the color code signal generated in this manner are sequentially sent to the density correction section 395.
Sent to The density correction unit 395 is used to whiten (delete) the density data of the pixel on which the drop color flag is set or to perform independent density adjustment for each color (for each color code) on the document. is there. The output 439 of the sub-color flag, the BKG enable flag, the area signal, the density data, etc., thus processed is
The signals are sequentially transmitted to the digital filter substrate 237 (FIG. 3).

(Description of Digital Filter Board)

FIG. 18 specifically shows a digital filter substrate. Digital filter board 237
Is the output 439 from the color substrate 236 shown in FIG.
And a background removal unit 441 for inputting
The digital filter 442 and the sub-color flag correction unit 443 provided in the subsequent stage in order, and these units 441
And a control unit 444 for controlling. The control unit 444 is connected to the VME bus 245, receives a control signal 411 from the color board 236, and sends a control signal 446 to the halftone processing board 238 (FIG. 3).

In the digital filter board 237, the background removing unit 441 sequentially whitens the background of the document where the BKG enable flag is set and generates the BKG flag. Next, in the digital filter 442,
Edge enhancement or smoothing processing is performed according to the selected image mode. Further, when the background density of the image edge portion is raised by the smoothing process, the sub color flag correction unit 443 performs correction to make the sub color flag of the raised background pixel the same as the sub color flag of the image portion. Thus, for example, the occurrence of a black contour around the color character of the document is prevented. The sub color flag, density data, area flag, and BK thus processed
The output 448 such as the G flag is sequentially sent to the halftone processing board 238 shown in FIG.

(Description of halftone processing substrate)

FIG. 19 specifically shows a halftone processing substrate. In the halftone processing board 238, the output 448 of the digital filter board 237 shown in FIG. 18 is input to the block-line parallel conversion section 451. Subsequent to the block-line parallel conversion section 451, a reduction / enlargement section 452, a density adjustment section 454 for inputting image data 453 from the editing board 241 (FIG. 3),
A halftone processing unit 455 and a quaternary data conversion unit 456 are arranged in order. The quaternary data conversion unit 456 includes:
A diagnostic memory 458 for storing the output data 457 is connected. The control unit 461 includes these units 451,
452, 454 to 456, 458 are controlled. Further, the clock generator 462 supplies a clock signal to them. The control unit 461 sets V
A control signal 446 from the digital filter board 237 shown in FIG.
And a control signal 464 from the editing board 241 are input, and control signals 465 and 466 are sent to the editing board 241 and the data processing board 251 (FIG. 3), respectively.

By the way, in the digital copying machine of this embodiment, the image is enlarged and reduced in the sub-scanning direction by changing the conveying speed of the original similarly to the analog copying machine. This is done by processing. In this case, the parallel processing for each block greatly complicates this processing. Therefore, the halftone processing substrate 2
The 38 block-line parallel conversion unit 451 converts the image data string for each block of a total of 6 blocks into an image data string that can be processed in parallel for each line.

FIG. 20 shows the state of image data before conversion by the block-line parallel conversion unit. In FIG. (A) image data before the conversion as shown in ~ (f) the first line L for each block b ₁ ~b ₆ of first to sixth
Image data is arranged in the order of ₁ , second line L ₂ ,...

FIG. 21 shows the state of image data after conversion by the block-line parallel conversion unit. As shown in (a) to (d) of FIG.
This is converted into a line-parallel image data sequence. Therefore, for example, in FIG. 9A, the image data of the _first to _sixth blocks b ₁ to b 6 for the first line L ₁ is sequentially arranged, and subsequently, the fifth line L ₅ and the ninth line L ₉ …
.. Are rearranged. In FIG. 9B, image data is similarly rearranged in the second line L ₂ , the sixth line L ₆ , the tenth line L ₁₀ ,... The same applies hereinafter.

The image data converted by the block-line parallel conversion unit 451 in FIG.
The flag and the sub color flag are sent to the reduction / enlargement unit 452, while the area flag (area signal) 471 is
1 (FIG. 3). The image data 472 output from the reduction / enlargement unit 452 is also sent to the editing board 241.

Here, after describing the editing board 241, the remaining portion of the halftone processing board 238 will be described.

(Description of Editing Board)

FIG. 22 shows a specific configuration of the editing board. The editing board 241 is provided with an area flag (area signal) 471 from the halftone processing board 238 shown in FIG.
And a halftone processing board 2
Mirror editing unit 4 for inputting image data 472 from
82, a negative / positive editing unit 483, a density adjusting unit 484, and a halftone editing unit 485 provided in the subsequent stage of the mirror editing unit 482, and a control unit 486 that controls these units 481 to 485. Amikake Editor 4
Reference numeral 85 denotes the image data 4 stored in the density adjusting unit 454 shown in FIG.
53 is output. The control unit 486 is a VM
While being connected to the E bus 245, the control signal 465 from the halftone processing board 238 shown in FIG.
A control signal 464 is sent to the halftone processing substrate 238.

The rectangular area recognition section 481 sends an area flag (area signal) 489 to the reduction / enlargement section 452 shown in FIG. A method of designating an area will be described with reference to the area flag 489. In the digital copying machine of the present embodiment, the area can be specified by two methods.

FIG. 23 shows a state where a region is designated by enclosing it with a marker, as the first region designation method. When you draw a rectangle in the marker on the document 306, are detected respectively 4 491 corresponding to the corner _{1-491 4,} which is recognized rectangle based on, for example, that the various editing processing is performed for the internal Become.

FIG. 24 shows a method of inputting an area by coordinates as another method of specifying an area. In this method, distances x _A , y _A , x _B , and y _B of two points A and B on the original 306 from the upper left corner of the original are input from the control panel 254 shown in FIG. 2
Recognizing a rectangular area as a point, various editing can be performed on the rectangular area.

The rectangular area recognizing unit 481 generates the area flag (area signal) corresponding to the recognition of the rectangular area and each pixel in the rectangular area. Area flags (area signals) 48 sequentially processed by the rectangular area recognition unit 481
9 is sent to the reduction / enlargement unit 452 of the halftone processing substrate 238 shown in FIG. The reduction / enlargement unit 452 performs reduction / enlargement processing together with the BKG flag, the sub color flag, and the density data. The image data 472 subjected to the reduction / enlargement processing is
These are sequentially sent to the mirror editing unit 482 of the editing board 241 shown in FIG. The editing board 241 edits the image data 472 sequentially transmitted in real time.

FIG. 25 shows the state of image processing in the mirror editing unit. The mirror editing unit 482 performs a mirror image editing process in the rectangular area 501 as shown in FIG. 5A or the entire area of the image, and obtains a mirror image as shown in FIG. I have.

The negative / positive editing section 48 at the next stage in FIG.
No. 3 is for obtaining a negative-positive inverted image in which white and black are inverted. Further, the density adjusting section 484 arranged at the next stage corresponds to the copy density adjusting function on the control panel 254 (FIG. 3), and can select several types of density conversion curves for each of two output colors. The next color appearance editing unit 485 performs the color appearance process on the image using the color pattern selected from the control panel 254.
Further, the function of erasing (masking) the inside of the area and erasing (trimming) the outside of the area is also performed by the apparent editing unit 485. It goes without saying that negative / positive editing and apparent editing can also be performed on the area surrounded by the marker or on the entire image. The image data 453 sequentially processed in this manner is sent to the halftone processing board 238 in FIG.

Returning to the halftone processing substrate shown in FIG. 19, the description will be continued. The image data 453 sent from the editing board 241 described in FIG. 22 is input to the density adjusting unit 454. The function of the density adjusting unit 454 is as follows.
This is equivalent to the density adjustment unit 484 of FIG. The editing board 241 is an option board. Therefore, when the editing board 241 is not mounted, the density adjustment is performed by the density adjusting unit 454 of the halftone processing board 238. When the editing board 241 is mounted, the density adjusting unit 4
At 54, nothing is processed. That is, in the digital copying machine of this embodiment, when the editing board 241 is mounted, the density of the apparent pattern can be selected from the control panel 254 using the editing board 241. Therefore, in order to prevent the selected density from being changed by the copy density adjustment of the control panel 254, the density adjustment is performed before the apparent editing process.
When one is mounted, the density adjustment is performed using the internal density adjustment unit 484.

The halftone processing unit 455 in FIG.
The multivalued image data is converted into quaternary data based on area gradation. The quaternization means that the density of one pixel is set to four gradations of white, first gray, second gray that is darker than the first gray, and black. The data processed in this manner is converted into image data for a plurality of pixels (a quaternary density data and a sub color flag) by a quaternary data conversion unit 456.
Is converted into output data 457, and sequentially output to the data processing board 251 outside the image processor system rack 246 as shown in FIG. The diagnostic memory 458 stores the output data 457 of the quaternary data converter 456 for self-diagnosis.

The data processing board 251 shown in FIG. 3 sends the image data sent from the halftone processing board 238 to the page memory board 253 and stores it in the page memory. When all the originals have been read in this way, the first one shown in FIG.
Of the second CPU board 252 (FIG. 3) through the control data line 257.
Send information to U. Then, C of the second CPU board 252
The PU is connected to the print unit 221 through the control data line 267.
The control unit 266 in FIG. 4 is informed that the sheet has been conveyed and that the image data is stored in the page memory.

Control unit 2 of print unit 221 in FIG.
Reference numeral 66 denotes a control sheet for conveying a predetermined sheet and a control signal 256.
Thus, the image data 255 in the page memory is read from the data processing board 251 (FIG. 3) at a predetermined timing. The read image data 255 is stored in the data separation unit 26.
1 (FIG. 4). The data separation unit 261 has a function of sorting the density data according to the sub color flag. For example, when the sub color flag is “0”, the density data is sent to the first color image data memory 262 and the second color image data memory 263 To send white data. When the sub color flag is "1", the density data is sent to the second color image data memory 263, and the first color image data
The white data is sent to 62. The printing unit 221 prints using the xerography technique, and the developing unit and the like have two for the first color and the second color. Then, the two-color image on the photoreceptor (drum) is transferred to the same sheet and fixed. Semiconductor lasers for exposure are also provided for the first color and for the second color, respectively. The first color laser drive unit 264 and the second color laser drive unit 265 drive and control these based on the image data.

(Overview of Self-diagnosis System)

The overall configuration of the digital copying machine of this embodiment has been described. Next, an outline of the self-diagnosis system employed in this embodiment will be described.

FIG. 1 shows an outline of a self-diagnosis system to which the self-diagnosis method of the processing unit group of this embodiment is applied. In this embodiment, the image processor system rack 2
First video board 23 arranged at 46 (see FIG. 3)
4. The self-diagnosis of the image processing board group including the second video board 235, the color board 236, the digital filter board 237, the halftone processing board 238, and the area recognition board 239 is performed. At the time of this self-diagnosis, the memory 601 used for image processing on the first video board 234 is used as a pattern generator, and the halftone processing board 23 arranged at the last stage is used.
The image processing result for the pattern output from the pattern generator is stored in a diagnostic memory 458 provided on the memory 8. Then, the stored image processing result is compared with a previously prepared pattern to check whether image processing has been performed normally, and self-diagnosis is performed on the entire image processing board groups 234 to 239 and 241. Is

In this embodiment, a memory arranged in the dark shading correction section 363 of the first video board 234 shown in FIG. 11 is used as the memory 601. The dark shading memory 601 can be directly read and written by the CPU 331 via the VME bus 245 as described above. Therefore,
By storing a program for self-diagnosis in the ROM 333 shown in FIG.
34 to 239 and 241 can be executed.

In this embodiment, these image processing board groups 234 to
In addition to the self-diagnosis for the whole 239 and 241, if a failure is found as a result of this diagnosis, the image processing board group 2
There is a separate diagnosis to check which of 34-239, 241 is faulty. For the latter self-diagnosis, a pattern is set in order from the last of the image processing board groups 234 to 239 and 241, and in this state, the data stored in the diagnostic memory 458 is checked to determine the corresponding board. Is to be identified. In addition, in the present embodiment, the image processing board groups 234 to 239, 24
It is also checked whether or not various control signals to be input to 1 are normally input.

(Self-diagnosis of entire image processing board group)

FIG. 26 shows details of a dark shading correction unit used as a pattern generator when checking the entire image processing board group.
First, the configuration of the dark shading correction unit 363 will be described, and then the control operation at the time of self-diagnosis will be described.

The dark shading correction section 363 includes an address generation section 611 for generating address information, and an address bus buffer 613 for transmitting address information supplied from the VME address bus 612. Address information selected by the first switch 614 is supplied to the address terminal AD of the dark shading memory 601. Dark shading memory 60
One data terminal DA is connected to a VME data bus 616 via a data bus buffer 615. Also,
This data terminal DA is connected to one side of the buffer 617 and the second switch 618. The buffer 617 is enabled when image data 619 before shading correction is temporarily stored, and disabled when the CPU 331 (FIG. 1) reads the image data 619 or reads an image on a document.

The image data 619 and the data for correction output from the data terminal DA of the dark shading memory 601 are input to a subtracter 621, and the two are subtracted to output image data subjected to dark shading correction. ing. A third switch 623 is arranged on the output side, and the image data corrected in the dark shading or the data in the dark shading memory 601 by the switching operation of the second and third switches 618 and 623 is stored in the third switch 623. Is output as the data 624 from the switch 623 of FIG.

First, a case where dark shading correction is performed by the dark shading correction unit 363 having such a configuration will be described. As described above, the dark shading correction is performed when the power of the image scanner unit 220 (FIG. 4) is turned on. At this time, both the address bus buffer 613 and the data bus buffer 615 are disabled. Buffer 61
7 is enabled. The first switch 614 is provided with an address generator 611 as shown by a solid line in FIG.
Are connected to the dark shading memory 601.

In this state, reading of the black surface 313 of the reference plate 312 shown in FIG. 6 is performed. At this time, address information for the dark shading memory 601 is generated by the address generation unit 611 corresponding to the position of the pixel to be read in the main scanning direction. The dark shading memory 601 fetches dark shading data in accordance with the address information. The captured dark shading data is read out corresponding to the position in the main scanning direction when a normal document is read, and the dark shading correction is performed by the subtracter 621 subtracting this from the image data 619. become.

Next, the operation at the time of self-diagnosis will be described. During the self-diagnosis, the buffer 617 is disabled and the address bus buffer 613 and the data bus buffer 615 are both enabled. Also, the first
The third to sixth switches 614, 618, 623 are all changed from the switching state shown by the solid line to the switching state shown by the solid line. Thus, as shown in FIG.
A desired pattern for self-diagnosis can be stored in the dark shading memory 601 via the ME bus 245.

Thus, the dark shading memory 6
01 with the pattern for self-diagnosis stored in CP
U331 can instruct the control unit 364 shown in FIG. 11 to start self-diagnosis. When the CPU 331 issues this instruction, the control unit 364 switches only the first switch 614 to the solid line side in FIG. 26 again. As a result, the address information is output from the address generator 611, and the self-diagnosis pattern is output to the data 62 without passing through the subtractor 621.
4 is output to the next stage.

On the other hand, the image processing substrate group 234 shown in FIG.
Halftone processing substrate 1 arranged at the last stage of
Image processing data as a result of performing various processes on the self-diagnosis pattern is temporarily loaded into the diagnostic memory 458 provided on the. CPU3
31 issues a data capture start instruction to the control unit 461 in the halftone processing board 238 shown in FIG. 19, and transmits image processing data stored in the diagnostic memory 458 via the VME bus 245. And can be read. Therefore, the CPU 331 can check whether normal image processing data is stored in the diagnostic memory 458.

That is, when the CPU 331 causes the dark shading memory 601 to output a pattern for self-diagnosis, if any data is stored in the diagnostic memory 458, all of the image processing board groups 234 to 238 are normal. Whether or not there is a failure can be diagnosed by checking whether or not such data is stored. Then, when it is determined that any of the image processing board groups 234 to 238 is out of order, the process proceeds to an operation for specifying a specific board that has failed.

(Individual substrate of image processing substrate group
self-diagnosis)

An operation for determining which of the image processing board groups 234 to 238 and 241 is out of order will be described. Now, it is assumed that the editing board 241 shown in FIG. 1 is not mounted on the image processor system rack 246. Since the halftone processing substrate 238 shown in FIG. 19 is disposed at the end of the image processing substrate groups 234 to 238, self-diagnosis is first started. In the present embodiment, this diagnosis is executed using the density adjustment unit 454 in the halftone processing substrate 238.

FIG. 27 shows how the density is adjusted by the control panel. By operating the control panel 254 shown in FIG. 3, various curves of conversion characteristics of output density data with respect to input density data can be set as shown in FIG. Such setting or changing of the density characteristic can be easily realized by preparing a look-up table 631 as shown in FIG. That is, a predetermined area of the memory is allocated as the look-up table 631, and output density data corresponding to various input density data is written therein. If the input density data is given as address information to the address input terminal AD of the look-up table 631, output density data 633 having desired density characteristics can be obtained from the data output terminal DA.

Therefore, if exactly the same value is written to all the addresses of the lookup table 631, no matter what value the input density data 632 takes, the output density data 6
33 is data of a constant value at all times. In other words, even if a circuit arranged earlier than this fails and unexpected address information is given to the lookup table 631, the output density data 633 has a constant value.
The look-up table 631 in which the same value is written can be considered as a kind of the same pattern generator.

The image processing data obtained when the halftone processing unit 455 and the quaternary data conversion unit 456 as shown in FIG. 19 are applied to arbitrary predetermined density data are, for example, normal digital copiers. In this case, the same data can be used to know in advance. Therefore, the image processing data in the normal case is stored in, for example, the RO shown in FIG.
By storing the data in M333 and comparing it with the image processing data stored in the diagnostic memory 458, it is possible to determine whether or not a failure has occurred in the circuit after the density adjustment unit 454 in FIG. . That is, if the determination results do not match, it can be determined that the halftone processing substrate 238 has failed.

If the result of this determination is that they match, the original data for density adjustment is stored again in the look-up table 631 used for self-diagnosis. Then, this time, the editing board 241 is connected to the halftone processing board 238, and the apparent editing unit 485 (FIG. 22) is used as a pattern generator. This makes it possible to easily determine whether the previous processing unit is normal or abnormal. At this time, if it is determined that there is an abnormality, it means that a failure has occurred between the previous density adjusting unit 454 shown in FIG. 19 and the apparent editing unit 485 in FIG. In this case, it is determined that either the halftone processing board 238 or the editing board 241 has failed.

The halftone editing unit 485 can perform a masking process for reducing the density of an image to zero, and can set an arbitrary density by replacing an image with a halftone density. Therefore, by using this characteristic, it can be used as a pattern generator.

Hereinafter, the image processing board group 2 is formed by the same procedure.
Individual self-diagnosis of 34 to 238 will be performed. The processing blocks that can be used as a pattern generator in this way include the image processing boards 234 to 23.
8, 241. For example, the editing board 241 (FIG. 2)
2) Density adjustment unit 484, digital filter board 23
7 (FIG. 18), the digital filter 442, the background removal unit 441, and the density correction unit 39 of the color substrate 236 (FIG. 16).
5. The bright shading correction unit 371 of the second video board 235 (FIG. 14) is such.

Therefore, it is set so that constant density data is sequentially output to these portions regardless of the input density, and the image processing data stored in the diagnostic memory 458 is checked each time. Thus, the failed board can be specified as one of the two predetermined boards.

Although the above description has been made with respect to density data, a faulty board can be specified in the same manner by using a sub-color flag. In this case, processing blocks that can be used as a pattern generator include:
The density adjustment unit 454 shown in FIG. 19, the halftone processing editing unit 453 shown in FIG. 22, the density adjustment unit 484, the negative / positive editing unit 483, the density correction unit 395 of the color substrate 236 (FIG. 16), the color editing unit 394, The hue determination unit 391 and the marker flag generation unit 431 of the area recognition board 239 (FIG. 17) can be given. In the latter case, another predetermined image data is stored and checked in the dark shading memory 601 corresponding to each of R, G, and B.

(Check of control signal)

As described above, the image processing board groups 234 to 239, 2
I explained self-diagnosis of failure of 41 itself,
Next, checking of various control signals used for these will be described.

FIG. 29 shows the relationship between the sample clock and the image data in normal image processing. When normal image processing is performed using the image processing board groups 234 to 239 and 241, the image data 641 and the sample clock 642 shown in FIG. 29A correspond to one pixel and one pixel.

FIG. 30 shows the relationship between the line synchronization signal and the sample clock in the normal image processing. FIG. 7A shows a line synchronization signal 643 for synchronizing each line, and FIG. 7B shows a sample clock 642.

FIG. 31 shows the relationship between the page synchronization signal and the line synchronization signal in the ordinary image processing. FIG. 7A shows a page synchronization signal 644 for synchronizing each page, and FIG. 7B shows a line synchronization signal 643.

The sample clock 642, the line synchronizing signal 643, and the page synchronizing signal 644 are input from the first video board 234 (FIG. 11) as a control signal 367 to the second video board 235. 378 is transferred to the color substrate 236 shown in FIG. In the same manner, the data is sequentially transferred to the halftone processing substrate 238. The halftone processing substrate 238 shown in FIG.
Then, this is output as the control signal 466.

If any of these control signals 367 to 466 is passed to a failed board in the middle of the image processing board groups 234 to 238, there is a possibility that the control signal will not be passed to subsequent boards. As a result, an erroneous determination may be made that the halftone processing substrate 238 has failed. Therefore, in the self-diagnosis system of this embodiment, each of the substrates 235 to 239 after the second video substrate 235
It is checked whether or not these control signals are input to the CPU.

FIG. 32 shows an example of a circuit for checking the input of a control signal. The control signal check circuit 651 includes a counter 652 and a flip-flop circuit 653. The reset terminal R of the counter 652 and the flip-flop circuit 653 has
Is supplied with a reset signal 655 at the timing when the CPU 331 checks the control signals 367 to 466 (hereinafter collectively referred to as control signals 654), and resets them. With these reset, the CPU 331 reads the output signal 657 output from the output terminal Q of the flip-flop circuit 653 through the VME bus 245. At this time, since the flip-flop circuit 653 has been reset, the output signal 657 should be at the L (low) level.

The control signal 654 is supplied to the input terminal IN of the counter 652. Therefore,
If the control signal 654 is normally transmitted to the corresponding substrate, the counter 652 outputs a carry (carry) signal 658 from its output terminal OU after a predetermined time has elapsed due to the counting operation. The carry signal 658 is input to the clock input terminal CK of the flip-flop circuit 653. Accordingly, the flip-flop circuit 653 is set by this, and the output signal 657 changes from the L level to the H (high) level. Since the frequency of the control signal 654 is known in advance, the CPU 331 checks the output signal 657 again after a certain period of time determined from the relationship with the count value until the counter 652 performs a full count.
Whether it is normal or abnormal can be determined.

FIG. 33 shows the flow of the control signal check using the control signal check circuit. CP
U331 is a counter 65 of a control signal check circuit 651 (FIG. 32) prepared on a specific board to be diagnosed.
The reset signal 655 is supplied to both the flip-flop circuit 2 and the flip-flop circuit 653 (step S101). Then, the state of the output signal 657 of the flip-flop circuit 653 is checked (step S102). If the output signal 657 is not at the L level (N), there is a high possibility that the control signal check circuit 651 itself has a problem. A flag for displaying an abnormality in the circuit is turned on (step S103).

On the other hand, in step S102, the output signal 657 is output.
Is low level (Y), the control signal 65
After the time during which the flip-flop circuit 653 is set by the output of the carry signal 658 by the count of 4 elapses (step S104; Y), the output signal 657 is checked again (step S105). (Y), the control signal 65 for the substrate
A flag indicating that the number 4 is abnormal is turned on (step S106). On the other hand, if the output signal 657 has changed to the H level (step S105; N), a flag indicating that the control signal 654 for the substrate is normal is turned on (step S107).

When the check of the control signal 654 for one board is completed as described above, the same check is performed for the other boards. The state of each flag is displayed together with the results of other self-diagnosis, for example, on the control panel 254 shown in FIG.

In the above-described control shown in FIG. 33, only the presence or absence of the supply of the control signal 654 is checked. However, the CPU 331 monitors the time when the output signal 657 changes from the L level to the H level. Thus, the outline of the frequency of the control signal 654 can be determined.
This makes it possible to detect a failure such as a case where a portion of the control signal 654 is missing (clock loss).

When the frequency of the control signal 654 is diagnosed as described above, the counter 65 is used to increase the accuracy.
It is effective to increase the number of counts until the carry signal 658 is output by increasing the number of stages of 2, for example. Further, a control signal check circuit 651 as shown in FIG.
2 may be used as a preset counter so that the count number until the carry signal 658 is output can be adjusted. Of course, although not related to this frequency measurement, the control signal check circuit 651 is arranged only on the first CPU board 244 (FIG. 9), and the control signal 654 input to each board to be checked is transmitted to the first CPU board 244. The self-diagnosis may be performed intensively at one place by commonly drawing in the substrate 244.

(Check on Two-Dimensional Image Processing)

The self-diagnosis of the image processing board groups 234 to 238 relating to the image processing has been described above.
There are various types of image processing. For example, the digital filter 442 shown in FIG. 18, the halftone processing unit 455 shown in FIG. 19, or the halftone editing unit 485 shown in FIG. 22 processes image data in two dimensions. Therefore, these circuit parts 442, 455, 4
In order to confirm whether or not the process of step 85 is performed normally, it is necessary to store and check several lines of image data in the sub-scanning direction of the document in the diagnostic memory 458 shown in FIG. . However, a memory element such as a RAM (random access memory) has a fixed memory capacity, and in order to store image data for several lines, a large number of memory elements having a relatively small memory capacity are used. It is necessary to use a large-capacity memory device at high cost.

FIG. 34 shows a configuration of a circuit used in this embodiment for processing image data two-dimensionally using a memory element having a relatively small capacity. The memory element 661 is a relatively small-capacity memory element capable of storing, for example, one line of image data. The output data (image data) 457 of the quaternary data conversion unit 456 is input to the data input terminal DA from the halftone processing board 238 shown in FIG.
This image data 457 is written at an address corresponding to the address information 662 input to the address input terminal AD. Therefore, by controlling this writing, data of an arbitrary line of the image data 457 is fetched, and this is sequentially repeated, thereby enabling two-dimensional processing of the image data.

Here, the generation of the address information 662 is performed by the address counter 664, and the sample clock 642 shown in FIGS. 29 and 30 is used as a clock signal for sequentially counting up the address. . Further, in order to specify image data of a specific line of a specific page, a page synchronization signal 644 (see FIG. 31) and a line synchronization signal 643 (see FIG. 30) are input to the AND gate 665. Then, while the specific page synchronization signal 644 is at the H level, the line synchronization signal 6
43 is output from an AND gate 665, which is input to a clock input terminal CK of a line counter 666 to count the number of lines.

As a result, when a desired line arrives, a carry signal 667 is output from the line counter 666, and this is supplied to the clock input terminal CK of the flip-flop circuit 668 to be set. When the flip-flop circuit 668 is set, an H-level set signal 669 is output from its output terminal Q and input to the enable terminal EN of the address counter 664. That is, from this point on, the address counter 6
64 is enabled and starts counting the sample clock 642, and sends its output to the memory element 661 as address information 662. As a result, the image data 457 is written for one line.

At this time, the address information 662 is also input to the store end determination section 671. Store end determination unit 671
Is for prohibiting a situation in which data is written to an area other than the area where the image data 457 is input in the memory element 661. This store end determination unit 671
Monitors the address information 662 output from the address counter 664, and outputs an end signal 672 when the address information 662 reaches an area outside the area where the image data 457 is written. The end signal 672 is input to the OR gate 675 together with the signal 674 obtained by inverting the logic of the page synchronization signal 644 by the inverter 673.
When 2 and 674 are output, the flip-flop circuit 668 is output.
A reset signal 676 is output to the reset terminal R of. Since the flip-flop circuit 668 is reset by the output of the reset signal 676, the address counter 664 is disabled, and the writing of the image data 457 ends.

(Overall Flow of Self-Diagnosis)

Finally, the flow of the self-diagnosis in this embodiment will be described. The self-diagnosis of the control signal 654 has already been described with reference to FIG.

FIG. 35 shows a flow for performing an overall check of the image processing board group. When the power of the digital copying machine is turned on, the first copying machine shown in FIG.
-The third switches 614, 618, 623 are switched to the dotted line side, and the buffer 617 is disabled (step S201). Next, the CPU 331 loads predetermined data into the dark shading memory 601 (Step S202). In this way, the self-diagnosis pattern is stored in the dark shading memory 601.

As a result, the CPU 331 instructs the start of the self-diagnosis (step S203). As a result, the first switch 614 is switched to the solid line side in FIG. 26 (step S204), and a pattern for self-diagnosis is read from the dark shading memory 601 and the image processing board group 234 is read.
To 238. As a result, the diagnostic memory 4
The data stored in 58 is read and stored in RAM 334 of first CPU board 244 shown in FIG. 9 (step S206). The CPU 331 compares the data stored in the RAM 334 with the processing result data prepared in advance in the ROM 333 (FIG. 9) when the image processing is normal, and determines whether or not they match (step S2).
07). As a result, if they match (Y), all of the first to third switches 614, 618, 623 are switched to the solid line side, the buffer 617 is enabled (step S208), and the self-diagnosis is terminated (END). If no data match is found in step S207 (N), abnormality analysis processing is executed (step S209).

FIG. 36 shows the flow of the abnormality analysis processing in step S209 of FIG. FIG.
If no data match is found in step S207, the control signal 654 is first checked as described with reference to FIG. 33 (step S301). As a result,
If abnormal (step S302; N), a failure of the corresponding board is displayed on the control panel 254 (step S303).

On the other hand, if there is no abnormality in the control signal 654 (step S302; Y), the CPU 331 proceeds to the control section 364 of the first video board 234 shown in FIG.
The reading of the pattern for the self-diagnosis is completed for the
The data acquisition of the diagnostic memory 458 is ended for the device 1 (step S304). Then, the last board (halftone processing board 238) is designated for individual diagnosis (step S305).

Then, processing for turning the image data into white or black is set for the board (step S306), and the reading of the data is started (step S3).
07). Then, the data stored in the diagnostic memory 458 is read and stored in the RAM 334 of the first CPU board 244 shown in FIG. 9 (Step S308). CP
U331 is the data stored in the RAM 334 and the ROM 3
A comparison is made with the processing result data in the case where the image processing prepared in advance for the individual diagnosis in step 33 (FIG. 9) is normal, and it is determined whether or not they match (step S309). As a result, if they match (Y), it is checked whether it is the final board (substrate in the front row) to be subjected to self-diagnosis (step S310), and if not (N), image processing is 1 Designate a board located immediately before (step S3
11). Then, returning to step S306, the self-diagnosis of the board is executed (steps S306 to S310).

On the other hand, if the processing results do not match in step S309 (step S304;
N), a code indicating the failure of the board that has undergone the self-diagnosis is displayed on the control panel 254 (step S).
312). On the other hand, if the processing results match the final board as a result of the self-diagnosis sequentially, and no abnormality of the digital copying machine is detected (step S
310; Y), first or second video board 234, 2
Since there is a high possibility that the failure has occurred, a code indicating that one of these has failed is displayed on the control panel 254 (step S313).

Then, each of the above display operations (step S3)
03, S312, S313) are started,
The third switches 614, 618, and 623 are all switched to the solid line side, the buffer 617 is enabled (step S314), and the self-diagnosis is ended (END).

Modified example

In the embodiment of the present invention described above, blocks for processing actual read data are used as a pattern generator. However, a latch circuit constituting an input unit of each substrate as a processing unit group is used. It is also possible to generate a specific pattern and use it for checking.

FIG. 37 shows a general circuit for image processing as an example of a circuit that can be used for self-diagnosis. Here, a plurality of flip-flop circuits (only one is shown in the figure) 702 exist in parallel on the address input terminal AD side of a look-up table (LUT) 701 constituted by a RAM, and address information 703 is supplied from these flip-flop circuits. It is supposed to be. Similarly, a plurality of flip-flop circuits (only one is shown in the figure) 704 exist on the data output terminal DA side of the look-up table 701, and data 705 is output from these flip-flop circuits. A clock signal 706 is supplied to a clock input terminal CK of each of the flip-flop circuits 702 and 704.

As described above, in the circuit shown in FIG. 37, the flip-flop circuits 702 and 704 are arranged on the input side and the output side of the lookup table 701, respectively. This is because the look-up table 701 requires a finite access time, and if processing is performed in multiple stages without using these flip-flop circuits 702 and 704, the time required to output valid data is increased. Is so short that processing cannot be performed at the end. The flip-flop circuits 702 and 704 used for such a role usually have terminals for clearing and setting outputs regardless of their respective inputs. Therefore, by controlling these terminals, a specific pattern for self-diagnosis can be created.

In the embodiment described above, the data is stored in the diagnostic memory 458 shown in FIG. 1 and the like and the data is checked. However, such a memory does not need to be specially prepared. It is also possible to substitute a page memory.

As for the check of the control signal 654, the CPU 331 may directly read the count value of the counter 652 without using the flip-flop circuit 653 shown in FIG. Further, a one-shot multivibrator may be used in place of the counter 652, and the output may change unless a control signal 654 having a predetermined cycle is input. In this case, the control signal 654 can be checked by determining whether or not the output of the one-shot multivibrator is always kept at a predetermined signal level.

[0151]

As described above, according to the first aspect of the present invention, since the entire system is first diagnosed and then an individual diagnosis is made when a failure is found, an efficient self-diagnosis can be performed. There is.

Further, according to the second aspect of the present invention, since the entire system is first diagnosed and then individual diagnosis is performed when a failure is found, efficient self-diagnosis can be performed. If a failure is found by the overall diagnosis, the individual diagnostic data is set in order from the last processing unit in the processing unit group, and the processed data obtained by processing the individual diagnostic data is compared with the check data. Therefore, it is possible to easily check a processing unit having a failure while suppressing an increase in hardware scale, and to reduce the cost of the apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a principle configuration of a self-diagnosis system to which a self-diagnosis method of a processing unit group according to an embodiment of the present invention is applied.

FIG. 2 is a perspective view showing an external appearance of a digital copying machine having a self-diagnosis system according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of an image scanner unit according to the present exemplary embodiment.

FIG. 4 is a block diagram illustrating a specific configuration of a printing unit according to the present exemplary embodiment.

FIG. 5 is a schematic configuration diagram illustrating a document reading portion of the image scanner unit illustrated in FIG. 3;

FIG. 6 is a perspective view showing a part of a configuration of a reference plate shown in FIG.

FIG. 7 is a plan view illustrating an arrangement structure of an image sensor used in the present embodiment.

FIG. 8 is a plan view illustrating a state of a pixel array in a chip constituting the image sensor of the present embodiment.

FIG. 9 is a block diagram specifically illustrating a circuit configuration of a first CPU board of the present embodiment.

FIG. 10 is a block diagram specifically showing a circuit configuration of the analog board of the present embodiment.

FIG. 11 is a block diagram specifically showing a circuit configuration of a first video board of the present embodiment.

FIG. 12 is an explanatory diagram illustrating a pixel data string output by a CCD gap correction unit in the present embodiment.

FIG. 13 is an explanatory diagram illustrating an output of an RGB separation unit in the present embodiment.

FIG. 14 is a block diagram specifically showing a circuit configuration of a second video board of the present embodiment.

FIG. 15 is an explanatory diagram illustrating a state of division of output image data in the main scanning direction in the present embodiment.

FIG. 16 is a block diagram specifically showing a circuit configuration of a color substrate of the present embodiment.

FIG. 17 is a block diagram specifically illustrating a circuit configuration of an area recognition board according to the present embodiment.

FIG. 18 is a block diagram specifically showing a circuit configuration of the digital filter substrate of the present embodiment.

FIG. 19 is a block diagram specifically showing a circuit configuration of a halftone processing substrate of the present embodiment.

FIG. 20 is an explanatory diagram illustrating a state of image data before conversion by a block-line parallel conversion unit in the present embodiment.

FIG. 21 is an explanatory diagram illustrating a state of image data after conversion by a block-line parallel conversion unit in the present embodiment.

FIG. 22 is a block diagram specifically showing a circuit configuration of an editing board of the present embodiment.

FIG. 23 is an explanatory diagram showing a case where an area is designated by surrounding it with a marker in the present embodiment.

FIG. 24 is an explanatory diagram showing a method of inputting an area by coordinates in the present embodiment.

FIG. 25 is an explanatory diagram illustrating a state of image processing in the mirror editing unit in the present embodiment.

FIG. 26 is a block diagram illustrating details of a dark shading correction unit according to the present embodiment.

FIG. 27 is a density characteristic diagram illustrating a state of density change when a control panel is operated in the present embodiment.

FIG. 28 is a block diagram showing a lookup table used for setting and changing density characteristics in the present embodiment.

FIG. 29 is a timing chart showing a relationship between a sample clock and image data in normal image processing in the present embodiment.

FIG. 30 is a timing chart showing a relationship between a line synchronization signal and a sample clock in normal image processing in the present embodiment.

FIG. 31 is a timing chart showing a relationship between a page synchronization signal and a line synchronization signal in normal image processing in the present embodiment.

FIG. 32 is a block diagram illustrating an example of a circuit for checking input of a control signal in the present embodiment.

FIG. 33 is a flowchart showing how a control signal is checked using a control signal check circuit in the present embodiment.

FIG. 34 is a block diagram illustrating a circuit that enables two-dimensional processing of image data in the present embodiment.

FIG. 35 is a flowchart illustrating control for performing an overall check of the image processing substrate group according to the present embodiment.

FIG. 36 is a flowchart showing a control signal check and individual diagnosis contents when a part of the image processing board group of the present embodiment is out of order.

FIG. 37 is a block diagram illustrating an example of a circuit that can be used for self-diagnosis according to the present embodiment.

FIG. 38 is a block diagram illustrating a main part of an apparatus to which a conventionally proposed self-diagnosis method is applied.

FIG. 39 is a plan view showing contents displayed on a display device of a user interface at the time of self-diagnosis in a conventionally proposed device.

FIG. 40 is a block diagram showing a circuit configuration when a self-diagnosis is performed on a D / A converter in a conventionally proposed device.

[Explanation of symbols]

231, an image sensor; 234, a first video board;
235: second video board, 236 ... color board, 23
7 digital filter board, 238 halftone processing board, 239 area recognition board, 241 editing board, 244
... First CPU board, 246 ... Image processor system rack, 253 ... Page memory board, 254 ... Control panel, 331 ... CPU, 332 ... Timer, 3
33 ROM, 334 RAM, 339 clock generator, 363 dark shading corrector, 458 diagnostic memory, 601 dark shading memory, 611 address generator, 613 address bus buffer, 614
... first switch, 615 ... data bus buffer, 618
.., A second switch, 621, a subtractor, 623, a third switch, 631, a lookup table, 642, a sample clock, 643, a line synchronization signal, 644, a page synchronization signal, 651, a control signal check circuit, 652: counter, 661: memory element, 664: address counter, 666: line counter, 671: store end determination unit, 702, 704: flip-flop circuit

Claims (2)

[Claims] 1. A self-diagnosis method for a processing unit group including a plurality of processing units for sequentially processing signals, the method comprising: performing a self-diagnosis on the entire processing unit group; When a failure is found as a result of the self-diagnosis, individually diagnosing which of the processing units in the processing unit is out of order. 2. A self-diagnosis method for a processing unit group consisting of a plurality of processing units for sequentially processing signals, wherein the first processing unit in the processing unit group sequentially performs diagnostic processing by a subsequent processing unit. Generating data in a diagnostic data generator disposed in the first processing unit; and processing data obtained by sequentially processing the diagnostic data and a check obtained when all of the plurality of processing units are normal. Comparing any of the plurality of processing units with each other.If the comparison results do not match, determining that any of the plurality of processing units is faulty.If it is determined that any of the plurality of processing units is faulty, Generating individual diagnostic data in order from the last processing unit of the processing unit group to the first processing unit by the individual diagnostic data generating units arranged in each of the plurality of processing units; A step of comparing the processed data obtained by processing the individual diagnostic data with the individual check data obtained when all the processing units subsequent to the processing unit in which the individual diagnostic data is generated are normal; Determining that a circuit between the individual diagnostic data generator that generated the individual diagnostic data when the individual diagnostic data was generated and the individual diagnostic data generator that generated the individual diagnostic data immediately before the failure has failed. A self-diagnosis method for a processing unit group characterized by the following.