JP2001111391A - Asic and delay compensating method in the same and automatic arranging and wiring method in the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of any malfunction at the time of the deterioration of the drive capability of a clock driver due to the fluctuation of a wafer process or the like when a circuit part with a small hold margin is present in an ASIC. SOLUTION: This ASIC is provided with a delay monitor circuit constituted by serially connecting plural clock drivers having the same constitution as that of a standard clock driver to be used in the same chip and the clock drivers whose drive capabilities can be corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ASIC having a function of preventing a malfunction that occurs in a circuit portion having a small hold margin due to a lack of drive capability of a clock driver due to a variation in a wafer process, and causes the malfunction. ASIC for correcting clock signal delay
And an automatic placement and routing method in an ASIC for preventing a malfunction occurring in a circuit portion having a small hold margin in a design stage in advance.

[0002]

2. Description of the Related Art FIG. 16 is a configuration diagram showing a general circuit portion in an ASIC. In FIG. 16, reference numeral 121 denotes a latch circuit, 122 denotes a clock driver, and 123 denotes a data input driver. DATA_IN is input data, CLK is a clock signal for latch, DATA_OU
T is output data after latching.

[0003] Next, the operation of the above circuit portion in the ASIC will be described. FIG. 17 is a timing chart showing the timing of each signal during normal operation. FIG. 18 is a timing chart showing the timing of each signal when a malfunction occurs due to insufficient driving capability of the clock driver. As shown in FIG. 17, during a normal operation, the rising edge of the latch clock signal CLK occurs while the input data DATA_IN is at the H level, the H level is latched, and the output data DATA_O is latched.
The H level is output as UT. However, if the drive capability of the clock driver is reduced due to the fluctuation of the wafer process and the rise time of the clock is extended, the input portion of the circuit portion having a small hold margin as shown in FIG. Data DATA_I
The latch clock signal CLK should rise while N is at the H level because the input data DATA_IN
Changes to the L level, and then the latch clock signal CLK
Rises, the L level is latched, and erroneous data is output as output data.

[0004]

In a conventional ASIC design, particularly in an ASIC that can be designed and implemented independently by a user such as a hardware-compatible semi-custom LSI, a circuit portion having a small hold margin as described above is required. In many cases, when a circuit portion having a small hold margin exists, the rise time of the clock signal is extended when the drive capability of the clock driver is reduced due to a variation in the wafer process or the like. There is a problem that a malfunction occurs in a circuit portion having a small hold margin, and a chip in which such a malfunction occurs is discarded, thereby lowering a chip manufacturing yield.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an ASIC which can prevent a decrease in product yield due to a variation in a wafer process or the like even when a circuit portion having a small hold margin exists. The purpose is to gain.

It is another object of the present invention to provide a delay correction method for an ASIC that can correct a delay of a clock signal that causes a malfunction even when a circuit portion having a small hold margin exists.

Another object of the present invention is to provide an automatic placement and routing method in an ASIC for preventing a malfunction occurring in a circuit portion having a small hold margin at a design stage in advance.

[0008]

An ASIC according to the present invention
Has a delay monitor circuit configured by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip, and a clock driver whose drive capability can be corrected. It was made.

An ASIC according to the present invention includes a plurality of clock drivers including a voltage source, a P-channel transistor, an N-channel transistor, and a ground,
The drain of the P-channel transistor and the drain of the N-channel transistor of each clock driver can be arbitrarily connected to a clock signal line.

An ASIC according to the present invention includes a plurality of clock drivers having different drive capabilities, and each of the clock drivers can be arbitrarily connected to a clock signal line.

An ASIC according to the present invention includes a plurality of clock drivers having different driving capabilities and a plurality of transmission gates respectively arranged between each clock driver and a clock signal line. .

An ASIC according to the present invention includes a variable voltage source capable of changing a voltage level based on a selection signal, a P-channel transistor, an N-channel transistor, and a clock driver including a ground portion.

An ASIC according to the present invention includes a clock driver including a voltage source, a P-channel transistor, an N-channel transistor, and a ground, and different voltage levels based on a selection signal for the gates of the P-channel transistor and the N-channel transistor. And a variable voltage source for gate capable of applying the above voltage.

An ASIC according to the present invention includes a delay monitor circuit formed by connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip in series, and a drive capability corrected. And a possible data input driver.

An ASIC according to the present invention includes a plurality of data input drivers each including a voltage source, a P-channel transistor, an N-channel transistor, and a ground, and a drain of the P-channel transistor and an N-channel transistor of each data input driver. Can be arbitrarily connected to the data signal line.

An ASIC according to the present invention includes a plurality of data input drivers having different driving capabilities, and a plurality of transmission gates respectively arranged between each data input driver and a data signal line. It is.

An ASIC according to the present invention includes a delay monitor circuit formed by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip, and a data input driver. And a delay correction circuit capable of changing a delay time of signal transmission in the extended data signal line.

An ASIC according to the present invention includes a delay correction circuit including one or a plurality of capacitors connectable to a data signal line in order to add capacitance to the data signal line.

An ASIC according to the present invention is a delay correction circuit including a plurality of signal relay lines extending from a data input driver and having wiring paths of different lengths, and a plurality of transmission gates connected to each signal relay line. It is provided with.

A delay correction method in an ASIC according to the present invention uses a delay monitor circuit configured by connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip in series. Calculating a drive capability of a clock driver in the chip, and detecting a clock driver related to a clock signal that cannot secure a sufficient hold margin in a circuit portion having a small hold margin with the calculated drive capability. Increasing the drive capability of the detected clock driver.

A delay correction method in an ASIC according to the present invention uses a delay monitor circuit configured by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip. Calculating the drive capability of the clock driver in the chip, and detecting a data input driver related to a data signal for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin with the calculated drive capability. Reducing the drive capability of the detected data input driver.

A delay correction method in an ASIC according to the present invention uses a delay monitor circuit configured by connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip in series. Calculating the drive capability of the clock driver in the chip, and detecting a data input driver related to a data signal for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin with the calculated drive capability. Extending the signal transmission delay time on the data signal line extending from the detected data input driver.

An automatic placement and routing method in an ASIC according to the present invention comprises the steps of configuring logical description data and delay description data for a target ASIC, and providing detailed information based on the configured logical description data and delay description data. Referring to the step of performing the simulation with delay and the result of the simulation with detailed delay,
Detecting a clock driver or a data input driver that outputs a signal to a circuit portion having a small hold margin; and securing a sufficient hold margin in the circuit portion having a small hold margin for the detected clock driver or data input driver. Reconstructing logic description data by adding a circuit element to which delay compensation function is provided, and delay compensation function using an automatic placement and routing tool based on the reconstructed logic description data and delay description data And generating a layout data including the following.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a clock driver having a normal drive capability according to the first embodiment of the present invention. In FIG. 1, 1a, 1b, 1c are voltage sources, 2a, 2b, 2c are P-channel transistors,
3a, 3b, 3c are N-channel transistors, 4 is a ground portion, 5 is a signal line to which an inverted clock signal is input,
Reference numeral 6 denotes a clock signal line to which a clock signal is transmitted.
These circuit elements except for a portion connecting the drain of the P-channel transistor 2a and the drain of the N-channel transistor 3a to the clock signal line 6,
It is formed in steps up to the metal step. FIG. 2 is a circuit diagram showing a configuration of a clock driver with enhanced drive capability according to the second embodiment of the present invention. 2, the same reference numerals as those in FIG. 1 denote the same parts, and a description thereof will be omitted. The circuit element shown in FIG. 2 has a first meta except for a part connecting the drains of P-channel transistors 2a, 2b, 2c and the drains of N-channel transistors 3a, 3b, 3c to clock signal line 6.
It is formed in steps up to l steps.

FIG. 3 is a diagram showing a configuration of a delay monitor circuit for detecting a delay amount of a clock signal by a clock driver. In FIG. 3, 7a, 7b, 7c, 7d
Is an inverter having the same configuration as a standard clock driver formed in the same ASIC. For example, each of the voltage source 1a, the P-channel transistor 2a, the N-channel transistor 3a, and the grounding unit 4 shown in FIG.
Are formed in the same manner as the clock driver composed of. Reference numeral 8 denotes an input pad for inputting a clock signal, and reference numeral 9 denotes an inverter row 7a, 7b, 7c, 7d,
Are output pads from which clock signals passed through are output. The delay monitor circuit shown in this figure also has the same F / F as the majority of the clock driver circuits shown in FIGS.
It is formed in steps up to the firstmetal step.

Next, a delay correction operation according to the first embodiment of the present invention will be described. First, a clock signal is input to the input pad 8 of the delay monitor circuit, the clock signal is compared with a delayed clock signal output from the output pad 9, and the amount of delay is detected. here,
Clock drivers formed in the same chip are presumed to be processed by the same wafer process and have the same characteristics.
It is presumed that clock drivers formed in the SIC have the same drive capability, that is, the same delay characteristics. Therefore, by calculating the delay amount for one inverter based on the delay amount detected by the delay monitor circuit, it is possible to calculate the delay amount and drive capability of the clock driver formed in the chip.

For an ASIC designed by a user, a circuit portion having a small hold margin can be specified by performing an operation simulation using CAD or the like. Therefore, for each clock driver that supplies a clock signal to each circuit part, if the hold margin required by the calculated drive capability can be secured, or the hold margin of the circuit part that supplies the clock signal is sufficient from the beginning. In the case of a larger value, the process after the first metal process (the process after the through hole contact process)
As shown in FIG. 1, the drain of P-channel transistor 2a and the drain of N-channel transistor 3a are connected to clock signal line 6.

If a required hold margin cannot be secured with the calculated driving capability of the clock driver that supplies a clock signal to a circuit portion having a small hold margin due to design, the driving capability of the clock driver is increased. First m
In a step after the etal step, as shown in FIG.
The drains of the channel transistors 2a, 2b, 2c and the drains of the N-channel transistors 3a, 3b, 3c are connected to the clock signal line 6.

As described above, according to the first embodiment, a plurality of inverters 7a, 7b, 7a, 7b having the same configuration as a standard clock driver used in the same chip.
The drive capability of the clock driver in the chip is calculated using a delay monitor circuit configured by serially connecting 7c, 7d,..., And the drive capability of the clock driver whose drive capability can be corrected according to the calculated value. Therefore, the driving capability of the clock driver related to the clock signal for which a sufficient holding margin cannot be secured in a circuit portion having a small holding margin with the driving capability calculated based on the detection value by the delay monitor circuit is enhanced. Therefore, the rise time (fall time) of the clock signal is shortened, the hold margin is enlarged, malfunction is prevented, and even if there is a circuit portion with a small hold margin, fluctuations in the wafer process in the manufacture of an ASIC. Can prevent a decrease in product yield due to factors such as The effect say.

Further, a plurality of clock drivers each comprising a voltage source 1a, 1b, 1c, P-channel transistors 2a, 2b, 2c, N-channel transistors 3a, 3b, 3c and a ground unit 4 are provided. Since the drain of the P-channel transistor and the drain of the N-channel transistor corresponding to the driver are configured to be arbitrarily connectable to the clock signal line 6, when a larger driving capability is required for the clock driver, First metal is used. Since the driving capability can be increased only by connecting the corresponding drains of the clock drivers corresponding to the driving capability required in the process after the process to the clock signal line 6, the delay correction can be easily performed.

Embodiment 2 FIG. 4 is a diagram showing a clock driver circuit before correction according to the second embodiment of the present invention. FIG. 5 is a diagram showing a clock driver circuit after correction according to the second embodiment of the present invention. 4 and 5, reference numerals 11, 12, and 13 denote clock drivers. The clock driver 11 has the smallest drive capability.
The drive capacity increases in the order of 3. Reference numeral 14 denotes a signal line to which an inverted clock signal is input, and reference numeral 15 denotes a clock signal line to which a clock signal is transmitted. In the design stage, the clock driver 11 is normally used, and all the other circuit elements except for the part connecting the clock drivers 11, 12, and 13 to the clock signal line 15 are subjected to the first metal process. It is formed in a process.

Next, a delay correction operation according to the second embodiment of the present invention will be described. First, First me
When the tal step is completed, as in the first embodiment,
The delay amount is detected by using the delay monitor circuit shown in FIG. 3, and the drive capability of the clock driver formed in the ASIC is calculated.

If a hold margin required by the calculated drive capacity can be secured, the first
The clock driver 11 is connected to the clock signal line 15 so as to use the clock driver 11 as planned at the design stage in a process after the metal process.

In addition, a clock signal is supplied to a circuit portion having a small hold margin, and for a clock driver that cannot secure a required hold margin with the calculated drive capability, it is necessary to enhance the drive capability of the clock driver. The clock driver 12 or the clock driver 13 is connected to the clock signal line. FIG. 5 shows a state in which a clock driver 13 having a large drive capacity is connected to the clock signal line 15 when the drive capacity needs to be increased in this way.

As described above, according to the second embodiment, the first embodiment relates to the prevention of a decrease in product yield due to a variation in a wafer process in the manufacture of an ASIC.
The same effect can be obtained. Further, a plurality of clock drivers 11, 12, and 13 having different driving capabilities are provided, and each of the clock drivers is connected to the clock signal line 1.
5 is configured to be arbitrarily connectable to a clock signal line, when a higher driving capability is required for the clock driver, a clock driver that matches the driving capability required in a process subsequent to the first metal process is connected to the clock signal line. Since the drive capability can be increased only by connecting to the line 15, the delay correction can be easily performed.

Embodiment 3 FIG. 6 is a diagram showing a configuration of the clock driver circuit according to the third embodiment of the present invention. In FIG. 6, reference numerals 21, 22, and 23 denote clock drivers. The clock driver 21 has the smallest drive capability, and the drive capability increases in the order of the clock driver 22 and the clock driver 23. In the design stage, the use of the clock driver 21 is usually planned. 24a, 24b, 24c are inverters, 25a, 25b, 25c are transmission gates, 26 is a signal line to which an inverted clock signal is input, 27 is a clock signal line, and 28a, 28b, 28c are selection signals A, B and C are selection signal lines to be input.

Next, a delay correction operation according to the third embodiment of the present invention will be described. First, after the wafer process is completed, the delay amount is detected using the delay monitor circuit shown in FIG. 3 and the drive capability of the clock driver formed in the ASIC is calculated as in the first embodiment. .

If a hold margin required by the calculated drive capability can be ensured, the selection signal line 28a is used so as to use the clock driver 21 having the smallest drive capability as planned at the design stage. , An active signal (H level signal in this case) is input to make the transmission gate 25a conductive. At this time, an inactive signal (in this case, an L level signal) is input to the selection signal line 28b and the selection signal line 28c, and the transmission gates 25b and 25c are turned off.

Further, regarding a clock driver for supplying a clock signal to a circuit portion having a small hold margin,
Clock driver 2 based on the calculated drive capacity
1 cannot secure the required hold margin, the selection signal line 28b or the selection signal line 28b or the selection signal line 23 is used so as to use the clock driver 22 or the clock driver 23 having a large drive capacity according to the required hold margin. An active signal is input to 28c to make the transmission gate 25b or the transmission gate 25c conductive.

As a method for selecting which of the selection signal A, the selection signal B, and the selection signal C is the active signal, a selection signal to be activated is instructed to a register connected to each selection signal line. A software-based method of writing a value, a method using laser trimming, and the like can be given.

As described above, according to the third embodiment, the same effect as that of the first embodiment can be obtained with respect to prevention of a reduction in product yield due to a variation in a wafer process in the manufacture of an ASIC. Further, a plurality of clock drivers 21, 22, 23 having different drive capabilities
And each clock driver and clock signal line 27
Transmission gates 2 arranged between
5a, 25b, and 25c.
If a higher driving capability is required for the clock driver, the desired driving capability can be obtained by inputting an active signal to the transmission gate corresponding to the clock driver that matches the required driving capability. There is an effect that the drive capability of the clock driver can be appropriately corrected even after the completion.

Embodiment 4 FIG. 7 is a diagram showing a configuration of a clock driver circuit according to a fourth embodiment of the present invention. In FIG. 7, reference numerals 31 and 32 denote voltage sources;
35 is a P-channel transistor, 36 is an N-channel transistor, 37 is an inverter, 38 is a ground portion, 39 is a signal line to which an inverted clock signal is input, 40 is a clock signal line to which a clock signal is transmitted, and 41 is P A selection signal line connected to both the channel transistor 33 and the inverter 37 and transmitting the selection signal D. Also,
Voltage sources 31, 32, P-channel transistors 33, 3
4. The variable voltage source 42 includes the inverter 37 and the selection signal line 41. Note that the voltage source 32 has a higher voltage level than the voltage source 31, and the use of the voltage source 31 is usually planned at the design stage.

Next, a delay correction operation according to the fourth embodiment of the present invention will be described. First, after the wafer process is completed, the delay amount is detected using the delay monitor circuit shown in FIG. 3 and the drive capability of the clock driver formed in the ASIC is calculated as in the first embodiment. .

If a hold margin required by the calculated drive capability can be secured, as selected in the design stage, the selection signal line 41 is connected to the selection signal line 41 so as to use the voltage source 31 having a low voltage level. An L-level signal is input to turn on the P-channel transistor 33, and the voltage level of the voltage source 31 is given as the source potential of the P-channel transistor 35.

Further, regarding a clock driver for supplying a clock signal to a circuit portion having a small hold margin,
If the required hold margin cannot be secured by using the voltage source 31 based on the calculated drive capability, an H level signal is supplied to the selection signal line 41 in order to enhance the drive capability of the clock driver. To turn on the P-channel transistor 34,
2 is applied as the source potential of the P-channel transistor 35. At this time, since the drain current of the P-channel transistor 35 increases as the source potential increases, the voltage source 32, the P-channel transistor 35,
The driving capability of the clock driver including the N-channel transistor 36 and the ground portion 38 is enhanced.

In the currently manufactured ASIC, a circuit configuration of a two-power-supply system is mainly used.
A V power supply is used, and a 5 V power supply is often used in input / output units such as I / O ports. Therefore, in the ASIC having such a configuration, a 3.3V power supply is used as the voltage source 31 and a 5V power supply is used as the voltage source 32. In the case of a single power supply, it is also possible to provide a booster circuit and selectively apply the voltage boosted by the booster circuit to the P-channel transistor 35.

As described above, according to the fourth embodiment, the same effect as in the first embodiment can be obtained with respect to the prevention of a decrease in the yield of products due to a variation in the wafer process in the manufacture of an ASIC. Further, the clock driver including the variable voltage source 42 capable of changing the voltage level based on the selection signal D, the P-channel transistor 35, the N-channel transistor 36, and the ground 38 is provided. When a large driving capability is required, a desired driving capability can be obtained by inputting a selection signal D corresponding to a voltage level corresponding to the required driving capability. There is an effect that the drive ability can be appropriately corrected.

Embodiment 5 FIG. FIG. 8 is a diagram showing a configuration of a clock driver circuit according to a fifth embodiment of the present invention. 8, reference numerals 51 and 52 denote voltage sources, 53, 54, and
55 and 56 are P-channel transistors, 57 and 58 are N
The channel transistors 59, 60 and 61 are inverters. Reference numeral 62 denotes a voltage source, 63 denotes a P-channel transistor, 64 denotes an N-channel transistor, and 65 denotes a grounding portion. These circuit elements constitute a clock driver. Further, 66 is a signal line to which the inverted clock signal is input, 67 is a gate signal line for transmitting the level-shifted inverted clock signal to the gates of the P-channel transistor 63 and the N-channel transistor 64, 68
Is a clock signal line to which a clock signal is transmitted, and 69 is a selection signal line to which the selection signal E is input and connected to both the P-channel transistor 53 and the inverter 59.
The voltage source 52 has a higher voltage level than the voltage source 51, and the use of the voltage source 51 is usually planned in the design stage. Note that P-channel transistors 55 and 56, N-channel transistors 57 and 58, inverters 60 and 61
Constitutes a level shift circuit. Then, the level shift circuit, voltage sources 51 and 52, P-channel transistors 53 and 54, inverter 59 and selection signal line 69
Constitutes the variable voltage source 70 for the gate.

Next, a delay correction operation according to the fifth embodiment of the present invention will be described. First, after the wafer process is completed, the delay amount is detected using the delay monitor circuit shown in FIG. 3 and the drive capability of the clock driver formed in the ASIC is calculated as in the first embodiment. .

If the hold margin required by the calculated drive capability can be secured, the select signal line 69 is set to use the voltage source 51 having a low voltage level as planned in the design stage. An L-level signal is input to turn on the P-channel transistor 53, and the voltage level of the voltage source 51 is applied as the source potential of the level shift circuit via the P-channel transistor 53.
Thereby, the voltage source 62, the P-channel transistor 6
3, the voltage level of the voltage source 51 is applied as the gate potential of the clock driver composed of the N-channel transistor 64 and the ground section 65.

Further, regarding a clock driver for supplying a clock signal to a circuit portion having a small hold margin,
If the required hold margin cannot be secured by using the voltage source 51 based on the calculated drive capability, an H level signal is supplied to the selection signal line 69 in order to enhance the drive capability of the clock driver. To turn on the P-channel transistor 54,
2 is given as the source potential of the level shift circuit. At this time, as the source potential of the level shift circuit increases, the voltage applied to the gate of the N-channel transistor 64 increases, and the drain current of the N-channel transistor increases, so that the driving capability of the clock driver increases.

In this embodiment, when the drain current of the N-channel transistor increases,
The fall time of the clock signal is reduced. On this occasion,
When the rise time is required to be reduced based on the circuit characteristics, an inverter may be provided on a clock signal line extending from the clock driver.

As described above, according to the fifth embodiment, the same effect as that of the first embodiment can be obtained with respect to the prevention of a decrease in the product yield due to the fluctuation of the wafer process in the manufacture of the ASIC. Further, a voltage source 62, a P-channel transistor 63, an N-channel transistor 64
And a clock driver including a ground unit 65,
Since the gate variable voltage source 70 capable of applying voltages of different voltage levels based on the selection signal E to the gates of the P-channel transistor 63 and the N-channel transistor 64 is provided, the driving capability of the clock driver is greater. Is required, a desired drive capability can be obtained by inputting a selection signal E corresponding to a gate voltage level corresponding to the required drive capability. Therefore, even after the wafer process is completed, the drive capability of the clock driver can be obtained. Can be corrected appropriately.

Embodiment 6 FIG. FIG. 9 is a circuit diagram showing a configuration of a data input driver having a normal drive capability according to the sixth embodiment of the present invention. In FIG. 9, 71
a, 71b, 71c are voltage sources, 72a, 72b, 72c
Is a P-channel transistor, 73a, 73b and 73c are N-channel transistors, 74 is a ground portion, 75 is a signal line to which an inverted data signal is input, and 76 is a data signal line to which the data signal is transmitted. These circuit elements include drains of P-channel transistors 72a, 72b, 72c and N-channel transistors 73a, 73a.
Except for the part connecting the drains of b and 73c to the data signal line 76, the drain electrode is formed in the steps up to the first metal step. FIG. 10 is a circuit diagram showing a configuration of a clock driver with reduced drive capability according to Embodiment 6 of the present invention. 10, the same reference numerals as those in FIG. 9 denote the same parts, and a description thereof will be omitted. The circuit element shown in FIG. 10 has the structure of First, except that the drain of P-channel transistor 72a and the drain of N-channel transistor 73a are connected to data signal line 76.
It is formed in steps up to the metal step.

The sixth embodiment and the seventh embodiment described below do not increase the driving capability of the clock driver but increase the driving capability of the data input driver as compared with the first to fifth embodiments. The difference is that the data signal is delayed by lowering the clock signal to relatively advance the clock signal and expand the hold margin.

Next, a delay correction operation according to the sixth embodiment of the present invention will be described. First, First me
When the tal step is completed, as in the first embodiment,
The delay amount of the clock signal is detected by using the delay monitor circuit shown in FIG. 3, and the drive capability of the clock driver formed in the ASIC is calculated.

For each clock driver that supplies a clock signal to each circuit part, if the required hold margin can be ensured by the calculated drive capability, or the hold margin of the circuit part that supplies the clock signal is initially If it is large enough,
At a step after the tmetal step, as planned in the design stage, the drains of the P-channel transistors 72a, 72b, 72c and the N
The drains of the channel transistors 73a, 73b, 73c are connected to the data signal line 76.

In the case of a clock driver that supplies a clock signal to a circuit portion having a small hold margin due to design, if a required hold margin cannot be secured based on the calculated delay amount, the small hold margin is required. To reduce the drive capability of the data input driver that supplies the data signal to the circuit portion,
In a step after the first metal step, the drain of the P-channel transistor 72a and the drain of the N-channel transistor 73a are connected to the data signal line 76 as shown in FIG.

As described above, according to the sixth embodiment, a plurality of clock drivers 7a, 7a having the same configuration as a standard clock driver used in the same chip are used.
The drive capability of the clock driver in the chip is calculated using a delay monitor circuit configured by connecting 7b, 7c, 7d,... In series, and the data input driver of the data input driver capable of correcting the drive capability according to the calculated value. Since the drive capability is configured to be corrected, the drive capability calculated by the delay monitor circuit reduces the drive capability of the data input driver relating to data signals for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin. In addition, the hold margin is expanded in accordance with the delay of the data signal to prevent malfunction, and even in the presence of a circuit with a small hold margin, it is possible to prevent a decrease in product yield due to a variation in a wafer process in ASIC manufacturing. It has the effect of being able to.

The voltage sources 71a, 71b, 71c, P
A plurality of data input drivers each comprising channel transistors 72a, 72b, 72c, N-channel transistors 73a, 73b, 73c and a ground portion 74 are provided.
Since the drain of the channel transistor and the drain of the N-channel transistor can be arbitrarily connected to the data signal line 76, when a smaller driving capability is required for the data input driver, the F
The drive capability can be appropriately reduced only by connecting the corresponding drains of the number of data input drivers corresponding to the drive capability required in a process after the first metal process to the data signal line 76, so that the delay correction can be easily performed. This has the effect of being able to be implemented.

Embodiment 7 FIG. FIG. 11 is a diagram showing a configuration of a data input driver circuit according to a seventh embodiment of the present invention. In FIG. 11, reference numerals 81, 82, and 83 denote data input drivers. The data input driver 81 has the largest drive capability, and the drive capability decreases in the order of the data input driver 82 and the data input driver 83.
At the design stage, the use of the data input driver 81 is usually planned. Also, 84a, 84b,
84c is an inverter, 85a, 85b, 85c are transmission gates, 86 is a signal line to which an inverted data signal is input, 87 is a data signal line, and 88a, 88
Reference numerals b and 88c denote selection signal lines to which selection signals F, G and H are input, respectively.

Next, a delay correction operation according to the seventh embodiment of the present invention will be described. First, after the wafer process is completed, the delay amount of the clock signal is detected by using the delay monitor circuit shown in FIG. 3 as in the first embodiment, and the driving capability of the clock driver formed in the ASIC is determined. Is calculated.

If a hold margin required by the calculated drive capability can be ensured, the selection signal line is selected so as to use the data input driver 81 having the largest drive capability as planned at the design stage. An active signal (in this case, an H level signal) is input to 88a to make transmission gate 85a conductive. At this time, the selection signal lines 88b and 88c
An inactive signal (in this case, an L level signal) is input, and the transmission gates 85b and 85c are turned off.

Further, regarding a clock driver for supplying a clock signal to a circuit portion having a small hold margin,
If the clock driver cannot secure the required hold margin based on the calculated drive capability, the drive capability of the data input driver that supplies a data signal to a circuit portion having a small hold margin is reduced. Therefore, depending on the required hold margin, the data input driver
Alternatively, an active signal is input to the selection signal line 88b or the selection signal line 88c so as to use the data input driver 83, and the transmission gate 85b or the transmission gate 85c is turned on.

As a method of selecting which of the selection signal F, the selection signal G, and the selection signal H is to be the active signal, a selection signal to be activated is instructed to a register connected to each selection signal line. A software-based method of writing a value, a method using laser trimming, and the like can be given.

As described above, according to the seventh embodiment, the same effect as that of the sixth embodiment can be obtained with respect to the prevention of a decrease in the product yield due to the fluctuation of the wafer process in the manufacture of the ASIC. Further, a plurality of data input drivers 81, 82, 83 having different drive capabilities
And each data input driver and data signal line 87
Transmission gates 8 arranged between
5a, 85b, and 85c.
When a smaller driving capability is required for the data input driver, a desired driving capability can be obtained by inputting an active signal to a transmission gate corresponding to the data input driver corresponding to the required driving capability. Is completed, the drive capability of the clock driver can be appropriately corrected.

Embodiment 8 FIG. FIG. 12 shows a structure of a normal data input driver circuit according to the eighth embodiment of the present invention. FIG. 13 is a diagram showing a configuration of a data input driver circuit after delay correction according to the eighth embodiment of the present invention. In FIGS. 12 and 13, reference numeral 91 denotes a voltage source, 92 denotes a P-channel transistor, 93 denotes an N-channel transistor, and 94 denotes a grounding unit. These circuit elements constitute a data input driver. Further, 95 is a signal line to which an inverted data signal is input, 96 is a data signal line to which a data signal is transmitted, and 97a, 97b, 9
7c is a capacitor for adding capacitance to the data signal line 96. These capacitors 97a, 9
7b and 97c constitute a delay correction circuit that can change the delay time of signal transmission on the data signal line 96. Except for the part connecting the capacitors 97a, 97b, 97c to the data signal line 96, all other circuit elements are formed in the steps up to the first metal step.

The eighth embodiment and a ninth embodiment to be described later are to delay a data signal on a data signal line extending from a data input driver to relatively advance a clock signal to increase a hold margin. It is characterized by.

Next, a delay correction operation according to the eighth embodiment of the present invention will be described. First, First me
When the tal step is completed, as in the first embodiment,
The delay amount of the clock signal is detected by using the delay monitor circuit shown in FIG. 3, and the drive capability of the clock driver formed in the ASIC is calculated.

If a hold margin required by the calculated drive capability can be secured, the capacitors 97a, 97b, 97c are set as planned in the design stage.
Is connected to the data signal line 96, and the data input driver is used as it is.

If the required hold margin cannot be secured based on the calculated delay amount with respect to the clock driver that supplies the clock signal to the circuit portion having a small hold margin due to design, the small hold margin is required. In order to delay the data signal supplied to the circuit portion, in a process after the First Metal process, as shown in FIG.
97b and 97c are connected to the data signal line 96. In addition,
It is not necessary to connect all the capacitors to the data signal line 96, and any number of capacitors corresponding to a desired delay time can be connected to the data signal line 96 according to the calculated delay amount.

As described above, according to the eighth embodiment, a plurality of clock drivers 7a and 7a having the same configuration as a standard clock driver used in the same chip are used.
7b, 7c, 7d,... Are connected in series to calculate the drive capability of the clock driver in the chip using the delay monitor circuit, and according to the calculated value, from the data input driver using the delay correction circuit. Extending data signal line 96
The data signal extending from the data input driver relating to the data signal for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin with the drive capability calculated by the delay monitor circuit because the delay time of the signal transmission in Since the signal transmission on the line 96 can be delayed, the hold margin is expanded in accordance with the delay of the data signal, malfunction is prevented, and even if a circuit with a small hold margin exists, the wafer process in the ASIC manufacturing can be performed. Thus, it is possible to prevent a decrease in the yield of products due to fluctuations in the product.

In order to add a capacitance to the data signal line 96, a delay correction circuit comprising one or a plurality of capacitors 97a, 97b, 97c connectable to the data signal line 96 is provided. Data signal line 9
If it is necessary to delay the signaling at 6,
Since signal transmission can be delayed by a desired time only by connecting the number of capacitors corresponding to the required delay time to the data signal line 96 in a process subsequent to the first metal process, delay correction can be easily performed. It works.

Embodiment 9 FIG. 14 is a diagram showing a configuration of a data input driver circuit according to a ninth embodiment of the present invention. 14, 101 is a voltage source, 102 is P
A channel transistor, 103 is an N-channel transistor, and 104 is a ground portion. These circuit elements constitute a data input driver. 105a, 105b, 1
05c is an inverter, 106a, 106b, and 106c are transmission gates, 107 is a signal line to which an inverted data signal is input, 108 is a data signal line to which a data signal is transmitted, and 109a, 109b, and 109c are the data input drivers. Signal relay lines 110a, 110b, 110c for connecting the output section and the data signal lines 108
Are selection signal lines to which selection signals I, J, and K are respectively input. In addition, the wiring route of the signal relay line 109a is the shortest, and thereafter, the wiring route becomes longer in the order of the signal relay line 109b and the signal relay line 109c, and the delay amount of the data signal increases accordingly. In the design stage, the use of the signal relay line 109a is usually planned. In addition, the inverters 105a, 105b, 105c, the transmission gates 106a, 106b, 106c,
9a, 109b, 109c and selection signal lines 110a,
From 110b and 110c, a delay correction circuit that can change the delay time of signal transmission on the data signal line 108 is configured.

Next, a delay correction operation according to the ninth embodiment of the present invention will be described. First, after the wafer process is completed, the delay amount of the clock signal is detected by using the delay monitor circuit shown in FIG. 3 as in the first embodiment, and the driving capability of the clock driver formed in the ASIC is determined. Is calculated.

If the hold margin required by the calculated drive capability can be secured, the selection signal is set to use the signal relay line 109a having the shortest wiring path as planned in the design stage. An active signal (H level signal in this case) is input to the line 110a to make the transmission gate 106a conductive. At this time, an inactive signal (in this case, an L level signal) is input to the selection signal lines 110b and 110c, and the transmission gates 106b and 106c are input.
c is turned off.

If the required hold margin cannot be secured based on the calculated delay amount with respect to the clock driver that supplies the clock signal to the circuit portion having the small hold margin due to the design, the small hold margin is required. In order to delay the data signal supplied to the circuit part, the selection signal line 110b or the selection signal is selected such that the signal relay line 110b or the signal relay line 110c having a long wiring path is used depending on the required hold margin. An active signal is input to the line 110c to make the transmission gate 106b or the transmission gate 106c conductive.

As a method for selecting which of the selection signal I, the selection signal J, and the selection signal K is to be the active signal, a selection signal to be activated is instructed to a register connected to each selection signal line. A software-based method of writing a value, a method using laser trimming, and the like can be given.

As described above, according to the ninth embodiment, the same effect as that of the eighth embodiment can be obtained with respect to the prevention of a decrease in the product yield due to the fluctuation of the wafer process in the manufacture of the ASIC. Further, a plurality of signal relay lines 109a, 109b, 109c extending from the data input driver and having wiring paths of different lengths, and a plurality of transmission gates 1 connected to the respective signal relay lines.
Since it is configured to include the delay correction circuit composed of the elements 06a, 106b, 106c, etc., when it is necessary to delay the signal transmission in the signal relay line, the signal having the length of the wiring path corresponding to the required delay time Since a desired delay time can be obtained by inputting an active signal to the transmission gate corresponding to the relay line, the delay time of the data signal can be appropriately corrected even after all the wafer processes are completed.

Embodiment 10 FIG. In the first to ninth embodiments, the delay amount is detected by using the delay monitor circuit formed up to the first metal process, and the drive capability and the like of the clock driver formed in the same ASIC are calculated. Later, operation evaluation is performed on a circuit portion having a small hold margin detected in advance through simulation using CAD or the like, and when it is determined that a malfunction occurs, the various delay correction units described in the above embodiment are used. The configuration was used. However, according to the tenth embodiment of the present invention, if a circuit portion having a small hold margin is detected in advance by simulation, the drive capability of the clock driver is not affected.
An ASIC incorporating delay correction means is configured so that a sufficient hold margin can be uniformly obtained at the design stage.

A procedure for configuring an ASIC incorporating delay correction means at the design stage will be described below. FIG.
15 is a flowchart showing an automatic placement and routing method in an ASIC according to a tenth embodiment of the present invention. First, logical description data and delay description data for the target ASIC are configured (step ST1). Next, a simulation with a detailed delay is performed based on the configured logic description data and delay description data (step ST2). If the result of the simulation with the detailed delay is obtained, a clock driver or a data input driver that outputs a signal to a circuit portion having a small hold margin is detected with reference to the result (step ST3).
When these drivers are detected, a circuit element is added to the detected clock driver or data input driver to provide a delay correction function for securing a sufficient hold margin in a circuit portion having a small hold margin. Then, the logic description data is reconstructed (step ST4). Then, based on the reconstructed logic description data and delay description data, layout data having a delay correction function is generated using an automatic placement and routing tool (step ST5).

In the step ST4 of adding a circuit element to provide a delay correction function, various delay correction means disclosed in the first to ninth embodiments are used.

As described above, according to the tenth embodiment, a clock driver or a data input driver which outputs a signal to a circuit portion having a small hold margin is detected, and the detected driver has a small hold margin. A circuit element for providing a delay correction function for securing a sufficient hold margin in a circuit portion is added to reconstruct logic description data, and based on this, layout data having a delay correction function is generated in advance. With this configuration, there is no need to provide a delay monitor circuit in the ASIC to detect the amount of delay of the clock driver and the like, and labor can be saved for humans, and an ASIC having a delay correction function can be obtained at the design stage. This has the effect of shortening the production time.

[0084]

As described above, according to the present invention, a delay monitor circuit constructed by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip. Is used to calculate the drive capability of the clock driver in the chip and the drive capability of the clock driver whose drive capability can be corrected according to the calculated value. Since the driving capability of the clock driver related to the clock signal for which a sufficient holding margin cannot be secured in a circuit portion having a small holding margin is increased in the capacity, the rising time (falling time) of the clock signal is shortened and the holding margin is expanded. Malfunctions are prevented and there is a circuit part with a small hold margin. Even when an effect that the yield loss of product due to fluctuation of the wafer process can be prevented in the manufacture of ASIC.

According to the present invention, a plurality of clock drivers each comprising a voltage source, a P-channel transistor, an N-channel transistor and a ground are provided, and the drains of the P-channel transistor and the N-channel transistor of each clock driver are provided. Since it is configured so that it can be arbitrarily connected to the clock signal line, if a larger driving capability is required for the clock driver, the number of clock drivers corresponding to the driving capability required in the process after the Firstmetal process is required. Since the drive capability can be enhanced only by connecting the corresponding drain to the clock signal line, there is an effect that delay correction can be easily performed.

According to the present invention, a plurality of clock drivers having different driving capabilities are provided, and each of the clock drivers can be arbitrarily connected to the clock signal line. Is required, First
Since the drive capability can be increased only by connecting a clock driver corresponding to the required drive capability to the clock signal line in a process after the metal process, the delay correction can be easily performed.

According to the present invention, since a plurality of clock drivers having different driving capabilities and a plurality of transmission gates respectively arranged between each clock driver and the clock signal line are provided, When a higher driving capability is required for the driver, the desired driving capability can be obtained by inputting an active signal to the transmission gate corresponding to the clock driver that matches the required driving capability, so that the entire wafer process is completed. There is an effect that the driving capability of the clock driver can be appropriately corrected even after the above.

According to the present invention, the clock driver includes the variable voltage source capable of changing the voltage level based on the selection signal, the P-channel transistor, the N-channel transistor, and the ground portion. If a greater drive capability is required, the desired drive capability can be obtained by activating the selection signal corresponding to the voltage level corresponding to the required drive capability. There is an effect that the driving ability of the driver can be appropriately corrected.

According to the present invention, a clock driver including a voltage source, a P-channel transistor, an N-channel transistor, and a ground, and a different voltage applied to the gates of the P-channel transistor and the N-channel transistor based on a selection signal. And a variable voltage source for the gate capable of applying a voltage of the same level. Therefore, if a larger driving capability is required for the clock driver, a selection corresponding to the gate voltage level corresponding to the required driving capability is required. Since the desired drive capability can be obtained by activating the signal, the drive capability of the clock driver can be appropriately corrected even after the wafer process is completed.

According to the present invention, a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip are connected in series by using a delay monitor circuit configured in the chip. Since the drive capability of the clock driver is calculated and the drive capability of the data input driver whose drive capability can be corrected according to the calculated value is configured, the drive capability calculated by the delay monitor circuit has a small hold margin. Since the drivability of the data input driver relating to the data signal for which a sufficient hold margin cannot be ensured in a portion is reduced, the hold margin is expanded according to the delay of the data signal, malfunction is prevented, and a circuit with a small hold margin is provided. Wafer processing in ASIC manufacturing even when An effect that the yield loss of product due to fluctuation of the scan can be prevented.

According to the present invention, a plurality of data input drivers each comprising a voltage source, a P-channel transistor, an N-channel transistor and a ground are provided, and the drains of the P-channel transistors and the N-channel transistors of each data input driver are provided. Since the drain can be arbitrarily connected to the data signal line, if a smaller driving capability is required for the data input driver, a number corresponding to the driving capability required in a process subsequent to the First Metal process is required. Since the drive capability can be appropriately reduced only by connecting the corresponding drain of the data input driver to the clock signal line, there is an effect that delay correction can be easily performed.

According to the present invention, a plurality of data input drivers having different driving capabilities and a plurality of transmission gates respectively arranged between the respective data input drivers and the data signal lines are provided. When a smaller driving capability is required for the data input driver, a desired driving capability can be obtained by inputting an active signal to a transmission gate corresponding to the data input driver corresponding to the required driving capability. There is an effect that the drive capability of the clock driver can be appropriately corrected even after all the processes are completed.

According to the present invention, a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip are connected in series using a delay monitor circuit configured in the chip. The drive capability of the clock driver is calculated, and the delay time of signal transmission on the data signal line extending from the data input driver is changed using a delay correction circuit according to the calculated value. The drive capability can delay signal transmission on a data signal line extending from a data input driver for a data signal for which a sufficient hold margin cannot be ensured in a circuit portion having a small hold margin. Margin is expanded to prevent malfunction, hold merge Even if the small circuit is present, there is an effect that the yield loss of product due to fluctuation of the wafer process can be prevented in the manufacture of ASIC.

According to the present invention, in order to add a capacitance to the data signal line, the data signal line is provided with the delay correction circuit comprising one or a plurality of capacitors which can be connected to the data signal line. If it is necessary to delay the signal transmission at
The signal transmission can be delayed by a desired time only by connecting the number of capacitors corresponding to the delay time required in the process after the process to the data signal line, so that there is an effect that the delay correction can be easily performed. .

According to the present invention, there is provided a delay correction circuit including a plurality of signal relay lines extending from a data input driver and having different lengths of wiring paths and a plurality of transmission gates connected to each signal relay line. When the signal transmission on the signal relay line needs to be delayed, an active signal is input to the transmission gate corresponding to the signal relay line having a wiring path length corresponding to the required delay time. As a result, a desired delay time can be obtained, so that the delay time of the data signal can be appropriately corrected even after all the wafer processes are completed.

According to the present invention, the step of configuring the logical description data and the delay description data of the target ASIC, and the simulation with the detailed delay is performed based on the configured logical description data and the delay description data. A step of detecting a clock driver or a data input driver that outputs a signal to a circuit portion having a small hold margin with reference to the result of the simulation with the detailed delay, and a step of detecting the clock driver or the data input driver. A step of reconstructing logic description data by adding a circuit element for providing a delay correction function for securing a sufficient hold margin in a circuit portion having a small hold margin; and reconstructing the logic description data and the delay description data. Based on
Generating layout data with a delay correction function using an automatic placement and routing tool. Therefore, there is no need to provide a delay monitor circuit in the ASIC to detect the amount of delay of the clock driver, etc. As a result, it is possible to save labor and to obtain an ASIC having a delay correction function at the design stage, so that the overall manufacturing time can be shortened.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a clock driver circuit having a normal drive capability according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a clock driver circuit with enhanced drive capability according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a delay monitor circuit for detecting a delay amount of a clock signal by a clock driver.

FIG. 4 is a circuit diagram showing a configuration of a clock driver circuit before correction according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a configuration of a clock driver circuit after correction according to a second embodiment of the present invention;

FIG. 6 is a circuit diagram showing a configuration of a clock driver circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a clock driver circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a clock driver circuit according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a data input driver circuit having a normal drive capability according to a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a data input drive circuit with reduced drive capability according to a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a data input driver circuit according to a seventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a normal data input driver circuit according to an eighth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of a data input driver circuit after delay correction according to an eighth embodiment of the present invention.

FIG. 14 is a diagram showing a configuration of a data input driver circuit according to a ninth embodiment of the present invention.

FIG. 15 is an ASIC according to a tenth embodiment of the present invention.
5 is a flowchart showing an automatic placement and routing method in FIG.

FIG. 16 is a circuit diagram showing a configuration of a general circuit portion in an ASIC.

FIG. 17 is a timing chart showing signal timings during normal operation.

FIG. 18 is a timing chart showing signal timings when a malfunction occurs.

[Description of Signs] 1a, 1b, 1c, 31, 32, 51, 52, 62, 7
1a, 71b, 71c, 91, 101 voltage sources, 2a,
2b, 2c, 33, 34, 35, 53, 54, 55, 5
6, 63, 72a, 72b, 72c, 92, 102P
Channel transistors, 3a, 3b, 3c, 36, 5
7, 58, 64, 73a, 73b, 73c, 93, 10
3 N-channel transistors, 4, 38, 65, 74,
94,104 grounding part, 5,14,26,39,66
A signal line to which an inverted clock signal is input;
5, 27, 40, 68 clock signal lines, 7a, 7b,
7c, 7d, 11, 12, 13, 21, 22, 23 clock driver, 8 input pads, 9 output pads, 2
4a, 24b, 24c, 37, 59, 60, 61, 84
a, 84b, 84c, 105a, 105b, 105c
Inverters, 25a, 25b, 25c, 85a, 85
b, 85c, 106a, 106b, 106c Transmission gates, 28a, 28b, 28c, 41, 6
9, 88a, 88b, 88c, 110a, 110b, 1
10c selection signal line, 42 variable voltage source, 67 gate signal line, 70 gate variable voltage source, 75, 86, 9
5,107 signal lines to which inverted data signals are input, 76,87,96,108 data signal lines, 81,
82, 83 data input driver, 97a, 97b, 9
7c Capacitor, 109a, 109b, 109c Signal relay line.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takashi Utsumi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5J001 AA04 AA05 BB00 BB05 BB12 DD01

Claims (16)

[Claims] 1. A delay monitor circuit configured by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip, and a clock driver whose drive capability can be corrected. An ASIC comprising: 2. A clock signal line comprising: a plurality of clock drivers each including a voltage source, a P-channel transistor, an N-channel transistor, and a ground portion; The ASI according to claim 1, wherein the ASI can be arbitrarily connected to the ASI.
C. 3. The ASIC according to claim 1, further comprising a plurality of clock drivers having different drive capabilities, wherein each of the clock drivers can be arbitrarily connected to a clock signal line. 4. The apparatus according to claim 1, further comprising: a plurality of clock drivers having different driving capacities; and a plurality of transmission gates respectively arranged between each clock driver and a clock signal line. ASIC. 5. The ASI according to claim 1, further comprising a clock driver including a variable voltage source capable of changing a voltage level based on a selection signal, a P-channel transistor, an N-channel transistor, and a ground.
C. 6. A clock driver comprising a voltage source, a P-channel transistor, an N-channel transistor, and a ground, and applying different voltage levels to the gates of the P-channel transistor and the N-channel transistor based on a selection signal. 2. The A according to claim 1, further comprising: an applicable gate variable voltage source.
SIC. 7. A delay monitor circuit configured by connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip in series, and a data input driver capable of correcting the driving capability. An ASIC comprising: 8. A data input driver comprising a voltage source, a P-channel transistor, an N-channel transistor, and a ground, wherein a drain of a P-channel transistor and a drain of an N-channel transistor of each data input driver are connected to a data input driver. The AS according to claim 7, wherein the AS can be arbitrarily connected to a signal line.
IC. 9. The semiconductor device according to claim 7, further comprising: a plurality of data input drivers having different drive capacities; and a plurality of transmission gates respectively arranged between the respective data input drivers and the data signal lines.
The ASIC according to 1. 10. A delay monitor circuit configured by connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip in series,
An ASIC comprising: a delay correction circuit capable of changing a delay time of signal transmission in a data signal line extending from a data input driver. 11. The ASIC according to claim 10, further comprising a delay correction circuit including one or a plurality of capacitors connectable to the data signal line in order to add capacitance to the data signal line. 12. A delay correction circuit comprising a plurality of signal relay lines extending from a data input driver and having wiring paths of different lengths, and a plurality of transmission gates connected to each signal relay line. The ASIC according to claim 10, wherein 13. A clock driver in a chip using a delay monitor circuit configured by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip. Calculating a drive capability; detecting a clock driver related to a clock signal for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin with the calculated drive capability; and detecting the drive capability of the detected clock driver. A delay correction method in an ASIC. 14. A clock monitor in a chip using a delay monitor circuit configured by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip. Calculating the drive capability; detecting a data input driver related to a data signal for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin with the calculated drive capability; and Reducing the drive capability. A method for correcting delay in an ASIC. 15. A clock driver in a chip using a delay monitor circuit configured by serially connecting a plurality of clock drivers having the same configuration as a standard clock driver used in the same chip. Calculating the drive capability; detecting a data input driver relating to a data signal for which a sufficient hold margin cannot be secured in a circuit portion having a small hold margin with the calculated drive capability; and Extending the signal transmission delay time in the extended data signal line. 16. Configuring logical description data and delay description data for the ASIC of interest.
A step of performing a simulation with a detailed delay based on the configured logic description data and the delay description data, and a clock driver or a clock driver for outputting a signal to a circuit portion having a small hold margin with reference to the result of the simulation with the detailed delay A step of detecting a data input driver, and adding a circuit element for providing a delay correction function for securing a sufficient hold margin in a circuit part having a small hold margin to the detected clock driver or data input driver. Reconstructing the logic description data, and generating layout data with a delay correction function using an automatic placement and routing tool based on the reconstructed logic description data and delay description data. Characteristic ASI
Automatic placement and routing method in C.