JP2001110927A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem where a semiconductor element mounted on the conventional semiconductor devices, such as BGA and CSP, is liable to malfunction due to the fact that wiring plates stub resides in the semiconductor device to behave like an open stub at high frequencies and gets short-circuited at certain frequency whose effective wavelength becomes four times as long as the length of the open stub, and when rectangular wave signals which contain many higher harmonics are transmitted through a wiring, a specific frequency component of signals is totally reflected in opposite phase at the stub part, a reflected signal component is superposed on the rectangular wave signals to disturb them, and this disturbance of the rectangular waves induces the semiconductor element to malfunction. SOLUTION: The length of the plates stub 6 of a line formed on a BGA or a CPS is set smaller than 1/4 as long as the wavelength of the upper limit of a required frequency band, by which signals transmitted through a signal line 4 are lease deformed, and a semiconductor element mounted on a BGA or a CPS can be prevented from malfunctioning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device packaged by mounting electronic components requiring high-speed transmission.

[0002]

2. Description of the Related Art In recent years, electronic devices have become increasingly smaller and more sophisticated.
The operation speed has been increased and modularization has been promoted. BGA (Ball Gr)
idArray Package) and CSP (Chip)
Scale Package) has been developed.

Hereinafter, a BGA compatible with high-speed transmission will be described as an example of a conventional semiconductor device with reference to the drawings.

FIG. 6 shows an example of a sectional configuration of a conventional BGA compatible with high-speed transmission. In FIG. 6, 41
Is a semiconductor element having a plurality of electrode pads, 42 is a wire, 43 is a mold resin, 44 is a solder resist, 45
Is a surface wiring, 46 is a ground layer (hereinafter referred to as a GND layer),
47 is a power supply layer, 48 is a back wiring, 49 is a via, and 50 is a solder ball. The BGA 51 is constituted as a whole. Reference numeral 52 denotes a plating stub used in an electrolytic plating step for forming a wiring.

In the BGA 51, the semiconductor element 41 is mounted on a base material, which is a wiring board, and the electrode pads of the semiconductor element 41 are connected to the surface wiring 45 formed on the base material by wires 42. Thereby, the electrode pad of the semiconductor element 41 is
Wire 42, surface wiring 45, via 49, and back wiring 4
8 and is electrically connected to the solder ball 50. Further, by electrically connecting to the outside via the solder ball 50, a signal from the electrode pad of the semiconductor element 41 can be output to the outside, and a signal from the outside can be input to the electrode pad of the semiconductor element 41. . Also, the semiconductor element 41
Is a wiring board on which a plurality of dielectric layers (such as BT resin) are stacked and wiring such as a surface wiring 45, a GND layer 46, a power supply layer 47, and a back wiring 48 is formed. The upper and lower wirings are electrically connected by 49 to form a desired wiring path. The surface wiring 45 and the back wiring 48 constitute a microstrip line with respect to the GND layer 46 and the power supply layer 47, respectively, and have a structure having a desired characteristic impedance Z ₀ , respectively.

FIG. 7 is a block diagram of a conventional B corresponding to high-speed transmission.
1 shows an example of a surface wiring pattern of a GA.

Normally, a BGA carrier (also for a CSP) is not manufactured in individual pieces, but is manufactured in a sheet or continuous shape in which some are combined and then cut out into individual pieces. At this time, a wiring pattern is formed on each of the individual pieces by an electrolytic plating method, and the wiring patterns of each of the individual pieces are connected by a conductive line to pass a current. BGA
The conductive line that remains when the carrier for a semiconductor device is cut into individual pieces is a plating stub. Therefore, the plating stub is a conductor wiring attached to a part other than one line from the bond finger (wire pad or flip chip connection pad) to the ball pad, and is formed near the ball pad and the via. The plating stub is formed in each layer, but the plating stub 52 in FIG. 6 is shown for the surface wiring 45 and is a wiring portion outside the via 49.

[0008] FIG. 8 is a diagram showing a conventional C compatible with high-speed transmission.
3 shows an example of a cross-sectional configuration of an SP. 8, reference numeral 61 denotes a semiconductor element, 62 denotes a bump, 63 denotes an underfill resin, 64 denotes a surface wiring, and 65 denotes a ground layer (hereinafter referred to as G).
ND layer), 66 is a power supply layer, 67 is a back wiring, 68
Indicates a via, and 69 indicates an external pad. The CSP 70 is constituted as a whole.

The CSP 70 has a semiconductor element 61 mounted on a base material, which is a wiring board, and connects an electrode pad of the semiconductor element 61 with a bump 62 to a surface wiring 64 formed on the base material. Thereby, the electrode pad of the semiconductor element 61 is
Bump 62, surface wiring 64, via 68, and back wiring 6
7, and is electrically connected to the external pad 69. Further, by electrically connecting to the outside via the external pad 69, it is possible to input to the electrode pad of the semiconductor element 61. The substrate on which the semiconductor element 61 is mounted is a wiring board on which a plurality of dielectric layers (alumina or the like) are laminated and wirings such as a surface wiring 64, a GND layer 65, a power supply layer 66, and a back wiring 67 are formed. The upper and lower wirings are electrically connected by the vias 68 to form a desired wiring path. The surface wiring 64 and the back wiring 67 are respectively G
ND layer 65 and constitute a microstrip line to the power supply layer 66, each of the wiring itself is designed to have a desired characteristic impedance Z _0.

Reference numeral 71 denotes a plating stub used in an electrolytic plating step for forming a wiring. As in the case of the BGA, the plating stub of the CSP is also formed in a step of forming a plurality of wirings on the CSP by electrolytic plating at one time.
Used to electrically connect the wiring between each CSP,
Each CSP is separated and left in an open stub state when it is divided into individual pieces. For this reason, the plating stub is formed in each layer.

When the length from the electrode pad of the semiconductor element of the signal line on the BGA or CSP to the ball or the external pad is sufficiently short with respect to the used frequency band, the characteristic impedance of the signal line is not considered. It is possible.

[0012]

At the time of high-speed transmission, for example, in the case of a clock frequency of 1 GHz, there are many cases where a harmonic component of a rectangular wave needs to be about ten times higher or higher. In this case, the required frequency band is 10G
Hz or more. The wavelength of the sine wave of 10 GHz is 30 mm in the air, and the effective wavelength λ _g on the microstrip line on BT resin (relative permittivity, about 4), which is a material of BGA, is about 15 mm.

In a conventional BGA or CSP configuration, a plating stub exists as described above. The plating stub in the high-frequency behavior as an open stub line on the package can be assumed to form, as shown in FIG. 9, the frequency (10 to open stub length L is equal to one quarter of an effective wavelength lambda _g At f _s ). For this reason,
Relationship attenuation and the frequency of the line is expressed as in FIG. 10, when considering an attempt to pass the rectangular wave signal containing a large number of harmonic components, antiphase in component plating stub portion of the specific frequency f _s Therefore, there is a problem that the reflected component is superimposed on the rectangular wave and the rectangular wave is largely disturbed, thereby causing a malfunction of the mounted semiconductor element.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a BGA or CSP semiconductor device on which a semiconductor element is mounted, in which signal distortion in conductor wiring is reduced as much as possible and a semiconductor element can be prevented from malfunctioning. It is to provide a device.

[0015]

According to the present invention, there is provided a semiconductor device comprising:
The length of the plating stub of the conductor wiring connected to the electrode pad of the semiconductor element is set to ４ of the upper limit wavelength of the desired frequency band.
This makes it possible to minimize signal distortion in the conductor wiring and prevent malfunction of the semiconductor element.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. Here, as an example, a diagram schematically showing a case where a wiring pattern on the outermost surface of a BGA for high-speed transmission is viewed from directly above. FIG. 2 is an enlarged view of a wiring pattern on the outermost surface of a similar semiconductor device. 1 and 2, 1 is a semiconductor element mounting portion, 2 is a bond finger for wire connection, 3 is a stack of a plurality of dielectric layers (such as BT resin), and wiring (including signal lines 4) and vias 5 are provided. Is a wiring substrate on which is formed, 4 is a signal line, 5 is a via, 6
Indicates a plating stub.

The BGA according to the present embodiment is characterized in that the length of the plating stub of the conductor wiring is less than a quarter of the upper limit wavelength of the desired frequency band. The schematic cross-sectional configuration of this BGA is the same as that of the conventional example shown in FIG. 6, and the surface wiring 45 in FIG. 6 corresponds to the illustrated portion of the signal line 4 (the outermost wiring). Note that the configuration having the above characteristics can be similarly applied to a CSP.

Here, the plating stub length L _{S at} which the plating stub 6 that behaves as an open stub in a high frequency state is in a short-circuit state is obtained by the following equation.

L _S = λ _g / 4 where λ _g is the effective wavelength of the signal passing through the signal line 4;
It is obtained by the following equation.

Λ _g = λ ₀ / √ε _e Here, λ ₀ is the wavelength in vacuum, and ε _e is the effective relative permittivity of the dielectric layer of the base material 3 on which the signal line 4 is formed. In the case of a microstrip line, the effective relative permittivity ε _e is
It can be approximately equal to the square root of the dielectric constant. The relationship between effective wavelength lambda _g and the frequency f is given by the following equation.

F · λ _g = C ₀ (C ₀ : speed of light) At the time of high-speed transmission, for example, when the clock frequency is 1 GHz, the harmonic component of a rectangular wave is about 10th harmonic, and the required frequency band is 10 GHz or more. Here, the effective wavelength λ _g on the 10 GHz sine wave microstrip line is, for example, BT as the dielectric layer of the base material 3.
When a resin (dielectric constant: 4.6) is used, the effective wavelength λ _g on the BT resin is about 14 mm, and the plating stub length L _S (= λ _g / 4) in a short-circuit state is about 3.5 mm. Become.
In order to avoid this state, in the present embodiment,
The plating stub length, that is, the open stub length is less than λ _g / 4, and in this example, the plating stub 6 is 3.5 m
The length must be less than m.

As described above, a BGA mounting a semiconductor element
And the length of the plating stub 6 of the line formed on the CSP is less than one-fourth of the upper limit wavelength of the desired frequency band, so that the signal distortion in the signal line 4 can be reduced as much as possible. Malfunction of the semiconductor element can be prevented. In the above description, the plating stub 6 formed on the outermost wiring has been described. However, the plating stub is formed on each layer as described above, and the length of the plating stub of each layer is set to the upper limit wavelength of the desired frequency band. By setting the ratio to less than one-fourth, signal distortion in the signal line 4 can be further reduced.

The rectangular wave is considered to be a sine wave having a fundamental frequency and a set of harmonic components thereof. For example, as shown in FIG. 3, a rectangular wave is a superposition of a large number of harmonics, and the required range of harmonic components differs depending on the system. Usually, it is necessary to consider a harmonic component of about tenth harmonic. Each harmonic component has a wavelength,
By making the length of the plating stub less than 1/4 with respect to the upper limit wavelength of the desired frequency band which is the shortest wavelength, the length of the plating stub is 4 minutes with respect to the wavelength of all harmonic components. Less than 1.

As shown in FIG. 4, there are always a point where the voltage amplitude is always zero and a point where the voltage amplitude is maximum on the transmission line, and that point is an integer multiple of a quarter wavelength of the transmission line from the load end. It is at a distance, and reverses when the load end is short-circuited or open. Similarly, when an arbitrary load is connected to the load end, the amplitude also has a maximum and a zero portion (the load can be adjusted to make all the amplitudes constant: a matching state). As described above, when the length of the transmission path is equal to or longer than a quarter wavelength with respect to the required maximum harmonic component of the signal, it is necessary to treat the transmission path as a distributed constant circuit. In the case of the open end, as shown in FIG. 4, a node is formed at a quarter wavelength portion, and a maximum value occurs at a half wavelength portion. Therefore, when the length of the plating stub exceeds a quarter wavelength, a wave having an opposite phase to the traveling wave is reflected. In particular, in the case of a quarter wavelength, total reflection occurs. For this reason, if there is a plating stub having a quarter wavelength or more, a ringing waveform as shown in FIG. 5 is generated, which may cause a malfunction in the system. Less.

Therefore, by setting the length of the plating stub of each layer to less than one-fourth of the upper limit wavelength of the desired frequency band, in other words, by making the length of the plating stub less than one-fourth for the wavelengths of all harmonic components. In addition, the signal distortion in the signal line 4 can be reduced, and malfunction can be prevented.
In addition, since the signal line is designed and manufactured to be stable at a certain characteristic impedance in a high-speed transmission line, the ideal type (the length of the plating stub is zero) is that there is no plating stub that disturbs the impedance, It is currently difficult to eliminate it in the manufacturing process.

[0027]

As described above, according to the present invention, the length of the plating stub formed on the BGA or CSP on which a semiconductor element is mounted is reduced to less than a quarter of the upper limit wavelength of the desired frequency band. In addition, it is possible to minimize signal distortion in the conductor wiring (signal line) and prevent malfunction of the semiconductor element.

[Brief description of the drawings]

FIG. 1 is a plan view of a wiring pattern on the outermost surface of a BGA corresponding to high-speed transmission according to an embodiment of the present invention.

FIG. 2 is an enlarged plan view of a wiring pattern on the outermost surface of a BGA corresponding to high-speed transmission according to the embodiment of the present invention.

FIG. 3 is a diagram schematically illustrating a home where rectangular waves are formed.

FIG. 4 is a view for explaining that the length of a plating stub is set to less than one-fourth of an upper limit wavelength of a desired frequency band in the present embodiment.

FIG. 5 is a diagram for explaining that the length of the plating stub is set to be less than 分 の of the upper limit wavelength of the desired frequency band in the present embodiment.

FIG. 6 is a sectional configuration diagram of a BGA corresponding to high-speed transmission in a conventional example.

FIG. 7 is a plan view of a surface wiring pattern of a BGA corresponding to high-speed transmission in a conventional example.

FIG. 8 is a sectional configuration diagram of a CSP corresponding to high-speed transmission in a conventional example.

FIG. 9 is a signal line equivalent circuit diagram including a plating stub.

FIG. 10 is a diagram illustrating a relationship between attenuation and frequency of a line including an open stub.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element mounting part 2 Bond finger for wire connection 3 Base material 4 Signal line 5 Via 6 Plating stub

[Procedure amendment]

[Submission date] December 28, 2000 (200.12.
28)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

[0015]

According to the present invention, there is provided a semiconductor device comprising:
The length of the plating stub of the conductor wiring connected to the electrode pad of the semiconductor element is determined by the rectangular wave signal passed through the semiconductor element.
The frequency of the high frequency component is set to less than one-fourth of the upper limit wavelength (the upper limit wavelength of the desired frequency band ) , thereby minimizing signal distortion in the conductor wiring and preventing malfunction of the semiconductor element. can do.

Claims (1)

[Claims] 1. A semiconductor element having a plurality of electrode pads, a base material having a conductor wiring for mounting the semiconductor element and electrically connecting an electrode pad of the semiconductor element to the outside, A semiconductor device comprising a plating stub, wherein a length of the plating stub of the conductor wiring is set to less than a quarter of an upper limit wavelength of a desired frequency band.