JP2001103109A - Symbol clock regeneration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a symbol clock regeneration circuit with a simple configuration that can conduct high-speed phase locking and generates a stable recovery symbol clock signal even in the case that a carrier frequency error is high and a phase of a symbol clock signal of a base station and a phase of a symbol clock signal of a mobile terminal are largely different. SOLUTION: The symbol clock regeneration circuit is provided with an reverse phase detector 5 that detects whether or not a phase of a regenerated symbol clock signal is reverse to a phase of a symbol clock signal of a base station. When the reverse phase detector 5 detects that the phase of the regenerated symbol clock signal is reversed, the reverse phase detector 5 immediately outputs a reset signal to initialize a self-running count of a counter 6 to the counter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit of a demodulator provided in a digital mobile communication terminal or the like which receives a burst signal by employing a TDMA (time division multiple access) method or the like, and more particularly to a QPSK (quadrature phase). shift
The present invention relates to a clock recovery circuit capable of performing high-speed phase pull-in for demodulation of a phase modulation wave such as keying.

[0002]

2. Description of the Related Art In digital mobile communication, π / 4 QPSK is used.
The phase modulation system and the TDMA system are adopted. In such mobile communication, in order to transmit and receive data, it is necessary to synchronize with the symbol clock timing in the base station. Therefore, the phase of the symbol clock signal of the base station and the phase of the symbol clock signal of the mobile station must be synchronized. Had to be synchronized. A digital mobile communication terminal that is a mobile station receives a signal transmitted from a base station, extracts the timing of the symbol clock signal of the base station from the received signal, and changes the phase of the symbol clock signal of the digital mobile communication terminal. It must be synchronized with the phase of the base station's symbol clock signal. As described above, the circuit that reproduces the symbol clock signal in the mobile station so as to synchronize with the phase of the symbol clock signal of the base station is the symbol clock regeneration circuit.

FIG. 5 is a schematic block diagram showing a configuration example of a conventional symbol clock recovery circuit. In FIG. 5, a symbol clock recovery circuit 100 includes a timing extraction circuit 101 and a PLL circuit 104 including a comparator 102 and a counter 103 having a free-running counter. A phase pull-in operation for synchronization is performed so as to match the phase of the input modulated wave.

The timing extraction circuit 101 detects a zero cross point of the input modulated wave signal, and outputs a pulse signal indicating the zero cross point to the PLL circuit 104. In the PLL circuit 104, the timing extraction circuit 1
An output signal from 01 is input as a symbol timing signal, and the self-running counter performs a synchronization operation for synchronizing with the symbol timing signal to generate and output a reproduced symbol clock signal.

In such a configuration, the PLL circuit 10
4 shows that if the range of phase lock-in of the reproduced symbol clock signal with respect to the symbol clock signal is widened, that is, if the synchronization accuracy is reduced, the phase lock-in speed, which is the speed until the synchronization is achieved, increases, but the reproduced symbol clock signal becomes stable. The properties are deteriorated and the properties are deteriorated. Conversely, if the range of the phase lock-in of the reproduced symbol clock signal with respect to the symbol clock signal is narrowed, that is, if the synchronization accuracy is improved, the phase pull-in speed is reduced, but the stability of the reproduced symbol clock signal is improved and the characteristics are improved. .

FIG. 6 is a timing chart showing an operation example of the PLL circuit 104 shown in FIG. 5. The operation of the PLL circuit 104 of FIG. 5 will be described with reference to FIG. The counter 103 is composed of a free-running counter having a counter cycle of “00h” to “13h”,
The L circuit 104 receives the signal indicating the zero cross point input from the timing extraction circuit 101 shown in FIG. 6B and the initial value “00” of the self-running counter value shown in FIG.
h ”is adjusted so that the self-running counter value is adjusted.
That is, the PLL circuit 104 sets the self-running counter value to “0”.
0h ”is synchronized with the rising edge of the symbol clock signal of the base station shown in FIG.

The PLL circuit 104 has a self-running counter value “0”.
A reproduced symbol clock signal is generated and output so as to rise at "0h" and fall at the free-running counter value "09h". Here, for example, as shown in FIG.
The zero-cross point in (b) is the value of the self-running counter value “00”.
h "to" 09h ", the self-propelled counter value normally initialized at" 13h "is counted up to" 14h "in order to delay the phase of the reproduced symbol clock signal to be output, and then is initialized. Become By doing so, the phase of the reproduced symbol clock signal becomes 1
/ 20 cycles can be delayed.

For example, as shown in FIG. 6E, the zero cross point in FIG.
When the detected value is detected between "Ah" and "13h", the self-running counter value normally initialized at "13h" is initialized at "12h" in order to advance the phase of the output reproduced symbol clock signal. By doing so, the phase of the reproduced symbol clock signal can be advanced by 1/20 cycle.

On the other hand, as shown in FIG. 6F, when the phase of the reproduced symbol clock signal is different from the symbol clock signal of the base station shown in FIG. In order to establish synchronization of the respective phases of the symbol clock signal and the reproduced symbol clock signal, as described above, the direction of delaying the phase of the reproduced clock signal,
Alternatively, in the case of FIG. 6, for example, the operation of changing the phase in the moving direction has to be performed ten times (10 × 1/20).
In mobile communications, when pulling in a phase from a completely opposite phase, synchronization occurs in the opposite phase due to a carrier frequency error. Synchronization occurs in the phase change operation of 10 times by correcting the carrier frequency error and changing the phase. Not completed,
In some cases, a great deal of time is required.

[0010] For this reason, in the digital mobile communication terminal, in the initial state of burst reception, it is necessary to perform high-speed phase pull-in. Therefore, a method of changing the amount of phase change to increase the phase pull-in speed has been performed. . For example, when the phase change amount is 1/20, the phase pull-in range is narrow and the phase pull-in speed is low, and the stability of the reproduced clock signal is improved. However, in the initial state of the burst reception, it takes too much time to phase-in, so that phase-in is not completed in the redundant bit (preamble) pattern, and communication cannot be established without establishing synchronization. Further, for example, the phase change amount is 2/20.
Is the case where the phase pull-in range is wide and the phase pull-in speed is fast, and phase pull-in is completed in the preamble pattern, but the stability of the reproduced symbol clock signal is poor, and synchronization is established but the stable symbol clock signal Since reproduction was not possible, it was difficult to obtain stable reception.

From the above, when a TDMA system such as digital mobile communication is employed, in the initial state of phase pull-in, the phase pull-in range is widened and the phase pull-in speed is increased to supplement synchronization. When the phase error is reduced, the high-speed phase pull-in operation is completed.
Next, in order to improve the stability of the operation, the phase lock-in range is narrowed, the phase lock-in speed is reduced, and synchronization is maintained to generate a stable reproduced symbol clock signal.

[0012]

In a TDMA system or the like such as digital mobile communication, synchronization is established in an initial state, that is, a preamble pattern of burst reception, and a synchronization (unique word) pattern following the preamble pattern is started. Must be stably received and reproduced. However, when the carrier frequency error is large, or when the phase of the input signal, that is, the phase of the symbol clock signal of the base station and the phase of the symbol clock signal of the mobile terminal are significantly different, the synchronized symbol clock signal can be easily converted. However, there is a problem that communication cannot be performed because the data cannot be reproduced.

As described above, when the phase pull-in range is widened and the phase pull-in speed is increased to perform the phase pull-in of the burst signal, the stability of the reproduced symbol clock signal is reduced, and the characteristics of the reproduced symbol clock signal are deteriorated. There was a problem. In addition, if the phase pull-in range is narrowed and the phase pull-in speed is slowed down to perform phase pull-in of the burst signal, it takes too much time to pull in the phase, the phase pull-in is not completed in the preamble pattern, and communication cannot be performed at all. There was a problem that would.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a large carrier frequency error or a large phase of the symbol clock signal of the base station and the phase of the symbol clock signal of the mobile terminal. It is an object of the present invention to provide a symbol clock reproducing circuit having a simple configuration capable of performing a phase pull-in operation at a high speed and generating a stable reproduced symbol clock signal even in a different case.

[0015]

A symbol clock recovery circuit according to the present invention is used in a demodulator of a digital mobile communication terminal or the like, and reproduces a symbol clock indicating a data identification timing from a received signal. The circuit includes a phase detection unit that detects and outputs a phase of a symbol clock signal from a received signal, and a clock signal generation unit that generates and outputs a clock signal synchronized with the phase detected by the phase detection unit. The clock signal generation unit detects an opposite phase state between the phase of the generated clock signal and the phase detected by the phase detection unit, and when the anti-phase state is detected, the phase of the generated clock signal is detected by the phase detection unit. Is generated by correcting so as to be in phase with the phase detected in step (1).

More specifically, the clock signal generation section includes a counter circuit section that generates and outputs a clock signal with a variable phase in accordance with a counter value of a free-running counter having a predetermined count cycle, and a phase detection section. A phase comparison unit that compares the phase detected by the unit with the phase of the clock signal output from the counter circuit unit, and changes the count cycle of the free-running counter with respect to the counter circuit unit according to the comparison result; Detecting an opposite phase state between the phase detected by the detection section and the phase of the clock signal output from the counter circuit section, and detecting the opposite phase state, the clock signal generated to the counter circuit section. And an anti-phase detecting unit for correcting the counter value of the self-running counter so that the phase becomes the same as the phase detected by the phase detecting unit.

More specifically, upon detecting the anti-phase state, the anti-phase detection section immediately outputs a reset signal for resetting the self-running counter value to the initial value to the counter circuit section.

Further, specifically, the above-mentioned antiphase detecting section comprises:
When the anti-phase state is detected, when the self-running counter value reaches a predetermined value, a reset signal for resetting the self-running counter value to an initial value is output to the counter circuit unit.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a schematic block diagram showing an example of the symbol clock recovery circuit according to the first embodiment of the present invention. In FIG. 1, a symbol clock recovery circuit 1
Is composed of a timing extraction circuit 2 and a PLL circuit 3, and sets the phase of a reproduced clock signal as an output signal to
A phase pull-in operation for synchronization is performed so as to match the phase of the input modulated wave. The PLL circuit 3 includes a comparator 4,
An anti-phase detector 5 and a counter 6 having a free-running counter are provided.

The timing extracting circuit 2 is connected to a comparator 4 and an antiphase detector 5, respectively, and the comparator 4 and the antiphase detector 5 are each connected to a counter 6. The timing extraction circuit 2 detects a zero cross point from the input modulated wave signal by using, for example, delay detection for detecting a difference from a symbol one symbol before, and outputs a signal indicating the zero cross point to the PLL circuit 3. To the comparator 4 and the antiphase detector 5. The output signal from the timing extraction circuit 2 is input to the comparator 4 and the antiphase detector 5 as a symbol clock signal.

The comparator 4 compares the signal indicating the zero-cross point from the timing extraction circuit 2 with the reproduced symbol clock signal input from the counter 6, and
, And outputs a predetermined initialization timing change signal. Thus, the comparator 4 performs a synchronization operation for synchronizing the symbol clock signal of the base station and the reproduced symbol clock signal with respect to the self-running counter of the counter 6.

The antiphase detector 5 includes a timing extraction circuit 2
From the signal indicating the zero-cross point from the base station and the self-running counter value input from the counter 6, the detection of the opposite phase state of the reproduced symbol clock signal relative to the phase of the symbol clock signal of the base station is performed. When the anti-phase detector 5 detects the anti-phase state of the reproduced symbol clock signal,
A reset signal for resetting the self-running counter value of the counter 6 to the initial value is output to the counter 6.

The counter 6 generates and outputs a reproduced symbol clock signal and a reproduced bit clock signal generated by performing a synchronous operation so that the signal level changes with respect to a predetermined free-running counter value. For example, counter 6
Repeats the count-up of the normal free-running counter value “00h” to “13h”, but responds to the initialization timing change signal from the comparator 4 to reset the normal free-running counter value “13h”.
The operation to be initialized by the counter value is “12h” or “14h”.
h ", the phase of the reproduced symbol clock signal is changed.

Here, in the π / 4 QPSK modulation, a bit clock signal which is a clock signal twice as fast as a symbol clock signal is required in order to represent one symbol with two bits for a quaternary symbol. . That is, since two bits of data are transmitted from the base station for one symbol clock signal, one bit of the symbol clock signal is transmitted.
A / 2 cycle signal is a bit clock signal. In a normal system, the bit clock signal is a reference for operation.

Next, the operation of the antiphase detector 5 will be described in more detail. FIG. 2 is a timing chart showing an operation example of the PLL circuit 3 shown in FIG. 1. The operation of the antiphase detector 5 of FIG. 1 will be described with reference to FIG. The counter 6 is composed of a free-running counter having a counter period of “00h” to “13h”, and the comparator 4 indicates a zero cross point input from the timing extraction circuit 2 shown in FIG. The self-running counter value is adjusted so that the signal matches the initial value “00h” of the self-running counter value shown in FIG. That is, the comparator 4
Performs an operation of synchronizing the self-running counter value “00h” with the rising edge of the symbol clock signal of the base station shown in FIG.

On the other hand, when the pulse signal indicating the zero cross point is input in the section of the free-running counter value “07h” to “0Dh” shown in FIG. It is determined that the phase of the reproduced symbol clock signal is shifted from the phase of the clock signal by about 180 °, and a reset signal for instantly resetting the counter 6 to an initial value is output to the counter 6 as shown in FIG. The self-running counter value is reset to “00h”. For this reason, the phase of the reproduced symbol clock signal in the opposite phase can be synchronized with the phase of the symbol clock signal of the base station. The reproduced symbol clock signal output from the counter 6 at this time is shown in FIG. 2E, and the reproduced bit clock signal corresponding to the reproduced symbol clock signal shown in FIG. 2E is shown in FIG. ing.

In this way, the opposite phase state of the reproduced symbol clock signal with respect to the symbol clock signal of the base station is eliminated, and the comparator 4 controls the self-running counter of the counter 6 so that the symbol clock signal of the base station and the reproduced symbol A synchronization operation for synchronizing with a clock signal is performed. In FIG. 2, in order to make the description easier to understand,
Since only the operation by the antiphase detector 5 is performed, the phases of the symbol clock signal of the base station and the reproduced symbol clock signal are not completely synchronized. The phase of the symbol clock signal and the phase of the reproduced symbol clock signal are completely synchronized.

On the other hand, in FIG. 1 and FIG.
When the reverse phase is detected, a reset signal for resetting the self-running counter value is immediately output to the counter 6. However, a filter 11 such as an integrating circuit is connected between the reverse phase detector 5 and the counter 6. Alternatively, the reset signal input to the counter 6 may be adjusted. FIG. 3 is a schematic block diagram showing another example of the symbol clock recovery circuit 1 in such a case. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and only the differences from FIG. 1 will be described.

The difference between FIG. 3 and FIG. 1 is that the reset signal output from the anti-phase detector 5 is input to the counter 6 via the filter 11, and this indicates that
The LL circuit 3 is replaced by a PLL circuit 3a, and the symbol clock recovery circuit 1 of FIG. 1 is replaced by a symbol clock recovery circuit 1a. In the circuit of the signal processing system, deterioration of characteristics due to quantization error, influence of noise, and the like can be considered. For this reason, the filter 11 is provided at the next stage of the antiphase detector 5, and the filter 11 adjusts the reset signal to the counter 6 according to a plurality of symbol states. For example, the adjustment is performed so that the reset signal is output to the counter 6 only when the opposite phase is detected by the opposite phase detector 5 twice in three consecutive symbols. By doing so, a more stable reproduced symbol clock signal can be obtained.

As described above, the symbol clock recovery circuit according to the first embodiment determines that the phase of the recovered symbol clock signal at the digital mobile communication terminal is opposite to the phase of the symbol clock signal at the base station. An anti-phase detector for detecting, and when the anti-phase detector detects that the phase of the reproduced symbol clock signal is in an anti-phase state, a reset signal for initializing the self-running counter value of the counter 6 is immediately sent to the counter 6. Added output.

From this, when the reproduced symbol clock signal in the digital mobile communication terminal has an opposite phase to the phase of the symbol clock signal of the base station, the reproduced symbol clock signal is instantaneously converted to the symbol clock signal of the base station. Synchronization can be established for the phase. For this reason, in the digital mobile communication terminal, in the initial state of burst reception, the recovered symbol clock signal is not phase-locked to the opposite phase with respect to the symbol clock signal of the base station,
The phase pull-in operation can be completed at high speed, the speed of synchronizing can be increased, and a stable reproduced symbol clock signal can be generated.

Embodiment 2 FIG. In the first embodiment, when the antiphase detector 5 detects that the reproduced symbol clock signal has the opposite phase to the symbol clock signal of the base station,
The self-running counter value is immediately reset to the initial value. However, when it is detected that the reproduced symbol clock signal has an opposite phase to the symbol clock signal of the base station, the self-running counter value becomes a predetermined value. Alternatively, the self-running counter value may be reset to an initial value, and such a value is referred to as a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation example of the symbol clock recovery circuit according to the second embodiment of the present invention. Note that a schematic block diagram showing a symbol clock recovery circuit according to the second embodiment of the present invention is:
The anti-phase detector 5 in FIG. 1 is replaced with an anti-phase detector 5b, and accordingly, the PLL circuit 3 in FIG.
1 except that the symbol clock recovery circuit 1 of FIG. 1 is replaced by a symbol clock recovery circuit 1b, the description is omitted, and the opposite phase detector 5 which is different from FIG.
The operation of b will be described.

The anti-phase detecting circuit 5b receives the signal indicating the zero cross point from the timing extracting circuit 2 and the counter 6
From the self-running counter value input from the base station, the phase of the recovered symbol clock signal with respect to the phase of the symbol clock signal of the base station is detected. When the anti-phase detector 5b detects the anti-phase state of the reproduced symbol clock signal, the anti-phase detector 5b counts a reset signal for resetting the self-running counter value to an initial value when the self-running counter value of the counter 6 reaches a predetermined value. 6 is output. Here, FIGS. 4 (a) to 4 (c)
2A to 2C, FIG. 4A shows a symbol clock signal of the base station, and FIG. 4B shows a signal indicating a zero cross point output from the timing extraction circuit 2. FIG. 4C shows the bit clock signal of the base station.

When the zero-cross point is detected in the section of the free-running counter value “07h” to “0Dh” shown in FIG. 4D, the antiphase detector 5b determines the phase of the symbol clock signal at the base station. It is determined that the phase of the reproduced symbol clock signal is shifted by about 180 °. Based on the determination, the anti-phase detector 5b resets the self-running counter value when the self-running counter value becomes "09h" as shown in FIG. And outputs a reset signal to the counter 6 to return to the initial value. Since the self-running counter value is reset at normal “13h” or “09h” of １ ／, the cycle of the bit clock signal which is １ ／ cycle of the symbol clock signal can be made constant. .

By doing so, the phase of the reproduced symbol clock signal at the opposite phase can be synchronized with the phase of the symbol clock signal of the base station.
The period of the reproduction bit clock signal can be made constant. The reproduced symbol clock signal output from the counter 6 at this time is shown in FIG. Also,
FIG. 4 also shows a case where only the operation by the antiphase detector 5b is performed for the sake of simplicity of explanation, so that the phases of the symbol clock signal of the base station and the reproduced symbol clock signal are completely synchronized. In practice, however, the comparator 4 ensures that the phases of the symbol clock signal of the base station and the reproduced symbol clock signal are completely synchronized.

As described above, the symbol clock recovery circuit according to the second embodiment determines that the phase of the recovered symbol clock signal at the digital mobile communication terminal is opposite to the phase of the symbol clock signal at the base station. An anti-phase detector 5b for detecting the phase of the reproduced symbol clock signal is detected when the anti-phase detector 5b detects that the phase of the reproduced symbol clock signal is in an anti-phase state. A reset signal for initializing the self-running counter value of the counter 6 with the running counter value is output to the counter 6.

Accordingly, the same effect as in the first embodiment can be obtained, and even when the opposite phase is frequently detected by the opposite phase detector 5b in the initial state or the no-signal state of the burst, Because the frequency of the reproduced bit clock signal can be kept constant without randomly changing the phase of the reproduced bit clock signal,
It is possible to eliminate the influence on the system that receives the reproduced bit clock signal.

The first embodiment and the second embodiment
In the above, the case where the π / 4 QPSK modulation system, the TDMA system, and the zero-cross detection system are used has been described as an example.
The present invention is not limited to these, and can be easily applied to other modulation schemes and detection schemes.

[0040]

As is apparent from the above description, according to the symbol clock recovery circuit of the present invention, the clock signal generated and output by the clock signal generation unit, specifically, the counter circuit unit having a free-running counter. Synchronize the phase of the signal with the phase of the symbol clock signal obtained from the received signal,
Correction was made to be in phase. For example, when it is detected that the phase of the clock signal generated by the counter circuit section is opposite, the self-running counter value of the counter circuit section is immediately reset to the initial value. Therefore, in the digital mobile communication terminal, the phase locking operation can be completed at high speed without performing the phase locking of the reproduced symbol clock signal in the initial state of the burst reception to the opposite phase to the symbol clock signal of the base station. In addition, the speed of synchronizing can be increased, and a stable reproduction symbol clock signal can be generated.

When it is detected that the phase of the clock signal generated by the counter circuit section is opposite, the self-running counter value of the counter circuit section is reset to a predetermined value without immediately resetting to the initial value. I made it. From this, even in the case where the opposite phase is frequently detected in the initial state or no signal state of the burst, the phase of the bit clock signal generated by changing the period of the symbol clock signal does not change at random. Since the frequency of the bit clock signal can be kept constant, it is possible to eliminate the influence on the system that receives the bit clock signal.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating an example of a symbol clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example of the symbol clock recovery circuit 1 of FIG.

FIG. 3 is a schematic block diagram showing another example of the symbol clock recovery circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing an operation example of the symbol clock recovery circuit according to the second embodiment of the present invention.

FIG. 5 is a schematic block diagram showing a configuration example of a conventional symbol clock recovery circuit.

FIG. 6 is a timing chart showing an operation example of the PLL circuit 104 of FIG. 5;

[Explanation of symbols]

 1, 1a Symbol clock recovery circuit 2 Timing extraction circuit 3, 3a PLL circuit 4 Comparator 5 Antiphase detector 6 Counter 11 Filter

Claims (4)

[Claims] 1. A symbol clock recovery circuit used for a demodulator of a digital mobile communication terminal or the like, which recovers a symbol clock indicating data identification timing from a received signal, wherein a phase of the symbol clock signal is detected from the received signal. And a clock signal generator for generating and outputting a clock signal synchronized with the phase detected by the phase detector. The clock signal generator includes a clock signal generator for generating the clock signal. The phase of the clock signal to be generated is detected to be in phase with the phase detected by the phase detection unit. A symbol clock regeneration circuit, wherein the symbol clock regeneration circuit generates the corrected symbol clock. 2. The clock signal generation section includes: a counter circuit section that generates and outputs a clock signal with a variable phase according to a counter value of a free-running counter having a predetermined count cycle; A phase comparator that compares the phase of the clock signal output from the counter circuit unit with the phase of the clock signal output from the counter circuit unit, and changes the count cycle of the self-running counter with respect to the counter circuit unit according to the comparison result; The phase detected by the unit and the phase of the clock signal output from the counter circuit unit are detected in an opposite phase state. When the anti-phase state is detected, the clock generated by the counter circuit unit is generated. An anti-phase detector for correcting the counter value of the self-running counter so that the phase of the signal becomes the same as the phase detected by the phase detector. Item 2. A symbol clock recovery circuit according to item 1. 3. The apparatus according to claim 2, wherein the antiphase detecting section outputs a reset signal for resetting the self-running counter value to an initial value to the counter circuit section upon detecting the antiphase state. The symbol clock regeneration circuit according to any of the preceding claims. 4. The anti-phase detecting section, when detecting an anti-phase state, outputs a reset signal for resetting the self-running counter value to an initial value when the self-running counter value reaches a predetermined value. 3. The symbol clock recovery circuit according to claim 2, wherein: