JP2001102925A - Digital-to-analog converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the precision of the analog output voltage of a PWM (pulse-width modulation) type D/A converting device and to improve the linearity of D/A conversion output characteristics as to an error of the analog output voltage generated owing to a difference in the output impedance of a PWM signal output circuit between a high-potential-output time and a low-potential- output time by adjusting the duty factor of a PWM signal so that an analog output voltage specified by digital data as an object of D/A conversion is obtained. SOLUTION: A data correcting means 14 converts digital data 11a as an object of D/A conversion into correction digital data 14a with which an output voltage corresponding to the digital data can actually be obtained. A PWM circuit part 12 generates a PWM signal with a duty factor corresponding to the correction digital data 14a and supplies the PWM signal 10a to a low-pass filter circuit 20 through a PWM signal output buffer circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM (pulse width modulation) type DA (digital-to-analog) converter, and more particularly to a PWM signal output circuit in which an output impedance of a PWM signal output circuit is high and low. By adjusting the duty of the PWM signal so that the analog output voltage specified by the digital data to be converted is obtained, the accuracy of the analog output voltage is improved. The present invention also relates to a DA converter that improves the linearity of DA conversion output characteristics.

[0002]

2. Description of the Related Art Digital data is converted into a PWM signal having a duty corresponding to the digital data.
A DA converter configured to input a signal to a low-pass filter and output an analog signal is disclosed in Japanese Patent Application Laid-Open No. H2-15530.
No. 3, JP-A-3-27621, JP-A-9-2
This is known from, for example, Japanese Patent No. 32958.

A one-chip microcomputer (one-chip microcomputer) having a built-in PWM circuit for generating a PWM signal, an ASIC having a built-in PWM circuit, and the like are used in various electronic devices. For example, JP-A-10-
JP-A-41819 discloses a measurement circuit using a microcomputer having a built-in PWM circuit.

A one-chip microcomputer (one-chip microcomputer) having a built-in PWM circuit, an ASIC having a built-in PWM circuit, and the like using a CMOS process are widely used.

FIG. 6 is a block diagram showing a specific example of a conventional DA converter constructed using a microcomputer having a built-in PWM circuit. Conventional DA converter 10 shown in FIG.
Reference numeral 1 denotes a one-chip microcomputer (hereinafter, referred to as a microcomputer) 110 and a low-pass filter circuit 120.

The microcomputer 110 includes a CPU unit 111 and a P
WM circuit unit 112 and PWM signal output buffer circuit unit 1
13 and a ROM, a RAM, various input / output units (not shown) and the like. The CPU unit 111 supplies digital data 111a to be subjected to DA conversion to the PWM circuit unit 112 at every preset DA conversion cycle.

The PWM circuit 112 is a binary counter circuit for counting a counter clock (not shown), and a PWM signal for generating a PWM signal by comparing the magnitude relationship between the count value of the binary counter circuit and the digital data 111a. And a generation unit (not shown). The PWM circuit 112 outputs an H level signal 112a until the count value of the binary counter circuit reaches the value of the digital data 111a supplied from the CPU 111.
And thereafter outputting the L-level signal 112a is repeated every DA conversion cycle.

[0008] The PWM signal output buffer circuit section 113 includes:
PWM based on the output signal 112a of the PWM circuit unit 112
The M signal output terminal 110a is driven with a predetermined driving capability.
As a result, the PWM signal 101a is output from the PWM signal output terminal 110a.

[0009] The PWM signal output buffer circuit section 113 includes:
Inverter 114, p-channel transistor 115 for outputting H level, and n for outputting L level
And a channel transistor 116. The output signal 112a is supplied to an input terminal of the inverter 114. The output terminal of the inverter 114 is connected to the gates of the transistors 115 and 116, respectively. p
The source of the channel transistor 115 is a circuit power supply VC.
C (or reference power supply + VREF). p
The drain of the channel transistor 115 and the drain of the n-channel transistor 116 are connected together, and the connection point is connected to the PWM signal output terminal 110a. The source of the n-channel transistor 116 is connected to a ground power supply (GND).

The low-pass filter circuit 120 includes a resistor 12
1 and a capacitor 122. In FIG. 6, a passive filter having a first-order filter is illustrated. However, according to the filter characteristics (cutoff frequency, attenuation, level fluctuation in a pass band, etc.) required for a low-pass filter, a resistor and a capacitor are used. A secondary or tertiary passive filter in which two or three stages of circuits are connected in series, or an active filter configured using an operational amplifier or the like may be used.

Next, the conventional DA converter 1 shown in FIG.
01 will be described. The PWM circuit unit 112 generates and outputs a signal 112a having a duty cycle corresponding to the digital data 111a to be DA-converted, in which the cycle of the pulse signal is the DA conversion cycle. This signal 112a is PW
The PWM signal 101a is output from the PWM signal output terminal 110a via the M signal output buffer circuit 113 as a PWM signal 101a, and high-frequency components are removed (smoothed) by the low-pass filter circuit 120, and an analog output signal is output. DA
The digital data 111a to be converted is, for example, 10
With a bit configuration, a DA converter having a resolution of 10 bits can be configured.

[0012]

FIG. 7 is a graph showing the output characteristics of the conventional DA converter shown in FIG. The horizontal axis indicates the value of the digital data and the duty of the PWM signal corresponding to the digital data. Here, digital data having a 10-bit configuration is shown in decimal notation. Further, the duty is shown in percentage (percent) display. The vertical axis indicates the output voltage of the analog output signal. Note that the output voltage of the analog output signal shown here is the output voltage of the analog output signal when the same digital data is repeatedly supplied for each DA conversion cycle.

When the voltage of the circuit power supply VCC (or reference power supply + VREF) shown in FIG.
WM signal duty is 0, output voltage is 0 volt, PWM
When the duty of the M signal is 100, the output voltage becomes 5 volts. A straight line (shown by a virtual line) K1 connecting these two points is an ideal conversion characteristic. However, the conventional DA converter 1
The actual conversion characteristic of 01 is not an ideal straight line as shown by the solid line K2, and an error occurs in the linearity. The output impedance of the PWM signal output buffer circuit 113 shown in FIG. 6 may be a cause of the linearity error.

FIG. 8 is a circuit diagram of an equivalent circuit of a PWM signal output buffer circuit and a low-pass filter circuit.
The PWM signal output buffer circuit unit 113 includes an ideal switch circuit SW, an on-resistance Rp of a p-channel transistor 115, and an on-resistance Rn of an n-channel transistor 116.
And can be represented by Further, the resistance value of the resistor 121 of the low-pass filter circuit 120 is RL.

During the period when the PWM signal is at the H level, the p-channel transistor 115 is turned on and the n-channel transistor 116 is turned off (the ideal switch circuit SW is in a switching state indicated by a solid line). In this state, the circuit power supply VCC
(Here, +5 volts) is supplied to the capacitor 122 via a combined resistance value (Rp + RL) of the ON resistance Rp of the p-channel transistor 115 and the resistance value RL of the resistance 121. During the period when the PWM signal is at the L level, the p-channel transistor 116 is turned off and the n-channel transistor 116 is turned on (the switching state of the ideal switch circuit SW indicated by a dotted line). In this state, the ground power supply (here, 0 volt) is applied to the n-channel transistor 11.
6 is supplied to the capacitor 122 via a combined resistance value (Rn + RL) of the on-resistance Rn of 6 and the resistance value RL of the resistor 121.

In a one-chip microcomputer (one-chip microcomputer), an ASIC, or the like, the on-resistance Rp of the p-channel transistor 115 is
Is generally larger than the on-resistance Rn. The on-resistance Rp of the p-channel transistor 115 is, for example, about 15 ohms,
n is, for example, about 10 ohms.

FIG. 9 is an explanatory diagram showing the operation of the low-pass filter circuit. FIG. 9A shows a PWM signal, and FIG.
9 shows an ideal analog output voltage, and FIG. 9C shows an actual analog output voltage. Here, the case where the duty of the PWM signal is 50% is shown.

Since the circuit power supply VCC (+5 volts in this case) is supplied during the H level period of the PWM signal, the capacitor 122 is charged and the analog output voltage rises. Since ground power (0 volt here) is supplied during the L level period of the PWM signal, the capacitor 122
Is discharged and the analog output voltage falls.

Assuming that the on-resistance Rp of the p-channel transistor 115 is equal to the on-resistance Rn of the n-channel transistor 116 (ideal state), as shown in FIG. The drop rates are equal, and the average value of the analog output voltage is 2.5 volts.

When the on-resistance Rp of the p-channel transistor 115 is larger than the on-resistance Rn of the n-channel transistor 116, as shown in FIG. And the degree of descent becomes relatively steep relative to the ideal state. For this reason, the average value of the analog output voltage (shown by a solid line) is the theoretical value at a duty of 50%.
5 volts (indicated by the dotted line).

For example, when Rp = 15 ohms, Rn = 10 ohms, and RL = 400 ohms, the analog output voltage (average value) is 2.475 volts, and the theoretical value is 2.5 volts.
It is 25 millivolts lower than the bolt.

When the analog output full range (maximum output voltage value) is 5 volts and the resolution is 10 bits, the voltage per bit is approximately 4.88 millivolts (5 volts / 1).
024), and 25 millivolts results in an error of about 5 bits.

To solve such a problem that an error occurs in the analog output voltage due to the influence of the output impedance of the PWM signal output buffer circuit section 113, the following may be considered.

It is conceivable to increase the area of the p-channel transistor to make the on-resistance Rp of the p-channel transistor equal to the on-resistance Rn of the n-channel transistor. However, increasing the area of the p-channel transistor is not preferable because the chip size of a microcomputer, an ASIC, or the like increases.

The drains of the transistors 115 and 116 constituting the PWM signal output buffer circuit 113 are not connected to each other, but are connected to the first output terminal connected to the drain of the p-channel transistor and the drain of the n-channel transistor. And a resistance value (Rp-Rn) between the on-resistance Rp of the p-channel transistor and the n-channel transistor Rn between the second output terminal and the input terminal of the low-pass filter circuit. By providing a circuit configuration in which the first output terminal and the input terminal of the low-pass filter circuit are directly connected together with a resistor having the following, the supply capability of the VCC power supply and the supply capability of the ground power supply can be made the same. I can think. However, this circuit configuration is not preferable because the number of output terminals increases by one.

The source of the n-channel transistor 116 is not connected to the ground power supply in the integrated circuit, but a source terminal connected to the source of the n-channel transistor 116 is provided, and a p-channel transistor is connected between the source terminal and the ground power supply. By providing a resistor having a resistance value (Rp-Rn) that is the difference between the on-resistance Rp and the n-channel transistor Rn, it is possible to make the supply capability of the VCC power supply and the supply capability of the ground power supply the same. However, this circuit configuration is not preferable because the number of terminals is increased by one.

An external switch circuit for supplying VCC power based on the H level of the PWM signal;
An external switch circuit that supplies ground power based on the level is provided, and the on-resistance of each external switch circuit is made equal so that the VCC power supply capacity and the ground power supply capacity are the same. I can think. But,
This circuit configuration is not preferable because the number of external circuits increases.

The present invention has been made to solve such a problem. In a PWM signal output buffer circuit portion built in an integrated circuit such as a microcomputer or an ASIC, the output capability at the H level is higher than the output capability at the L level. It is another object of the present invention to provide a DA converter so that the linearity error of the DA conversion output caused by the small size can be eliminated without changing the hardware configuration.

[0029]

According to a first aspect of the present invention, there is provided a digital-to-analog converter which corrects digital data to be subjected to DA conversion to an output voltage corresponding to the digital data. A data correction means for converting the data into digital data, and a PWM having a duty corresponding to the corrected digital data based on the corrected digital data
A signal is generated, and the generated PWM signal is supplied to a low-pass filter circuit to obtain a DA conversion output.

The DA converter according to claim 1 converts the digital data to be DA-converted into corrected digital data, generates a PWM signal based on the corrected digital data, and outputs the PWM signal via a low-pass filter circuit. Get. Thereby, the linearity error of the DA conversion output can be reduced.

The data correction means may comprise a correspondence data correction table in which digital data to be subjected to DA conversion and corrected digital data from which an output voltage corresponding to the digital data can be actually obtained.

By using the data correction table, conversion into corrected digital data can be performed at high speed.

According to a third aspect of the present invention, there is provided a DA converter, comprising a correction digital data calculating means for calculating correction digital data necessary for generating an output voltage corresponding to the digital data to be DA-converted. Generating a PWM signal having a duty corresponding to the corrected digital data based on the corrected digital data obtained by
The generated PWM signal is supplied to a low-pass filter circuit to obtain a DA conversion output.

According to a third aspect of the present invention, a DA converter converts digital data to be DA-converted into corrected digital data by calculation, and performs PW conversion based on the corrected digital data.
An M signal is generated, and a DA conversion output is obtained via a low-pass filter circuit. Thereby, the linearity error of the DA conversion output can be reduced.

The correction digital data calculation means sets the output resistance at the time of outputting the PWM signal at the H level to Rp and the output resistance at the L level of the PWM signal.
The output resistance at the time of level output is Rn, the input resistance of the low-pass filter circuit section is RL, and the H level voltage of the PWM signal is V.
When the L level voltage of the H and PWM signals is VL, the H level period of the PWM signal is TH, and the L level period of the PWM signal is TL, the output voltage V can be expressed by the following equation. ,

(Equation 3) The correction digital data required to generate the output voltage corresponding to the digital data may be obtained.

The correction digital data calculation means sets the output resistance when the PWM signal is at the H level to Rp, and sets the output resistance to the L level of the PWM signal.
The output resistance at the time of level output is Rn, the input resistance of the low-pass filter circuit section is RL, and the H level period of the PWM signal is T.
By using the fact that the substantial duty DH can be expressed by the following equation when the period of the L level of the H and PWM signals is TL,

(Equation 4) The correction digital data required to generate the output voltage corresponding to the digital data may be obtained.

The output resistance when the PWM signal is output at the H level is Rp, the output resistance when the PWM signal is output at the L level is Rn,
In addition, in consideration of RL, the input resistance of the low-pass filter circuit section is used to obtain corrected digital data so that the substantial duty DH becomes a value specified by the digital data.
By generating a PWM signal based on the obtained corrected digital data and obtaining a DA conversion output via a low-pass filter circuit, a linearity error of the DA conversion output can be reduced.

In the digital-to-analog converter according to the first aspect, the data correction means includes a correction amount data table in which digital data to be subjected to the digital-to-analog conversion is associated with correction amount data for the digital data. Alternatively, a configuration may be provided that includes a data correction unit that calculates corrected digital data based on digital data to be subjected to digital-to-analog conversion and correction amount data for the digital data.

By using a configuration in which the correction amount is stored in the data table, the amount of data to be stored can be reduced. When digital data to be subjected to digital-to-analog conversion is, for example, 10 bits, the correction amount is a small value of about 1 to 3 bits. Therefore, the data amount of the data table can be reduced as compared with the case where 10-bit corrected digital data is stored in the data table. For example, when the data table is configured by a semiconductor memory such as a ROM, the storage capacity can be reduced.
Reading the correction amount of several bits (1 to 3 bits) from the data table and adding the correction amount read from the data table to the digital data to be subjected to the digital-to-analog conversion (subtracting when the correction value is negative) To obtain corrected digital data.

Further, the correction amount data table may include correction amount data corresponding to a plurality of upper bits of digital data to be subjected to digital / analog conversion.

The correction amount data has the same value over a relatively wide range of digital data to be subjected to digital-to-analog conversion. Therefore, by providing a configuration in which the correction amount data is provided corresponding to a plurality of upper bits of digital data to be subjected to digital-to-analog conversion, the data amount of the correction amount data table can be further reduced.

[0042]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a DA converter according to the first embodiment. The DA converter 1 shown in FIG. 1 includes a microcomputer 10 and a low-pass filter circuit 20. The microcomputer 10 includes a CPU unit 11, a data correction unit 14,
PWM circuit section 12 and PWM signal output buffer circuit section 1
3 and a ROM, a RAM, various input / output units (not shown) and the like. The PWM signal output buffer circuit unit 13 includes an inverter 13I, a p-channel transistor 13P, and an n-channel transistor 13N. The low-pass filter circuit 20 is constituted by a passive low-pass filter having a first-order filter composed of an input resistor RL and a capacitor C1.

The CPU section 11 outputs digital data 11a to be subjected to DA conversion at every preset DA conversion cycle. In this embodiment, 10-bit digital data 11a is output. The digital data 11a is supplied to the data correction means 14.

The data correction means 14 outputs the digital data 1
The correction digital data 14a necessary for actually obtaining the analog output voltage V corresponding to the digital data 11a is output based on 1a. This data correction means 14
Converts the digital data 11a to the corrected digital data 14a
It is configured using a data correction table that converts the data into a data.
The correction digital data 14a is supplied to the PWM circuit unit 12.

The PWM circuit section 12 generates a PWM signal by comparing the magnitude relationship between the count value of the binary counter circuit section and the corrected digital data 14a with a binary counter circuit section (not shown) that counts a counter clock (not shown). A signal generator (not shown). The PWM circuit unit 12 outputs the H-level signal 12a until the count value of the binary counter circuit unit reaches the value of the corrected digital data 14a, and thereafter outputs the L-level signal 12a, by DA conversion. Repeat every cycle.

When the signal 12a is at the H level, the PWM signal output buffer circuit 13 drives the p-channel transistor 13P to the on state and the n-channel transistor 13N to the off state via the inverter 13I. VCC via the channel transistor 13P
The power supply (here, +5 volts) is connected to the low-pass filter circuit 2
0. The PWM signal output buffer circuit unit 13 includes:
When the signal 12a is at the L level, the p-channel transistor 13P is driven off via the inverter 13I and the n-channel transistor 13N is driven on, and the ground power supply (here, the power supply) via the n-channel transistor 13P. 0 volts) to the low pass filter circuit 20.

The low-pass filter circuit 20 includes the microcomputer 1
The high-frequency component of the PWM signal 10a output from 0 is removed (smoothing the PWM signal 10a), and an analog output signal (DA conversion output) is output.

When, for example, 512 is set in decimal notation by the 10-bit digital data 11a,
Conventionally, a signal 12a having a duty of 50% (512/1024) is generated by the PWM circuit unit 12, and based on the signal 12a, the PWM signal output buffer circuit unit 1
PWM signal 10 with 50% duty via 3
a, and an analog output signal of, for example, 2.5 volts (when the power supply voltage of the VCC power supply is 5 volts) is obtained through the low-pass filter circuit 20.

However, the on-resistance (output resistance at the time of H-level output) Rp of the p-channel transistor 13P constituting the PWM signal output buffer circuit section 13 is equal to the on-resistance (output resistance at the time of L-level output) Rn of the n-channel transistor 13N. Otherwise, the voltage of the analog output signal will be slightly lower than the target 2.5 volts.

Therefore, when the digital data 11a is 512 in decimal notation, the corrected digital data 14a (for example, 515 in decimal notation) that can actually obtain a voltage of 2.5 volts to be output corresponding to the data. ) Is obtained in advance. Then, the value of 512 is converted into, for example, 515, and supplied to the PWM circuit unit 12, so that the duty corresponding to 515 in decimal notation (515/102
4) The PWM signal is generated. Thereby, an output voltage of 2.5 volts corresponding to the digital data 11a can be obtained.

The data correction means 14 stores correction digital data preset for each digital data (0 to 1024 in decimal notation) in a table format. Then, the data correction means 14 outputs the digital data 11a
Output the corrected digital data 14a.

FIG. 2 is an explanatory diagram showing a specific example of the data correction table. The data correction table shown in FIG.
The ON resistance (output resistance at the time of H level output) Rp of the channel transistor 13P is 15 ohms, and the ON resistance (output resistance at the time of L level output) R of the n-channel transistor 13N is R
The figure shows corrected digital data when n is 10 ohms and the input resistance RL of the low-pass filter circuit 20 is 400 ohms.

The correction digital data may be obtained based on the measurement result of the analog output voltage. Further, by utilizing the fact that the analog output voltage V can be approximated by the following equation 1, the corrected digital data may be obtained in advance by calculation.

[0055]

(Equation 5)

Here, Rp is a p-channel transistor 1
3P ON resistance (output resistance at H level output), Rn is ON resistance of n channel transistor 13N (output resistance at L level output) Rn, TH is H level period of PWM signal, and TL is L level of PWM signal. During the level period, VCC is the power supply voltage of the circuit power supply.

When using 10-bit digital data, one cycle of the PWM signal is 1024, where Tc is the cycle of the reference clock for generating the PWM signal.
× Tc. If the digital data is represented by X in decimal notation, the H level period of the PWM signal is X × Tc,
The period TL of the L level of the WM signal is (1024−X) × T
c. Since the period Tc of the reference clock can be deleted,
The above equation 1 can be expressed by the following equation 2.

[0058]

(Equation 6)

Therefore, when digital data having a 10-bit configuration is used, the corrected digital data X for obtaining the target analog output voltage V may be obtained by using the above equation (2).

The correction digital data obtained in advance is written as a data correction table in a nonvolatile memory such as a ROM.

With the above configuration, the DA converter 1 shown in FIG. 1 converts the digital data 11a to be DA-converted by the data
4a, generates a PWM signal 10a based on the converted corrected digital data 14a, and obtains a DA conversion output (analog output signal) via the low-pass filter circuit 20. PWM signal output buffer circuit section 13
In this configuration, it is possible to eliminate the correction of the digital data for the linearity error of the analog output voltage caused by the difference between the output capability at the H level output and the output capability at the L level output. The linearity error of the analog output signal can be reduced. Therefore, a highly accurate voltage corresponding to the digital data to be DA-converted can be obtained.

FIG. 3 is a block diagram of another DA converter according to the first embodiment. The DA converter 2 shown in FIG.
The data correcting means 34 operates under the control of a programmer using the CPU 31 of the microcomputer 30. The data correction unit 34 includes a correction condition storage unit 35 and a data correction unit 36. The correction condition storage unit 35 corresponds to a correction amount data table in the claims. The configurations of the PWM circuit section 12, the PWM signal output buffer circuit section 13 and the low-pass filter circuit 20 are shown in FIG.
Is the same as that shown in FIG.

The correction condition storage unit 35 stores a correction value for adding and correcting digital data to be DA-converted to the digital data. 10 digital data
An example of the relationship between the range of the digital data and the correction value as a bit is shown below. When the digital data is in decimal notation, the range of 0 to 64 is the correction value 0, the range of 65 to 192 is the correction value +1, the range of 193 to 320 is the correction value +2, 1,
The range from 94 to 704 is the correction value +3, the range from 705 to 832 is the correction value +1, the range from 833 to 960 is the correction value +1,
The range from 961 to 1024 is set to the correction value 0.

The data correction section 36 receives a signal from the CPU section 31
When the digital data 11a to be A-converted is supplied, a correction value corresponding to the value of the digital data 11a is obtained from the correction condition storage unit 35 based on the value of the digital data 11a, and the obtained correction value is obtained. Digital data 1
1a to generate corrected digital data 14a,
The generated correction digital data 14a is transmitted to the PWM circuit 12
Supply to

For example, if the digital data 11a to be subjected to DA conversion is 512 in decimal notation, the value 5
12 is +3, the data correction unit 3
6 supplies the value of 515 obtained by adding 3 to 512 to the PWM circuit unit 12 as corrected digital data 14a.

With the above configuration, the D / A converter 2 shown in FIG. 3 is similar to the D / A converter 1 shown in FIG.
The digital data 11a to be A-converted is converted into corrected digital data 14a capable of actually obtaining an output voltage designated by the digital data 11a, and the PWM signal 10 is converted based on the converted corrected digital data 14a.
Since a is generated, a voltage that is the same as or very close to the output voltage specified by the digital data 11a can be output via the low-pass filter 20. Therefore, DA
The linearity error of the conversion output (analog output signal) can be reduced, and a highly accurate voltage corresponding to the digital data to be DA-converted can be obtained.

The correction condition storage unit 35 sets the correction range of the digital data 11a more finely than the above, and sets a correction value having a value after the decimal point such as +0.5, +1.5, +2.25. May be set. Here, when the correction value is +0.5, when the same digital data 11a is continuously supplied, the data correction unit 36 does not perform any correction with the corrected digital data obtained by adding +1 to the digital data 11a. Data (that is, digital data 11a) is output alternately. When the correction value is +1.5, when the same digital data 11a is continuously supplied, the data correction unit 36 alternately changes the correction digital data obtained by adding +1 to the digital data 11a and the correction digital data obtained by adding +2 to the digital data 11a. Output. When the correction value is +2.25, when the same digital data 11a is continuously supplied, the data correction unit 36 adds the corrected digital data obtained by adding +2 to the digital data 11a to 3
After output once, output of corrected digital data obtained by adding +3 to digital data is repeated once.

As described above, by employing the averaging process of the PWM signal over a plurality of cycles, the analog output voltage can be adjusted in steps smaller than one bit (1 LSB) of digital data. For example, the full range is 5 volts and the resolution is equivalent to 10 bits (1024 steps)
In this case, the voltage corresponding to one bit is about 4.88 millivolts, and the output voltage changes in units of about 4.88 millivolts. On the other hand, by averaging the PWM signal over a plurality of cycles, for example, about 1.
The output voltage can be adjusted in units of 22 millivolts. Therefore, using the DA converter according to the present invention,
It is possible to generate a DC reference voltage or the like with high accuracy.

The correction value is the same over a relatively wide range of digital data to be subjected to digital-to-analog conversion. Therefore, the correction condition storage unit 35 may be configured to store a correction value corresponding to a plurality of upper bits of digital data to be subjected to digital-to-analog conversion. For example, if the digital data to be digital-to-analog converted is 1
In the case of 0 bits, a correction value is obtained by designating, for example, the upper 6 bits. With such a configuration, the amount of data stored in the correction condition storage unit 35 can be significantly reduced. In this case, the data correction unit 3
6 supplies the upper 6 bits of the digital data 11a to be subjected to the digital-to-analog conversion to the correction condition storage unit 35, and obtains a correction value corresponding to the upper 6 bits. Then, the data correction unit 36 obtains the correction digital data 14a by adding a correction value to the digital data 11a to be subjected to the digital-to-analog conversion, and supplies the obtained correction digital data 14a to the PWM circuit unit 12.

FIG. 4 is a block diagram of a DA converter according to a third aspect. The DA converter 3 shown in FIG. 4 includes a microcomputer 40 and a low-pass filter circuit 20. The microcomputer 40 includes a CPU 41, a PWM circuit 12,
It includes a WM signal output buffer circuit section 13 and the like. The correction digital data calculating means 42 which operates under the control of the programmer using the CPU 41 is constituted. PWM circuit section 12, PWM signal output buffer circuit section 13, and
The configuration of the low-pass filter circuit 20 is the same as that shown in FIG.

The correction digital data calculation means 42 outputs the CP
When the m-bit digital data 11a to be subjected to DA conversion is supplied from the U unit 41, first, the output voltage VA specified by the digital data 11a is calculated by the following equation (3).
Calculate based on

[0072]

(Equation 7)

Here, VA is the output voltage (theoretical value), DD
Is a value (decimal notation) designated by the digital data 11a, m is the number of bits of digital data to be subjected to DA conversion, and VCC is a power supply voltage of a circuit power supply.

For example, the bit number m of digital data is set to 1
0, the value specified by the digital data 11a (10
Assuming that DD is 512 and the power supply voltage of the circuit power supply is 5 volts, the output voltage (theoretical value) VA is 2.5 volts ((512/1024) × 5 volts).

Next, the correction digital data calculation means 42
Is the output voltage (theoretical value) previously obtained using the fact that the output voltage V actually output can be expressed by the following equation 4.
Corrected digital data X that provides an output voltage V closest to VA (for example, 2.5 volts) is obtained by calculation.

[0076]

(Equation 8)

Here, V is the actual output voltage, X is the corrected digital data (decimal notation), Rp is the on-resistance of the p-channel transistor 13P (output resistance at the time of H level output), and Rn is the n-channel transistor 13N. On resistance (output resistance at the time of L level output), RL is an input resistance of the low-pass filter circuit 20, m is the number of bits of digital data, and VCC is a power supply voltage of a circuit power supply.

The corrected digital data (decimal notation)
X corresponds to an H-level period TH of the PWM signal described in the claims. (2 m -X) is the L level period T of the PWM signal described in the claims.
L. Power supply voltage VCC for circuit power supply
Is equivalent to the difference (VH-VL) between the H-level potential VH of the PWM signal and the L-level potential VL of the PWM signal described in the claims.

The correction digital data calculation means 42 calculates
Is calculated based on the calculated digital data X that provides the output voltage V closest to the output voltage (theoretical value) VA.
Supply to

The PWM circuit section 12 generates and outputs a signal 12a having a duty corresponding to the corrected digital data X based on the corrected digital data X. This signal 12
a is the PWM signal via the PWM signal output buffer circuit 13
The signal is supplied to the low-pass filter circuit 20 as the M signal 10a, and an analog output signal (DA conversion output) is obtained through the low-pass filter circuit 20.

With the above configuration, the DA converter 3 shown in FIG. 4 converts the digital data 11a to be subjected to DA conversion by the correction digital data calculating means 42 into an output voltage specified by the digital data 11a. Is converted into obtainable corrected digital data 14a (X),
Since the PWM signal 10a is generated based on the converted corrected digital data 14a (X), the low-pass filter 2
A voltage which is the same as or very close to the output voltage specified by the digital data 11a can be output via the "0". Therefore, the linearity error of the DA conversion output (analog output signal) can be reduced, and a highly accurate voltage corresponding to the digital data to be DA converted can be obtained.

On-resistance of p-channel transistor 13P (output resistance at the time of H-level output) Rp, on-resistance of n-channel transistor 13N (output resistance at the time of L-level output)
Each value of Rn, the input resistance RL of the low-pass filter circuit 20, the power supply voltage VCC of the circuit power supply, and the like uses a preset value.

Note that these values Rp, Rn, RL, VC
C may be configured to be set via an input port (not shown). With a configuration in which these values Rp, Rn, RL, and VCC can be set from the outside, it is possible to cope with variations in the on-resistances Rp and Rn of each transistor. This makes it possible to obtain a more accurate DA conversion output corresponding to the characteristics of each chip such as a microcomputer or an ASIC. Further, by setting the measured values of the on-resistances Rp and Rn of each transistor,
The accuracy and linearity of the DA conversion output can be further improved. Further, it is possible to cope with a change in circuit conditions such as a change in the power supply voltage VCC and a change in the resistance value of the input resistor RL of the low-pass filter circuit 20.

The correction digital data calculation means 42 calculates
(Rp + RL) / (R
Since the term (n + RL) is a fixed value, the fixed value is calculated in advance, and the calculation result is used repeatedly. Thereby, the operation speed is increased.

The correction digital data calculation means 42
May store a result of calculation in the past in a RAM or a non-volatile memory to create a correspondence table between digital data DD to be DA-converted and corrected digital data X. Good. With such a configuration, it is possible to reduce the number of times of performing the arithmetic processing for obtaining the correction digital data X. Thereby, C
The load on the PU unit 41 can be reduced.

The correction digital data calculation means 42 generates correction digital data X1 capable of outputting, for example, 2.498 volts with respect to output voltage (theoretical value) of 2.5 volts, for example, and 2.503 volts. When the corrected digital data X2 that can be output is calculated, the corrected digital data X1 and X2 are alternately supplied to the PWM circuit unit 12 so that the output voltage (theoretical value) VA becomes 2.5. It may be made closer to the bolt. Further, the selection ratio of the corrected digital data X1, X2 is, for example, 1: 2, 2: 1, 1: 3, 3: 1,
By setting such as 1: 4, 4: 1, etc., the average value of the analog output voltage in a predetermined period may be closer to the theoretical value.

FIG. 5 is a block diagram of a DA converter according to a fifth aspect. The DA converter 4 shown in FIG. 5 includes a microcomputer 50 and a low-pass filter circuit 20. The microcomputer 50 includes a CPU unit 51, a PWM circuit unit 12,
It includes a WM signal output buffer circuit section 13 and the like. The CPU 51 constitutes a correction duty calculation means 52 that operates under programmer control. PWM circuit part 1
2. The configurations of the PWM signal output buffer circuit unit 13 and the low-pass filter circuit 20 are the same as those shown in FIG.

When the m-bit digital data 11a to be subjected to DA conversion is supplied from the CPU section 51, the correction duty calculating means 52 first receives the digital data 11a.
The duty D of the PWM signal specified by a is calculated based on the following equation 5.

[0089]

(Equation 9)

Here, D is the duty (theoretical value) of the PWM signal, DD is the value (decimal notation) specified by the digital data 11a, and m is the number of bits of the digital data to be DA-converted.

For example, if the bit number m of the digital data is 1
0, the value specified by the digital data 11a (10
Assuming that DD is 512, the duty (theoretical value) of the PWM signal is 0.5 (512/1024).

Next, the correction duty calculation means 52 calculates P
Taking into account the output resistance of the WM signal output buffer circuit section 13 and the input resistance of the low-pass filter circuit 20, the fact that the actual duty (correction duty) DH can be expressed by the following equation 6 is used to calculate the duty obtained earlier. Corrected digital data X that gives a value closest to (theoretical value) is obtained by calculation.

[0093]

(Equation 10)

Here, X is the corrected digital data (decimal notation), Rp is the on-resistance of the p-channel transistor 13P (output resistance at the time of H level output), and Rn is the on-resistance of the n-channel transistor 13N (at the time of L level output). RL is the input resistance of the low-pass filter circuit 20, m
Is the number of bits of digital data.

The corrected digital data (decimal notation)
X corresponds to an H-level period TH of the PWM signal described in the claims. (2 m -X) is the L level period T of the PWM signal described in the claims.
L.

The correction digital data calculation means 52 calculates
When the correction digital data X that obtains the value closest to the duty (theoretical value) is calculated based on the calculation, the calculated correction digital data X is supplied to the PWM circuit unit 12.

The PWM circuit section 12 generates and outputs a signal 12a having a duty corresponding to the corrected digital data X based on the corrected digital data X. This signal 12
a is the PWM signal via the PWM signal output buffer circuit 13
The signal is supplied to the low-pass filter circuit 20 as the M signal 10a, and an analog output signal (DA conversion output) is obtained through the low-pass filter circuit 20.

With the above configuration, the DA converter 4 shown in FIG. 5 converts the digital data 11a to be DA-converted into the corrected digital data 14a (X) by the corrected digital data calculating means 52, and the converted data is converted. Since the PWM signal 10a is generated based on the corrected digital data 14a (X), a voltage that is the same as or very close to the output voltage specified by the digital data 11a can be output via the low-pass filter 20. Therefore, the linearity error of the DA conversion output (analog output signal) can be reduced,
Further, a highly accurate voltage corresponding to digital data to be subjected to DA conversion can be obtained.

The DA converter 4 shown in FIG. 5 uses the correction digital data 14a based on the correction duty DH.
Since the calculation of (X) is performed, the amount of calculation for obtaining the corrected digital data 14a (X) can be made smaller than that of the DA converter 3 shown in FIG. Thereby, the load on the CPU unit 51 can be reduced.

On-resistance of p-channel transistor 13P (output resistance at the time of H-level output) Rp, on-resistance of n-channel transistor 13N (output resistance at the time of L-level output)
Each value of Rn, the input resistance RL of the low-pass filter circuit 20, and the like is configured to use a preset value.

Incidentally, the configuration may be such that these values Rp, Rn, RL can be set via an input port (not shown). With a configuration in which these values Rp, Rn, and RL can be set from the outside, the on-resistances Rp and R
It is possible to deal with variations in n. This makes it possible to obtain a more accurate DA conversion output corresponding to the characteristics of each chip such as a microcomputer or an ASIC. Further, by setting the measured values of the on-resistances Rp and Rn of each transistor, the accuracy and linearity of the DA conversion output can be further improved.
In addition, a change in the power supply voltage VCC or a low-pass filter circuit 2
It is possible to cope with a change in circuit conditions such as a change in the resistance value of the input resistance RL of 0.

The correction digital data calculation means 52 calculates
(Rp + RL) / (R
Since the term (n + RL) is a fixed value, the fixed value is calculated in advance, and the calculation result is used repeatedly. Thereby, the operation speed is increased.

The correction digital data calculation means 52
May store a result of calculation in the past in a RAM or a non-volatile memory to create a correspondence table between digital data DD to be DA-converted and corrected digital data X. Good. With such a configuration, it is possible to reduce the number of times of performing the arithmetic processing for obtaining the correction digital data X. Thereby, C
The load on the PU unit 51 can be reduced.

The correction digital data calculation means 52 has a duty (theoretical value) D of, for example, 0.5 and a substantial duty (correction duty) DH of, for example, 0.499.
6 and the corrected digital data X2 having a substantial duty (corrected duty) DH of, for example, 0.5006, are calculated by alternately using the corrected digital data X1 and X2. You may make it supply to the part 12. Thereby, the accuracy of the output voltage can be improved. Further, the ratio of selecting the corrected digital data X1 and X2 is set to, for example, 1:
The average value of the analog output voltage during a predetermined period may be closer to the theoretical value by setting the ratio to 2,2: 1,1: 3,3: 1,1: 4,4: 1 or the like.

[0105]

As described above, the digital-to-analog converter according to the present invention converts digital data to be subjected to digital-to-analog conversion into corrected digital data from which an output voltage corresponding to the digital data can be actually obtained. Since the pulse width modulation signal is generated based on the corrected digital data, the accuracy of the analog output voltage can be improved and the linearity of the digital-to-analog conversion output characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DA converter according to claim 1;

FIG. 2 is an explanatory diagram showing a specific example of a data correction table.

FIG. 3 is a block diagram of another DA converter according to claim 1;

FIG. 4 is a block diagram of a DA converter according to claim 3;

FIG. 5 is a block diagram of a DA converter according to claim 5;

FIG. 6 is a block diagram illustrating a specific example of a conventional DA converter configured using a microcomputer having a built-in PWM circuit.

FIG. 7 is a graph showing output characteristics of the conventional DA converter shown in FIG.

FIG. 8 is a circuit diagram of an equivalent circuit of a PWM signal output buffer circuit unit and a low-pass filter circuit.

FIG. 9 is an explanatory diagram showing an operation of the low-pass filter circuit.

[Explanation of symbols]

1, 2, 3, 4 DA converter 10, 30, 40, 50 Microcomputer (microcomputer) 11, 31, 41, 51 CPU section 12 PWM circuit section 13 PWM signal output buffer circuit section 14, 34 Data correction means 20 Low pass Filter circuit 35 Correction condition storage unit 36 Data correction unit 42, 52 Correction digital data calculation means

Claims (7)

[Claims] 1. A data correction means for converting digital data to be subjected to digital-to-analog conversion into corrected digital data capable of actually obtaining an output voltage corresponding to the digital data. A digital-to-analog converter, wherein a pulse-width modulation signal having a duty corresponding to the corrected digital data is generated, and the generated pulse-width modulation signal is supplied to a low-pass filter circuit to obtain a digital-to-analog conversion output. 2. The digital-to-analog conversion apparatus according to claim 1, wherein said data correction means comprises a data correction table in which digital data to be subjected to digital-to-analog conversion is associated with the corrected digital data. . 3. Compensated digital data calculating means for calculating corrected digital data required to generate an output voltage corresponding to digital data to be subjected to digital-to-analog conversion, wherein the corrected digital data obtained by the calculation is provided. A digital-to-analog conversion, wherein a pulse-width modulation signal having a duty corresponding to the corrected digital data is generated based on the digital-to-analog conversion data, and the generated pulse-width modulation signal is supplied to a low-pass filter circuit to obtain a digital-to-analog conversion output. apparatus. 4. The correction digital data calculation means includes an output resistance Rp when the pulse width modulation signal is output at the H level, an output resistance Rn when outputting the pulse width modulation signal at the L level, an input resistance of the low-pass filter circuit unit. RL, the H level voltage of the pulse width modulation signal is VH, the L level voltage of the pulse width modulation signal is VL, the H level period of the pulse width modulation signal is TH, and the L level period of the pulse width modulation signal is TL. Using the fact that the output voltage V can be expressed by the following equation, 4. The digital-to-analog converter according to claim 3, wherein corrected digital data required to generate an output voltage corresponding to the digital data is obtained. 5. The correction digital data calculating means includes an output resistance Rp when the pulse width modulation signal is output at the H level, an output resistance Rn when outputting the pulse width modulation signal at the L level, an input resistance of the low-pass filter circuit unit. Is RL, the H level period of the pulse width modulation signal is TH, and the L level period of the pulse width modulation signal is TL, the output resistance Rp when the pulse width modulation signal is output at the H level, and the L level of the pulse width modulation signal. Utilizing that the substantial duty DH in consideration of the output resistance Rn at the time of level output and the input resistance RL of the low-pass filter circuit can be expressed by the following equation: 5. The digital-to-analog converter according to claim 4, wherein corrected digital data required to generate an output voltage corresponding to the digital data is obtained. 6. The data correction means includes a correction amount data table in which digital data to be subjected to digital-to-analog conversion and correction amount data for the digital data are associated with each other, and the digital-to-digital conversion target is 2. The digital-to-analog converter according to claim 1, further comprising a data correction unit that calculates correction digital data based on the data and the correction amount data for the digital data. 7. The digital data according to claim 6, wherein the correction amount data table includes the correction amount data corresponding to a plurality of upper bits of digital data to be subjected to the digital-to-analog conversion. Analog converter.