JP2001101075A - Disk storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the speed of the interruption of pre-reading processing when a write/read command from a host is issued during the pre-reading processing of a cache memory in a disk device on which a cache memory is loaded. SOLUTION: An interface is provided with a function for detecting a command. Upon receiving the command from a host, the interface issues a command detection interfering signal to a sequencer, and the sequencer interrupts the transfer of pre-read data by controlling a data multiplexer, and stops pre-reading by stopping a disk formatter, and calculates the data transferring position of a cache memory by operating a sector boundary calculating circuit and a leading address register and an address pointer. Upon receiving a write command, write data are written from an address following the pre-read data interrupting position of the cache memory, and upon receiving a read command, when any data requested by the host are not present in the cache memory, the pre-reading is stopped, and seek is started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device equipped with a cache memory, and more particularly to control of a cache memory having a prefetch function.

[0002]

2. Description of the Related Art In a storage device using a magnetic disk, an access speed of the magnetic disk is considerably lower than a data transfer speed of a host using the magnetic disk. For this reason, cache memories have conventionally been mounted on storage devices using magnetic disks. By using this, the data once read from the magnetic disk is stored in the cache memory, and the LB following the logical block address (hereinafter, LBA) of the data once requested by the host is used.
The data transfer speed to the host has been improved by using a function called read-ahead in which the data of A is read in advance from the magnetic disk.

By the way, depending on the specifications of an interface of a storage device using a magnetic disk, there is a case where a write command and write data are continuously transferred from a host. In this case, while receiving the write command,
Transfer the write data to the cache memory. And
If the prefetch is being performed, the prefetch is stopped and the write data is stored in the cache memory. On the other hand, the servo system control device is operated under the control of the CPU of the magnetic disk device to seek the write data recording position on the magnetic disk. When the seek is completed, the write data stored in the cache memory is written on the disk drive. In the prior art, as described in JP-A-11-110291, read-ahead control is performed at the firmware level. The control performed by the firmware is
Generally, the operation is slower than the prefetch operation performed by hardware.

Also, when a read command is received from the host, if there is no data requested to be read in the cache memory and further prefetching is being performed, prefetching is stopped at the firmware level. Then, an area on the magnetic disk drive where the data requested to be read exists is sought to read out the corresponding data, transferred to the cache memory, and stored.

[0005]

Generally, when a write command is received, a function called auto-write is used in which a disk controller automatically transfers write data to a cache memory under the control of hardware without the intervention of firmware. Can be On the other hand, when the disk controller is performing prefetch processing on the cache memory, it takes time until the firmware actually completes the prefetch suspension processing in response to the write command, and the prefetch is not immediately stopped. , Prefetching continues to some extent. For example, there is a case where it is necessary to look at a margin of several tens to several hundred sectors until the prefetch stops. For this reason, if write data is transferred to the cache memory immediately after the current prefetch position and writing is performed, a problem occurs that the write data is overwritten by the next prefetch data that continues. For this reason, an auto-write pointer indicating the write data transfer start position is set in advance so that the write data is transferred to a position at a fixed interval from the current pre-read position. That is, the write data is written at a position spaced by the maximum expected amount of the prefetched sector until the prefetch is actually stopped by the control of the firmware. However, with this method, look-ahead (LA)
The area between the position where H: Look Ahead stops and the write data write start position is wasted.

Further, in the above-mentioned prior art, when a read command is received, if the data requested by the host does not exist in the cache memory, the pre-reading is interrupted by the firmware and then the magnetic disk is moved to the position where the data exists. Since the seek is performed, there is a problem that it takes time from the reception of the read command to the start of the seek.

An object of the present invention is to stop prefetching into a cache memory early.

Another object of the present invention is to improve the problem of wasting the area between the position where the prefetching is stopped and the write data transfer start position, and improve the efficiency of use of the cache memory.

Another object of the present invention is to improve the problem that it takes a long time from the reception of the read command to the start of the seek due to the control of the prefetch by the firmware. The goal is to reduce the time to start.

[0010]

In order to achieve the above object, when a command is transmitted from a host, a command detection circuit having means for detecting the command and generating an interrupt, and a disk formatter receiving the interrupt are provided. And a sequencer that interrupts the prefetching by interrupting data transfer from the cache memory to the cache memory and stopping the disk formatter. In this way, prefetching is interrupted by hardware. In the case of a write command, the address in the cache memory at the head of the last prefetched sector is calculated from the address pointer that records the position in the cache memory where the prefetch was interrupted and the value of the address pointer. Equipped with a sector boundary calculation circuit having means and a sequencer having means for setting a calculation result of the sector boundary calculation circuit to an auto-write pointer and executing auto-write to write write data immediately after pre-read data in the cache memory The disk storage device is configured.

In the case of a read command, the prefetching is similarly interrupted, and the data requested by the host is recorded in the cache memory according to the instruction of the CPU, or the prefetching is restarted.

[0012]

FIG. 1 is an example of a configuration diagram of an information device using a hard disk configured according to the present invention. Here, a schematic configuration portion is shown, and details will be described later. The host 101 is connected to the hard disk 102 using a bus 118. The hard disk 102 which is a disk storage device is a disk controller 1
03, cache memory 104, ROM 105, CPU
106, a servo system control circuit 107 and a disk drive 108. Disk control device 103
Are an interface 109, a sequencer 110, a sector boundary calculation circuit 111, a head address register 112, an address pointer 113, and an address multiplexer 11.
4. It has a data multiplexer 115, an ECC 116, and a disk formatter 117.

The cache memory 104 may store data to be transmitted and received between the hard disk 102 and the host 101, and may also store information such as a segment management table for managing data in the cache memory 104. In this embodiment, a segment management table is stored in the work area of the cache memory. The ROM 105 stores firmware, control parameters, and the like necessary for controlling the hard disk 102. The CPU 106 is used for executing firmware and controlling the servo control circuit 107.

The servo system control circuit 107 controls the mechanical system of the disk drive 108 and related parts (for example, a seek operation in response to a write command or a read command). The disk drive 108 includes a magnetic disk for recording data, an R / W channel for performing data conversion between a signal from the magnetic disk and a disk formatter to perform read / write, and a mechanical system for controlling the magnetic disk. ing.

The disk formatter 117 includes a data format management circuit for the disk drive, an error check circuit, a circuit for modulating data and writing the data to the disk drive 108, a circuit for demodulating and reading a signal detected from the disk drive 108, and a read / write circuit. And a circuit for performing a process for stopping the operation. The interface 109 is connected to the host 101 via a bus 118, controls actual data transfer between the host 101 and the hard disk 102, and places necessary data on the internal data bus 125. Then, if necessary, a specific command is detected, a command detection interrupt signal 120 is issued, and the sequencer 11
Inform 0 that a particular command has been received.

The sequencer 110 is a hardware control circuit. The sequencer 110 uses the interface control signal 119 and the module control signal 129 to control the disk controller 103.
And the cache memory 104 are controlled. Further, an interrupt is generated to the CPU 106 as necessary. The sector boundary calculation circuit 111 refers to the value of the address pointer 113 at the time of stopping prefetching and corrects the value of the address pointer 113 to a value corresponding to the sector boundary. Then, the corrected value of the address pointer 113 is set in the head address register 112. The start address register 112 is provided in the cache memory 10 for transferring data.
4 is stored. Address pointer 113
Is the prefetch and the cache memory 104 from the host 101
When write data is transferred to the cache memory 10
4 is updated in accordance with the writing of data.

The address multiplexer 114 has an internal address bus 126 and a CPU address bus 122 in the disk controller 103 connected to the cache memory 104.
And the formatter address bus 127 is switched. The data multiplexer 115 is connected to the CPU data bus 123, the formatter data bus 128, and the disk controller 1
3 controls the connection with the internal data bus 125. E
The CC 116 is connected to the disk formatter 117 via the ECC data bus 130, and performs error correction of data read from the disk drive 108. The disk formatter 117 performs data transfer with the disk drive 108 via the signal bus 132.

The cache memory 10 used in the present invention
4 will be described. The segment is variable in length and includes a plurality of fixed-length sectors (for example, 512 bytes). FIG. 7 shows the cache memory 104 in this system.
And the segment management table. The cache memory 104 is used separately for a work area and a data area. The work area stores firmware information, a segment management table, and the like. However,
Since high-speed access is required for the segment management table, the segment management table may be recorded in a recording area other than the cache memory 104 (such as a working nonvolatile memory in the disk control device 103 or the CPU 106).

The data area stores data transmitted and received between the hard disk 102 and the host 101. In this method, continuous data of LBAs in the data area are grouped into segments, and each segment is managed by a segment management table. As shown in FIG. 7, the contents of the segment management table record the head LBA of the data in each segment, the head address of the data in the cache memory 104, and the data size of the segment. When new data is stored, the data is stored from the address indicated by the address pointer 113 in FIG. 1, and when the data storage is completed, the head address and the corresponding LBA at which the data storage was started, and the size of the stored data Is registered in the segment management table, and the value of the address pointer 113 is updated to the next address value at the end of the generated segment.

The data area is a ring buffer. When data is stored to the end of the data area, the data area returns to the head of the data area to store subsequent data.
At this time, if there is a segment to be overwritten by new data, the segment is discarded and the corresponding segment information in the segment management table is invalidated.

The case where a write command is detected in the interface 109 will be described below. An example of the interface 109 configured to detect a write command in the interface 109 is shown in FIG. The bus controller 301 is controlled by the sequencer 110 using a bus control signal 304, and controls transmission and reception of data between the bus 118 and the internal data bus 123. The write command detection circuit 302 detects a write command from the commands transferred from the host 101 via the bus 118, and issues a write interrupt signal 306 (part of the bus 120 in FIG. 1) to the sequencer 110. And FIF
By controlling the O303, the data following the write command is stored in the FIFO 303. Of course, when the write data from the host 101 can be directly transferred to the cache memory 104, the FIFO 303 may not be mounted. F
The I / F 303 serves as a buffer memory for temporarily storing write data. The data in the FIFO 303 is written to the cache memory 104 at an appropriate time.

The write command detection circuit 302 can be operated from the sequencer 110 by a detection circuit control signal 305 (part of the interface signal 119 in FIG. 1). If the function is unnecessary, it can be stopped. That is, it is possible to cope with a case where there is a need to make a disk storage device having the same function as the conventional one.

A case in which a write command is issued from the host 101 to the hard disk 102 while pre-reading is being performed in the hard disk 102 will be described with reference to the flowchart of FIG. When a write command is received from the host 101, the write command detection circuit 302 in the interface 109 detects the write command (90
1). Similarly, the write command detection circuit 302 issues a write interrupt to the sequencer 110, and
It controls the IFO 303 to store the data following the write command. If the data from the host 101 can be directly transferred to the cache memory 104,
3 is not mounted in the interface 109, this processing is not performed (902).

Sequencer 110 that has received a write interrupt
Controls the data multiplexer 115 to block data transfer from the disk formatter 117 to the cache memory 104. At this time, a prefetch stop interrupt is generated for the CPU 106 (903). CPU10
Numeral 6 designates a disk drive 1 via a servo system control circuit 107 for seeking a recording position for storing write data.
08 is instructed (911). At this time, sequencer 1
10 controls the disk formatter 117 to close the read gate in the disk drive 108 and interrupt prefetching (904).

The following steps in the flow of FIG. 9 will be described below with reference to FIGS. FIG. 8 shows the prefetch control signal, read gate, data transfer to the cache memory, the timing of buffer data, and the state in the cache memory 104 when prefetching is interrupted. The state at the time of prefetch interruption will be described using this. The upper part of the figure shows the writing state of the sector with the time axis taken in the horizontal direction. The lower left part shows the situation where the sector of the cache memory is written, and the lower right part is an enlarged view of the part where the writing was interrupted halfway. Here, pre-reading of the sector is stopped before reaching the sector boundary, but the auto-write start position of the write data is at the head of the sector, that is, at the sector boundary. The data of the sector pre-read halfway is overwritten by auto-write and discarded.

When the read gate itself can be operated only in units of one sector, the read gate performs a read operation up to the data of the last sector which has been pre-read. In the present embodiment, the data transfer to the cache memory 102 is interrupted by the data multiplexer 115 in order to quickly perform the prefetch interruption process. For this reason, since only part of the data of the last prefetch sector can be read, only partially read data is stored in the area where the data of the last prefetch sector should be read in the cache memory 104. Therefore, the write data transferred from the host should be written from the start address of the last prefetch sector on the cache memory 104. (In FIG. 8, the part of the fourth sector that has been read halfway is discarded, and the halfway advanced address pointer becomes invalid. The next address to be written should be the top address of the fourth sector. The sector boundary calculation circuit 111 is used to calculate the start address.

FIG. 5 shows an example of the configuration of the sector boundary calculation circuit 111. The sector size register 501 records the size of one sector. The lower bit mask circuit 502
The lower bit corresponding to the size of one sector is masked by a mask signal 503 from the sector size register 501. For example, when the size of one sector is 512 bytes, if 512 bytes are set in the sector size register 501, this register
Is instructed to mask the lower 9 bits used to indicate values from 0 to 511. (That is,
If the lower 9 bits are set to "0", the address becomes the sector boundary address. In this way, 1 is previously stored in the sector register 501.
The size of the sector is stored, and the internal data bus 12
The lower bit mask circuit 502 masks the address value transferred via the address 5 and resets the address value to a value at the sector boundary. (FIG. 9, step 905) Since the address pointer 113 indicates the final read-ahead position on the cache memory 104, the sector boundary is calculated from the value of the address pointer 113 by using the sector boundary calculation circuit 111. Then, the value of the address pointer 113 is set in the start address register 112. (FIG. 9,
Step 906) Next, the sequencer 110 uses the value of the start address register 112 as the start address and
03 to the cache memory 104. Of course, when the FIFO 303 is not used or is not mounted on the interface 109, the write data is directly transferred from the host 101 to the cache memory 104.

When the automatic writing is completed, the sequencer 11
0 increments and updates the address pointer 113 by the amount of transfer of the write data, and sets the auto write end interrupt to C
It is issued to the PU 106 (907 in FIG. 9) and enters a standby state (step 908 in FIG. 9). Here, the auto light means the disk control device 103 (H
DC: Hard Disk Controller) stores the write command in the cache memory. CPU10
6 is the start address register 112 and the address pointer 1
13, the segment management table is updated to generate a new segment (FIG. 9, step 91).
3). Then, the head address of the write data in the cache memory is set in the data write position register of the disk formatter 117 (FIG. 9, step 914).
When the seek for writing the write data is completed (FIG. 9, step 912), the CPU 106 activates the disk control device (FIG. 9, steps 915, 909). The sequencer 110 controls the disk formatter 117 to transfer the data in the cache memory 104 to the disk drive 108 (FIG. 9, step 910).

A case where a read command is detected in the interface 109 will be described below. FIG. 4 shows an example of the interface 109 configured to detect a read command in the interface 109. Of course, Fig. 3
It is also possible to incorporate the read command detection circuit 402 into the configuration at the same time. The bus controller 401 is controlled by the sequencer 110 by a bus control signal 403,
The transmission and reception of data between the bus 118 and the internal data bus 123 are controlled. The read command detection circuit 402
8, a read command is detected from commands transferred from the host 101 through the read interrupt signal 4.
05 to the sequencer 110. The read command detection circuit 402 can be operated from the sequencer 110 by the detection circuit control signal 404, and when the read command detection function is not required, such as when the read command detection processing is performed by firmware (the same processing as in the related art is performed). It can be stopped if desired). The read command detection circuit 402 can be operated from the sequencer 110 by the detection circuit control signal 404, and the read command detection function can be stopped as needed.

A case in which a read command is issued from the host 101 to the hard disk 102 while pre-reading is being performed in the hard disk 102 will be described with reference to the flowchart of FIG.

When a read command is received from the host 101, the read command detection circuit 40 in the interface 109
2 detects a read command and issues a read interrupt to the sequencer 110. The sequencer 110 that has received the read interrupt issues a command reception interrupt to the CPU 106 (1001). The CPU 106 searches the segment management table of FIG. 7 and starts hit determination as to whether or not the read data exists in the cache memory 104 (1015). The hit determination is performed by reading the head address of the LBA in the segment management table of FIG. 7 in the order of segments, and comparing the read address with the address in the segment management table to determine whether this is the address including the address specified by the read command. It is. The sequencer 110 controls the data multiplexer 115 to control the disk formatter 1
The transfer of data from 17 to the cache memory 104 is interrupted (1002). Then, the disk formatter 11
7 to close the read gate in the disk drive 108 and interrupt prefetching (1003).

The address pointer 113 indicates the final read-ahead position on the cache memory 104. By calculating the sector boundary from the value of the address pointer 113 using the sector boundary calculation circuit 111, the data of the last sector that has not been read due to the interruption of the prefetch is truncated, and the last address of the sector before the last sector is discarded. Ask for. This is the same as that described with reference to FIG. And
This value is set in the address pointer 113, and a segment update interrupt is issued to the CPU 106 (100
4) A standby state is entered (1005). The CPU 106 refers to the values of the start address register 112 and the address pointer 113, updates the segment management table, and generates a new segment (1017).

If the result of the hit determination by the CPU 106 is that the data in the cache memory 104 has hit,
The PU 106 starts the disk controller 103 (10
06). The sequencer 110 is provided in the cache memory 104
The more hit data is transferred to the host 101 (10
07). Then, the value of the address pointer 113 is set in the head address register 112 in order to restart the prefetch (1008), and the disk formatter 117 is activated to restart the prefetch (1009). Cache memory 1
If no data is found on the data on
Sends an instruction to the disk drive 108 via the servo control circuit 107 to seek to read the read data (1018), and when the seek is completed (101)
9), start the disk controller 103 (101)
0). The sequencer 110 sets the value of the address pointer 113 in the start address register 112 (101
1) Activate the disk formatter 117 to transfer data from the disk drive 108 to the cache memory 104 (1012). When the data requested by the host 101 is transferred from the disk drive 108 to the cache memory 104, the sequencer 110 transfers the read data from the cache memory 104 to the host 101 (1
013). Then, the prefetching is continued (1014).

Next, at step 1005 in FIG.
A case in which the cache memory hit search performed by 106 is performed by hardware in the disk control device 103 will be described with reference to FIGS.

FIG. 2 shows an example of the configuration of the second embodiment of the disk control device 103 in which a segment management circuit 201 is mounted so that the disk control device 103 makes a hit determination.

The segment management circuit 201 will be described. The segment management circuit 201 is a circuit that searches the contents of the segment management table and makes a hit determination. An example of this circuit configuration is shown in FIG. The maximum segment number register 601 holds the maximum segment number (m) handled by the segment management circuit 201. The segment start address register 602 holds the start address of the segment management table in the work area on the cache memory 104, and is used to read the segment table from the work area. Segment counter 603
Indicates the number of the segment for which hit determination is currently being performed, and designates one line at a time in the segment management table. The segment information register 604 is
The segment information for which hit determination is currently performed is held for one line. The LBA register 606 holds a command request LBA requested from the host. The sector register 607 holds the number of command request sectors of the LBA register 606. The hit determination circuit 605 compares the values of the segment information register 604 with the values of the LBA register 606 and the sector register 607, and performs a hit determination on the segment.

The operation of the segment management circuit 201 will be described. The segment management circuit 201 includes the sequencer 1
Controlled by 10. Before performing the hit determination, the maximum segment number register 601 stores the maximum segment number, the segment head address register 602 stores the start address of the segment management table, and the LBA register 606 stores the start address.
The command request LBA is set in the sector register 607 to the number of command request sectors. Then, the segment counter 603 is cleared. The sequencer 110 operates the segment head address register 602 and the segment counter 603 according to the register control signal 609,
The address of the segment for which hit determination is performed is output to the internal address bus 126, and information on the target segment is read into the segment information register. Next, the sequencer 110 operates the hit determination circuit 605 to make a hit determination. If a hit occurs, the hit determination circuit 605 outputs a hit signal 611 to the sequencer 110. In the case of a mistake, the same processing is performed by increasing the segment counter 603.
When the value of the segment counter 603 becomes equal to the maximum segment number register 601, the hit determination ends. In the second embodiment shown in FIGS. 2 and 6, the processing speed can be further improved.

In the case of the embodiment shown in FIG.
A case in which a read command is issued from the host 101 to the hard disk 102 while the pre-reading is being performed in 02 will be described with reference to the flowchart in FIG.
When a read command is received from the host 101, the read command detection circuit 402 in the interface 109 detects the read command and issues a read interrupt to the sequencer 110 (1101). The sequencer 110 that has received the read interrupt operates the hit determination circuit 201 to make a hit determination (1102). If hit, CPU 10
Issue a segment update interrupt for
The read data is transferred from the cache memory 104 to the host 101 (1104), and the prefetch is continued (110).
5). The CPU 106 refers to the value of the address pointer 113 and updates the information of the prefetch target segment in the segment management table (1117).

If the result of the hit determination is a miss, the sequencer 110 controls the data multiplexer 115 to send data from the disk formatter 117 to the cache memory 104.
Block data transfer to At this time, a prefetch stop interrupt is generated for the CPU 106 (110
6). The CPU 106 issues an instruction to the disk drive 108 via the servo control circuit 107 to seek to read the read data (1115). The sequencer 110 controls the data multiplexer 115 to block data transfer from the disk formatter 117 to the cache memory 104 (1106). Then, the disk formatter 117 is controlled, and the disk drive 10 is controlled.
8 and the pre-reading is interrupted (110).
7). Since the address pointer 113 indicates the last read-ahead position on the cache memory 104, the last address of the sector before the last sector is obtained by using the sector boundary calculation circuit 111. Then, the address pointer 11
3 and a segment update interrupt
(1108), and enters a standby state (110
9). The CPU 106 refers to the values of the start address register 112 and the address pointer 113, updates the segment management table, and generates a new segment (111).
7). When the seek started by the prefetch stop interrupt is completed (1116), the CPU 106 activates the disk controller 103 (1110). The sequencer 110
The value of the address pointer 113 is stored in the first address register 1
12 (1111), and the disk formatter 1
17 is started to transfer data from the disk drive 108 to the cache memory 104 (1112). When data requested by the host 101 is transferred from the disk drive 108 to the cache memory 104, the sequencer 1
10 transfers the read data from the cache memory 104 to the host 101 (1113) and continues the prefetch (1).
114).

In this embodiment, the case where the magnetic disk is used as the recording medium has been described. However, the same applies to the case where another recording medium such as a magneto-optical disk is used as the recording medium.

In the embodiment of the present invention described above, the write command is detected in the disk controller, and the read-ahead to the cache memory is interrupted by the control of the hardware.
Since write data from the host is written immediately after the pre-read data in the cache memory, the use efficiency of the cache memory can be improved.

Further, since the read command is detected in the disk controller and the pre-reading is interrupted, the time from the reception of the read command to the start of the seek can be shortened.

[0043]

According to the present invention, when the cache memory is prefetched when a command such as read or write is received from the host, the prefetch can be stopped earlier, and the performance of the disk storage device can be improved. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an information equipment system using a hard disk configured using the present invention.

FIG. 2 is a configuration diagram of another embodiment in which a segment management circuit is mounted on the disk control device of FIG. 1;

FIG. 3 is a configuration diagram when a write command detection circuit is mounted on the interface of FIG. 1;

FIG. 4 is a configuration diagram when a read command detection circuit is mounted on the interface of FIG. 1;

FIG. 5 is a configuration diagram of a sector boundary calculation circuit of FIG. 1;

FIG. 6 is a configuration diagram of a segment management circuit in FIG. 2;

FIG. 7 is an explanatory diagram of a cache memory using a variable segment system.

FIG. 8 is an explanatory diagram of the hard disk in FIG. 1 when prefetching is interrupted.

FIG. 9 is a flowchart when a write command is detected in a hard disk equipped with the interface of FIG. 3;

FIG. 10 is a flowchart when a read command is detected in a hard disk equipped with the interface of FIG. 4;

11 is a flowchart when a read command is detected in a hard disk equipped with the interface of FIG. 4 and the segment management circuit of FIG. 6;

[Explanation of symbols]

101: Host, 102: Hard Disk, 103: Disk Controller, 104: Cache Memory, 105:
ROM, 106 CPU, 107 servo control circuit,
108: disk drive, 109: interface,
110: sequencer, 111: sector boundary calculation circuit, 1
12 ... head address register, 113 ... address pointer, 114 ... address multiplexer, 115 ... data multiplexer, 116 ... ECC, 117 ... disk formatter, 118 ... bus, 119 ... interface control signal, 120 ... command detection interrupt signal, 121 ...
CPU interrupt signal, 122 ... CPU address bus, 12
3 CPU data bus, 124 CPU control signal, 12
5 internal data bus, 126 internal address bus, 12
7: formatter address bus, 128: formatter data bus, 129: module control signal, 130: E
CC data bus, 131 ... servo control signal bus, 132
... Signal bus, 201 ... Segment management circuit, 301 ... Bus controller, 302 ... Write command detection circuit, 3
03: FIFO, 304: bus control signal, 305: detection circuit control signal, 306: write interrupt signal, 307: F
FIFO control signal, 308... FIFO control signal 2, 309
... response signal, 401 ... bus controller, 402 ... read command detection circuit, 403 ... bus control signal, 404 ...
Detection circuit control signal, 405 ... read interrupt signal, 50
1: Sector size register, 502: Lower bit mask circuit, 503: Mask signal, 504: Sector size register control signal, 505: Mask circuit control signal, 507 ...
Calculation result register control signal, 601: maximum segment number register, 602: segment head address register,
603: segment counter, 604: segment information register, 605: hit determination circuit, 606: LBA register, 607: sector register, 608: register control signal, 609: counter control signal, 610: hit determination circuit control signal, 611: hit signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukie Hiratsuka 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside the Hitachi, Ltd.System Development Laboratory (72) Inventor Manabu Nishikawa 2880 Kozu, Kozu, Odawara City, Kanagawa Prefecture Hitachi, Ltd. 5B005 JJ11 MM11 NN22 NN71 5B065 BA01 CA14 CA15 CC08 CH01 CH05

Claims (5)

[Claims] A command detection device for detecting a specific command sent from a host and generating an interrupt signal in a disk storage device having a cache memory and prefetching data in the cache memory;
A disk storage device, comprising: a sequencer for interrupting transfer of data to the cache memory in response to the interrupt signal and interrupting data read for pre-reading the data. 2. The disk storage device includes a data gate for managing output of write data to the cache memory, a disk drive for storing data, and a disk formatter for controlling writing and reading of the disk drive. 2. The disk storage according to claim 1, wherein said sequencer receives said interrupt signal, interrupts data to said cache memory at said data gate, and interrupts a read-ahead read operation by said disk formatter. apparatus. 3. A disk storage device having a cache memory and prefetching data in the cache memory, a command detection device for detecting a specific command sent from a host and generating an interrupt signal, and A disk drive for storing, a processing device that executes firmware, and a sequencer that receives the interrupt signal and generates a prefetch stop interrupt to the processing device, wherein the processing device responds to the prefetch stop interrupt. And a disk drive for causing the disk drive to start a seek operation. 4. A command detecting device for detecting a write command sent from a host and generating a write interrupt signal in a disk storage device having a cache memory and prefetching data in the cache memory, A sequencer for stopping the prefetch in response to the interrupt signal, and a sector boundary calculation circuit for correcting the address pointer of the cache memory to a value of a sector boundary, and the write data sent from the host is processed by the sector boundary calculation circuit. A disk storage device wherein data is written to the cache memory from a determined sector boundary. 5. A command detecting device for detecting a read command sent from a host and generating a read interrupt signal in a disk storage device having a cache memory and prefetching data in the cache memory, A sequencer for interrupting data transfer to the cache memory upon receiving an interrupt signal and interrupting data read for prefetching the data; and determining whether data requested by a host is stored in the cache memory. And a determination circuit that performs
A disk storage device wherein the pre-reading is resumed if the data is stored, and if the data is not stored, a seek operation for reading data requested by the host is performed to a disk drive storing the data.