JP2001101030A - Program debugging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a software break point in a ROM region. SOLUTION: This system is provided with a reloadable memory, a maintenance means for arbitrarily reloading the memory, and a lock means for preventing the operation that the memory is automatically updated. In this case, an instruction for changing program control is written in the memory equivalent to the ROM region by using a maintenance means, and the locking operation is executed so that the memory can be prevented from being automatically reloaded by the maintenance means. Thus, a software break point can be set in the ROM region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a program debugging system that does not use an in-circuit emulator (ICE) or the like.

[0002]

2. Description of the Related Art As one of conventional program debugging methods, there is a software breakpoint debugging method. In this software breakpoint debugging method, program instructions for setting switch points are
A means for temporarily replacing an instruction for changing the program control, for example, an instruction for generating an interrupt (trap instruction) has been employed.

According to this method, the area for setting a breakpoint is limited to a program developed in the RAM area, so that it was not physically possible to set a software breakpoint in the ROM area.

For example, according to the contents described in Japanese Patent Application Laid-Open No. 9-288598, a program is stored in a ROM as a target, and a manager refers to a switch table from a preset switch point of a process of the program. The program process is transferred to the debugger process, the program on the ROM is debugged, and the program to be debugged is switched by the table manager that manages the switch table, and the program is referred to by the corresponding switch table. Process is transferred to the debugger process,
It has been proposed that a plurality of different programs on the ROM can be debugged.

[0005]

However, according to this method, each time the program is executed, a large amount of time is required for the operation of comparing the reference tables. Furthermore, since a switch point to be a predetermined break point is embedded in a program instruction in advance, it is difficult to set a switch point at an arbitrary position after the ROM is created. In addition, since a required number of switch points is embedded in a program instruction, R
The OM capacity has increased significantly, resulting in an increase in the total program size, which has limited the freedom of design. SUMMARY OF THE INVENTION It is an object of the present invention to solve these problems of the prior art and to provide means for setting a software breakpoint in a ROM area.

[0006]

In order to solve the above-mentioned problems, the present invention provides a rewritable memory, a maintenance means for arbitrarily rewriting the memory, and an operation for automatically updating the memory. In a system having a lock unit, an instruction for changing program control is written into the memory corresponding to the ROM area using the maintenance unit, and the memory is automatically written using the maintenance unit. Software breakpoints can be set in the ROM area by locking them so that they do not change.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. Figure 2 shows an on-chip memory (OCM)
It is a block diagram which shows the structure at the time of using. The same parts are denoted by the same reference numerals.

In FIG. 1, reference numeral 1 denotes a read-only memory (hereinafter referred to as a ROM) in which a program to be debugged is stored. The program includes an instruction to be a point for starting a debugger.
Reference numeral 2 denotes a format in which program instructions in the ROM 1 are stored, and shows that programs corresponding to addresses are stored in the order of addresses.

Reference numeral 3 denotes an instruction cache memory used as an instruction temporary storage high-speed memory used in the present embodiment.
Temporarily store the most recent command of the program in OM1,
Used for high-speed instruction read operation. The central processing unit (CPU) 4 reads out and executes the program stored in the ROM 1 based on the address. The executed instruction is also temporarily stored in the temporary high-speed memory 3 at the same time. If the instruction whose address matches next time is in the temporary storage high-speed memory 3, the operation of reading the instruction from the ROM 1 is omitted, and by reading the instruction from the temporary storage high-speed memory 3, high-speed program execution is realized. . Reference numeral 5 denotes maintenance means for arbitrarily rewriting the temporary storage high-speed memory 3. As the maintenance means 5, a cache maintenance register which can be easily operated is used.

In the present invention, when it becomes necessary to debug a target program in the ROM 1, the maintenance means 5 of the temporary storage high-speed memory 3 is used to control the program corresponding to the address corresponding to the temporary storage high-speed memory 3. Is written into the temporary storage high-speed memory 3 and the maintenance means 5 is locked so that the temporary storage high-speed memory 3 is not automatically rewritten. When the CPU 4 executes an operation of reading a program to be debugged in the ROM 1, the CPU 4 checks the address of the temporary storage high-speed memory 3 and reads an instruction written in advance to change the program control, and debugs the control. By transferring control to a debugger program that supports the above, it is possible to operate as if a software breakpoint was set in a program in the ROM1 area. Reference numeral 6 denotes an instruction bus for the CPU 4 to read out a program instruction, and reference numeral 7 denotes an instruction cache internal table indicating a data format stored in the temporary high-speed memory 3. A program instruction corresponding to a program address is stored in the table 7 as data, and a row (line) corresponding to each address includes a flag V indicating whether the address line is valid and a corresponding address line. There is a flag L for setting whether or not to prohibit the update of the.

FIG. 2 shows the temporary storage high-speed memory 3.
FIG. 13 is a block diagram showing an example in which an on-chip memory is used in place of FIG. Reference numeral 8 denotes an on-chip memory OCM used as an additional instruction temporary storage high-speed memory.
Are usually stored in advance in the ROM 1 for a high-speed operation requesting program instruction, and are used for high-speed instruction reading operation. The CPU 4 reads out and executes the program stored in the ROM 1 based on the address. At this time, the CPU 4 searches the on-chip memory 8 and, if a corresponding program instruction exists, reads the instruction from the on-chip memory 8. By reading, the program is executed at high speed.

In this case, when it becomes necessary to debug a target program in the ROM 1, the program control corresponding to the address corresponding to the on-chip memory 8 is changed by using the data-side on-chip memory bus 9. Is written in the on-chip memory 8. CPU4
Executes an operation of reading a program to be debugged in the ROM 1, checks an address of the on-chip memory 8, and issues an instruction for changing program control written in advance to the instruction side on-chip memory bus 10. , And control is transferred to a debugger program that supports debugging, thereby making it possible to operate as if a software breakpoint was set in the program in the ROM1 area. 1
1 is an instruction bus for the CPU 4 to read out program instructions.

[0014]

As described above, according to the configuration and method of the present invention, the instruction is read from a predetermined breakpoint of the program on the ROM by the transition control means by targeting the program on the ROM. Instead, by reading an instruction for changing the preset predetermined program control from the temporary storage high-speed memory, the control of the program is transferred to the debugger, so that the program on the ROM can be debugged. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration when an on-chip memory (OCM) is used;

[Explanation of symbols]

Reference Signs List 1 ROM 2 Program instruction storage format 3 Temporary storage high-speed memory (instruction cache) 4 CPU 5 Maintenance means 6 Instruction bus 7 Temporary storage high-speed memory instruction storage format 8 On-chip memory 9 Data side on-chip memory bus 10 Instruction side on-chip memory bus 11 Instruction bus

Claims (3)

[Claims] In a system having a rewritable memory, a maintenance means for arbitrarily rewriting the memory, and a lock means for preventing an operation of automatically updating the memory, the memory in the memory corresponding to a ROM area To
A software breakpoint is set in the ROM area by writing an instruction for changing the program control using the maintenance unit and further locking the memory using the maintenance unit so that the memory is not automatically rewritten. A program debugging method characterized by being made possible. 2. The program debugging method according to claim 1, wherein a software breakpoint can be set in a program on the ROM by using a temporary storage high-speed memory as the memory. 3. The program debugging method according to claim 1, wherein a software breakpoint can be set in a program on the ROM by using an on-chip memory from which a program instruction can be read.