JP2001095007A - Killer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a killer circuit characterized in that failures are few when presence/absence of a color is judged, even for a signal of small chroma level in a chroma signal of a PAL system. SOLUTION: This circuit is provided with a first multiplying circuit 101, a second multiplying circuit 102, a first low-pass filter circuit 103, a second low-pass filter circuit 104, a first BLK circuit 105, a second BLK circuit 106, an APC(Auto Phase Control) circuit 107, a 1H delay circuit 108, a subtraction circuit 109, a lone inversion circuit 110, a cut-over circuit 111 and the killer circuit 112.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a killer circuit which is less likely to fail when judging the presence or absence of a color even with a small chroma level signal in a PAL system chroma signal.

2. Description of the Related Art In recent years, with the spread of large-screen television receivers, killer circuits have been regarded as important circuits for determining the quality of televisions. Hereinafter, an example of the above-described conventional killer circuit will be described with reference to the drawings. FIG.
FIG. 1 shows a block diagram of a killer circuit proposed in Japanese Patent Application Laid-Open No. 58-21358. In the block diagram of FIG. 2, 61 is a chroma signal, 62 is a variable gain amplifier circuit, 63 is a burst chroma separation circuit, 64 is a color control circuit, 65 is a volume, and 66 is 1
H delay line, 67 is a capacitor, 68 is a time adjustment volume, 69 is a capacitor, 71 is an ACC detection circuit, 72 is a gate pulse shaping circuit, 74 is a switch circuit, 75 is a pal matrix circuit, and 76 is a BY demodulator. , 77 is a RY demodulator, 78 is a GY demodulator, 79 is a system switch circuit, 80 is a waveform shaping circuit, 81 is a hue control circuit, 82 is a volume circuit, 83 is a killer detection circuit, and 84 is APC detection. Circuit, 85 is an identity killer circuit, 86 is a flip-flop circuit, 87 is a voltage controlled oscillator, and 88 is a phase synthesis circuit. The operation of the color signal processing device configured as described above will be briefly described below. First, based on the signal output from the APC detection circuit 84, various subcarriers for demodulation are output by the phase synthesis circuit 88. The conventional invention uses B-
The subcarrier for demodulating Y and the subcarrier input to the killer detection circuit 83 at the time of PAL are used as the same signal, thereby reducing the circuit scale.

However, the above configuration has the following problems. Since the conventional invention is a color demodulation circuit based on analog signal processing,
Although a circuit such as the phase synthesis circuit 88 could be easily configured,
When the demand for a color demodulation circuit based on digital signal processing has increased in recent years, it is irrational to configure a circuit such as the phase synthesis circuit 88 digitally in terms of the circuit scale.

In order to solve the above-mentioned problems, a killer circuit according to the present invention comprises a first multiplication circuit for multiplying an input chroma signal by a COS wave signal from an APC circuit to be described later, and an input chroma signal. Signal and S from the APC circuit described later
A second multiplying circuit for multiplying the signal by the IN-wave signal; a first low-pass filter circuit for reducing a high-frequency component of the output signal from the first multiplying circuit; and a high-level output signal from the second multiplying circuit. A second low-pass filter circuit for reducing a frequency component, a first BLK circuit for performing a blanking process for setting an output signal level of the first low-pass filter circuit to “0”, and the second low-pass filter circuit And a second BLK circuit for performing a blanking process for setting the output signal level of the second low pass filter circuit to "0", an output signal from the second low-pass filter circuit, and a subcarrier frequency of an input chroma signal; APC (Aut) that operates to match the frequency of the SIN wave and the COS wave
o Phase Control) circuit and the second
A 1H delay circuit for delaying the output signal from the low-pass filter circuit for one horizontal period, a subtraction circuit for subtracting the output signal from the 1H delay circuit and the second low-pass filter circuit, and an output from the subtraction circuit. A line inversion circuit that inverts the polarity of the signal if the line identification signal is H, and outputs the signal with the same polarity if the line identification signal is L; an output signal from the line inversion circuit; A switching circuit for switching an output signal from the low-pass filter circuit by a control signal input from the outside; and a killer circuit for determining whether or not there is a chroma signal from the output signal from the switching circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a killer circuit characterized by the effect that it is possible to determine the presence or absence of a color in a PAL system chroma signal without failure even with a signal having a small chroma level. There is a circuit that switches the demodulated signal according to the input chroma signal method and inputs the signal to the killer circuit, thereby improving the accuracy of the output signal from the killer circuit. According to a second aspect of the present invention, a first multiplying circuit for multiplying an input chroma signal by a COS wave signal from an APC circuit described later, and a SIN wave signal from an APC circuit described later by an input chroma signal. A second multiplication circuit for multiplying, a first low-pass filter circuit for reducing a high-frequency component of an output signal from the first multiplication circuit, and a second low-frequency filter circuit for reducing a high-frequency component of an output signal from the second multiplication circuit. 2 low-pass filter circuits, a first BLK circuit that performs a blanking process to make the output signal level of the first low-pass filter circuit “0”, and an output signal level of the second low-pass filter circuit. A second BLK circuit for performing a blanking process to make it “0”, and an output signal from the second low-pass filter circuit as an input, and a subcarrier of an input chroma signal And frequency output to SIN wave, APC which operates to match the frequency of the COS wave (Auto Phase Contra
ol) circuit, a 1H delay circuit for delaying the output signal from the second low-pass filter circuit for one horizontal period, and the second
And a subtraction circuit for subtracting the output signal of the low-pass filter circuit, and inverting the polarity of the output signal from the subtraction circuit if the line ident signal is H and outputting the same if the line ident signal is L. A line inverting circuit for outputting the output signal from the line inverting circuit, a switching circuit for switching an output signal from the first low-pass filter circuit by a control signal input from the outside, and an output signal from the switching circuit. And a killer circuit for judging the presence or absence of a chroma signal from a PAL system. By switching the signal according to the input chroma signal method and inputting it to the killer circuit, the accuracy of the output signal from the killer circuit It has a circuit that improves. Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a killer circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes an input chroma signal 113 and an AP to be described later.
A multiplication circuit for multiplying the COS wave signal from the C circuit 107; a multiplication circuit 102 for multiplying the input chroma signal 113 by a SIN wave signal from the APC circuit 107, which will be described later;
03 is a low-pass filter circuit that drops high-frequency components of the output signal from the multiplication circuit 101, 104 is a low-pass filter circuit that drops high-frequency components of the output signal from the multiplication circuit 102, and 105 is the output signal level of the low-pass filter circuit 103. B that performs a blanking process to make it “0”
LK circuit. 106 is a low-pass filter circuit 10
4 is a BLK circuit that performs a blanking process to make the output signal level of “4” “0”, 107 receives the output signal from the low-pass filter circuit 104 as an input, and
13 subcarrier frequencies and the output SIN wave,
APC that operates to match the frequency of the COS wave
(Auto Phase Control) circuit, 1
08 is a 1H delay circuit for delaying the output signal from the low-pass filter circuit 104 by one horizontal period, 109
Is a subtraction circuit for subtracting the output signal from the low-pass filter circuit 104 from the output signal from the 1H delay circuit 108. Reference numeral 110 denotes a line identification signal which is necessary for demodulating a PAL type chroma signal, and which can specify a line identification, inverts the polarity of the output signal from the subtraction circuit if the line identification signal is H, and outputs the inverted signal. If the line identification signal is L, the line inversion circuit outputs the signal with the same polarity, and 111 switches between the output signal from the line inversion circuit 110 and the output signal from the low-pass filter circuit 103 by a control signal input from the outside. A switching circuit 112 is a killer circuit that determines whether or not there is a chroma signal from the output signal from the switching circuit 111. The operation of the killer circuit configured as described above will be described below with reference to FIGS. First, FIG. 3 is an operation explanatory diagram for explaining the operation of the killer circuit according to the present embodiment. The SIN and COS waves output from the APC circuit 107 have the same frequency as the input chroma signal 113,
The wave is input to the multiplication circuit 102, and the COS wave is multiplied by the multiplication circuit 1
03 is input. Therefore, the signals output from the low-pass filter circuits 103 and 104 become a BY signal 115 and an RY signal 114, respectively. Killer circuit 112
Detects the level of the signal corresponding to the burst period among the input signals, and when the input signal is smaller than a certain level, determines that there is no burst, that is, a black and white signal, and sets the output level of the BLK circuits 105 and 106 to " 0 ". If the level of the input signal is higher than a certain level, it is determined that the input signal is a color signal, and the outputs of the BLK circuits 105 and 106 operate to output the input signal as it is. Here, when the input chroma signal 113 is a signal of the NTSC system, the phase of the burst signal is a vector indicated by a solid line in FIG. 3A, and the signal input to the killer circuit 112 is on the BY axis. It turns out that it is necessary to input a signal. The reason is R
If the signal is on the -Y axis, the signal level during the burst period becomes substantially "0", so that killer detection cannot be performed. Therefore, for the signal of the NTSC system, the switching circuit 111 needs to be on the low-pass filter circuit 103 side. On the other hand, P
Since the phase of the burst signal of the AL system is a vector indicated by a dotted line in FIG.
What is necessary is just to input the signal on an axis to a killer circuit. Here, an object of the present invention is to further improve the killer detection performance by the 1H delay circuit 108, the subtraction circuit 109, and the line inversion circuit 110. This will be described below. FIG.
(B) Reference numerals 1 and 3 denote burst phases of the PAL system in which the phase is changed every 1H. Reference numeral 2 in FIG. 3B denotes a signal obtained by projecting 1 on the R-Y axis, and reference numeral 4 denotes R-Y. This is a signal projected on the Y axis. A signal obtained by delaying the signal on the RY axis by 1H by the 1H delay circuit 108 and subtracting the signal before the delay from the signal is shown in FIG. The polarity of this signal is inverted every 1H. However, the line identification signal 117 is a signal that can specify the line to be inverted, and the line identification signal 117 can be used to adjust the polarity of all the lines to the positive polarity in the line inversion circuit 110. When a signal output from the line inversion circuit 117 is input to the killer circuit 112, killer detection can be performed. Now, here, Figure 3
Paying attention to the signal level of 5 in (b), it can be seen that the original amplitude is larger than that of 1 in FIG. 3 (b). Also, even if a noisy signal is input, 1
Since the subtraction is performed before and after H, noise is removed. As a result, the signal level in the burst period input to the killer circuit 112 is increased and the noise is also removed, so that the killer detection accuracy is improved. Become. Therefore, when a PAL-type chroma signal is input, the switching circuit 111 is set to the line inverting circuit side, so that the accuracy of killer detection performed by the killer circuit 112 can be improved. Also, unlike the conventional example, there is no need to combine the subcarrier signals in various ways, and the circuit scale can be reduced when performing digital signal processing.

As described above, according to the present embodiment, the 1H delay circuit 108, the subtraction circuit 109, and the line inversion circuit 1
By providing 10, the signal level during the burst period input to the killer circuit 112 increases and noise is also removed, so that the killer detection accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a killer circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional killer circuit.

FIG. 3 is a diagram illustrating the operation of the killer circuit according to the first embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 1st multiplication circuit 102 2nd multiplication circuit 103 1st low-pass filter circuit 104 2nd low-pass filter circuit 105 1st BLK circuit 106 2nd BLK circuit 107 APC (Auto Phase Contra)
ol) circuit 108 1H delay circuit 109 subtraction circuit 110 line inversion circuit 111 switching circuit 112 killer circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisao Morita 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor Hitoshi Ando 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term within Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A killer circuit characterized in that there is little failure when judging the presence or absence of a color even in a signal of a small chroma level in a chroma signal of the PAL system. 2. An input chroma signal and an APC (Au) described later.
COS from to Phase Control circuit
A first multiplication circuit for multiplying an input chroma signal and a SIN wave signal from an APC circuit, which will be described later, and a high frequency band of an output signal from the first multiplication circuit. A first low-pass filter circuit for dropping components;
A second low-pass filter circuit for reducing high-frequency components of the output signal from the second multiplication circuit; and a first low-pass filter circuit for performing a blanking process to set the output signal level of the first low-pass filter circuit to “0”. BLK circuit and the second
A second BLK circuit that performs a blanking process to set the output signal level of the low-pass filter circuit to "0", and an output signal from the second low-pass filter circuit as an input, and a subcarrier of an input chroma signal. An APC (Auto Phase Co.) that operates so that the frequency matches the frequency of the output SIN wave or COS wave.
1H) for delaying the output signal from the second low-pass filter circuit by one horizontal period.
A delay circuit; a subtraction circuit for subtracting an output signal of the second low-pass filter circuit from an output signal from the 1H delay circuit; and a line eye required for demodulating a PAL-type chroma signal and capable of specifying a line identity. A line inverting circuit which receives a dent signal as input, inverts the polarity of the output signal from the subtraction circuit if the line ident signal is H, and outputs the inverted signal if the line ident signal is L; A switching circuit for switching an output signal from the line inverting circuit and an output signal from the first low-pass filter circuit by a control signal input from the outside; and a signal in a burst period among output signals from the switching circuit. A killer circuit that determines the presence or absence of a chroma signal based on the level level is provided. In determining the presence or absence of color in Sai chroma level signal, the killer circuit, characterized in effect collapse is small. 3. The input signal to the killer circuit selects an output signal from the line inverting circuit in PAL and an output signal from the first low-pass filter circuit in NTSC. Killer circuit.