JP2001094561A - Decelling device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce transmission delay and to suppress a decrease in data throughput of a transmission line as to a decelling device which performs a decelling process according to cell assembly information at the time of a celling process. SOLUTION: A format conversion part 80 maps the cell assembly information (frame data effective byte length, error detection information, etc.), to redundant bits before the position at the time of the celling process. Further, a decelling part 73 discards unnecessary bits except data included in ATM cell data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decellularization apparatus, and more particularly to a decellularization apparatus for performing decellularization based on cell assembly information at the time of cellification. In recent years, ATM
(Asynchronous transfer mode) is capable of transferring all kinds of information at high speed, and thus has been used in many fields including data communication. In the cell-based transfer mode of ATM, it is important how to efficiently convert transmission information into cells and de-receive cells.

[0002]

2. Description of the Related Art FIG. 8 shows a CPCS (Common Part Convergence Sublayer) _PDU (PTM) of an ATM adaptation layer type 5 (AAL5).
3 shows the format of a (rotocolData Unit) frame 10.

The CPCS_PDU frame 10 has a CPCS_PDU payload field 11, a pad of 0 to 47 bytes (PAD: PADdi).
ng) field 12, and an 8-byte CPCS_PDU trailer (tr
(ailer) field 13. PAD field 1
The number 2 is for increasing the length of the frame 10 to an integral multiple of 48 bytes, and for enabling the SAR (Segmentation And Reassemble) process to divide the ATM cell without padding. is there.

[0004] The trailer field 13 is a 1-byte CPCS.
_UU (User-to-User indication) field 14, 1-byte CPI (Common Part Indicator) field 15, 2-byte LI (Length Indicator) field 16, and 4-byte
It consists of CRC-32 field 17. LI field 16
(Hereinafter, the value of the LI field 16 is referred to as the LI value) is CPCS_P
It indicates the length of the DU payload field 11, and the CRC-32 field 17 is for detecting a bit error of the CPCS_PDU frame 10.

[0005] The CPCS_PDU frame 10 is decomposed every 48 bytes and is divided into a head cell 20a, an intermediate cell 20b, an intermediate cell 20c, ...,
It is mapped to the payload part of the last cell 20n. Therefore, the trailer field 13 of 8 bytes is stored in the last cell 20n.
Will be mapped to the last 8 bytes.

A PTI (Payload) included in the header of an ATM cell
Type Identifier) field = "1xx (x: don't car
e) ”to identify the last cell.
An example is shown in which a CPCS_PDU frame 10 having a payload field (frame data) 11 of 89 bytes is converted into an ATM cell. This example shows a case where the most PADs are inserted.

[0007] The first 48 bytes of the CPCS_PDU frame 10 are:
Mapped to the payload part of the first cell 20a, the remaining 4
One byte is mapped to the intermediate cell 20b. Intermediate cell 20
Since only 48-41 = 7 bytes remain at the end of the payload portion of b, the 8-byte trailer field 13 to be mapped at the end of the payload portion cannot be mapped.

Therefore, the last cell 20c is added, and the trailer field 13 is mapped to the last of the last cell 20c, so that the last 7 bytes of the intermediate cell 20b and the front of the last cell 20c are mapped.
PAD field 12 is inserted in 40 bytes. The decelerating device includes a first cell 20a, an intermediate cell 20b, and a last cell 20c.
Are sequentially received, and when the last byte of the last cell 20c is received, the length (effective byte length) information of the CPCS_PDU payload field 11 and the CRC-32 operation value are obtained.

[0009] Accordingly, the decelerating device transmits the CPCS_PDU payload field with the last cell 20c in the received data (excluding the ATM header portion) and the byte preceding the preceding byte by 55 bytes corresponding to the 7-byte PAD. Judge as the last byte of 11. Assuming such a worst case, the decelerator prepares a buffer of 55 bytes or more,
The received data is buffered, and upon receiving the last byte of the last cell, the data up to the byte length indicated by the effective byte length is subjected to CRC-32 inspection and then reproduced in a frame.

The following is a more specific example of the operation of the decellularizing device. FIG. 10 shows a configuration example of an ATM switch 40 that performs a decellularization process. This ATM switch 40
ATM interface adapter 50 connected by ATM line to
An ATM switch 60 and an STM interface adapter 70 for transmitting the frame 10 are cascaded.

The opposite device 30 sends out the ATM cell 20 through the 155.52 Mbps ATM interface. The ATM cell 20 is received by the adapter 50 and passed to the ATM switch 60. The ATM switch 60 converts the received ATM cell 20 into a predetermined STM interface adapter.
Switch to 70. The adapter 70 has a built-in decelerating device, converts the format of the ATM cell 20 into a frame 10 (decelerates it), and then sends the frame 10 to the 1.544 Mbps STM interface transmission line.

Table 1 summarizes the functions of each block in FIG.

[0013]

[Table 1]

FIG. 11 shows an example of the configuration of the STM interface adapter 70. This adapter 70 is used for ATM switch 6
The configuration is such that an ATM switch interface unit 71, a clock replacement buffer 72, a decellularization unit 73, and an STM interface control unit 74 connected to the STM interface are connected in cascade.

The ATM switch interface unit 71 receives an ATM cell with a clock of 155.52 Mbps synchronized with the ATM switch 60 and supplies the clock to the clock transfer buffer 72. The clock transfer buffer 72 uses an ATM with a clock of 155.52 Mbps.
The cell is received, an ATM cell is provided to the decellularization unit 73 in synchronization with a clock of 1.544 Mbps, and a buffer function for absorbing a clock phase between the interface unit 71 and the decellularization unit 73 is performed.

The decellularizing section 73 reproduces frame data from the ATM cell 20 and supplies the frame data to the STM interface control section 74. The control unit 74 operates in synchronization with the 1.544 Mbps clock of the transmission line, converts the frame 10 into the format of the STM interface, and sends it out. Thus, in the STM interface adapter 70, the clock transfer buffer 72
The transmission rates on the input and output sides are 15
5.52 Mbps and 1.544 Mbps, and the output side is much slower than the input side.

When an ATM cell including the 47-byte PAD field 12 shown in FIG. 9 arrives at the STM interface adapter 70, after reading 89 bytes of valid data to be framed, the valid byte length 16 and Reading must continue to the last byte of the last cell to read CRC-32 bit 17.

Therefore, as shown in FIG.
The transmission of the frame 10 is waited for about 60 μs × 8 bits / 1.544 Mbps = about 310 μs for reading out a total of 60 bytes of the last 7 bytes of 20b and the last cell 53 bytes at 1.544 Mbps. Table 2 summarizes the function of each block in FIG.

[0019]

[Table 2]

[0020]

As described above, in the conventional decelerating apparatus, the frame data to be reproduced (FIG. 8)
Even if the reception of the CPCS_PDU payload field 11) is completed, if the reception of the last byte of the last cell is not completed, it will not be possible to determine the delimitation of the frame and the normality of the data, resulting in a delay in the completion of frame reproduction. Become. As a result, the transmission delay increases.

Data not included in the frame data (PAD field 12 and trailer field 1 in FIG. 8)
Since 3) must be received, reception of the next ATM cell cannot be started. For this reason,
The transmission path is filled with an idle pattern, which causes a decrease in throughput.

Further, until the last byte of the last cell is received, it is necessary to accumulate all the received ATM cell data, so a data buffer of at least 55 bytes is required. Accordingly, it is an object of the present invention to reduce the transmission delay and suppress the reduction in data throughput of a transmission path in a decellularization device that performs decellulation based on cell assembly information included in a cell.

[0023]

In order to solve the above-mentioned problems, a decelerating apparatus according to the present invention maps cell assembly information to redundant bits ahead of a position at the time of cellification. It is characterized by having means for decelerating.

FIG. 1 shows the principle of a decelerating apparatus according to the present invention, and shows the conventional STM interface adapter 70 shown in FIG.
The example applied to FIG. The decelerating device of the present invention,
The difference from the conventional decelerator is that a format converter 80 is inserted between the ATM switch interface unit 71 and the clock switching buffer 72.

The format conversion section 80 maps the cell assembly information included in the cell at the time of cell conversion into redundant bits existing before the bit including this information. According to this cell assembly information, it is possible to end the decellularization at an earlier point in time than in the case of performing the decellularization using the cell assembling information itself at the time of the cellization, and it is possible to reduce the transmission delay.

Further, in the present invention according to claim 2,
The cell assembly information can be used as effective byte length information. In other words, the effective byte length information of the frame to be assembled by deceleration can be known at an earlier point in time, and the end point of the deceleration can be earlier. This makes it possible to reduce transmission delay.

Further, in the present invention according to claim 3,
The cell assembly information can be used as error detection information. That is, it is possible to know at an earlier time whether or not an error has occurred in the received frame data, and it is possible to correct or discard the frame data,
Transmission delay can be reduced.

In the present invention according to claim 4,
The redundant bits may be bits included in a cell including the cell assembly information. That is, it is possible to map the cell assembly information to redundant bits ahead of the cell assembly information among the bits of the cell including the cell assembly information.

In the present invention according to claim 5,
The redundant bit may be a redundant bit included in a cell preceding the cell including the cell assembly information. That is, the cell assembling information can be mapped to redundant bits of a cell ahead of the cell including the cell assembling information.

In the present invention according to claim 6,
The redundant bits can be bits in a cell header. That is, it is possible to map the cell assembly information in the cell header ahead.

In the present invention according to claim 7,
Bits excluding data behind the position where the cell assembly information is mapped can be discarded at high speed. That is, when there is an unnecessary bit other than the data behind the position of the cell assembly information moved forward, this can be discarded at a high speed.

As a result, the time for processing unnecessary bits is shortened, and a decrease in the throughput of the transmission path can be suppressed. Further, in the present invention according to claim 8, it is assumed that the cell is obtained by converting an AAL5 CPCS_PDU frame into a cell,
The cell assembly information is transferred to the effective byte length information of the frame and CR.
The redundant bits can be used as the header part of the last cell as the C-32 operation result information.

That is, the decelerator converts the CPCS_PDU of AAL5
The cell of the frame is received, and the effective byte length information of the frame and the operation result information of CRC-32 at the end of the last cell are mapped to redundant bits in the header part. This allows
The frame assembling end time can be shortened, and the transmission delay due to the decelling can be reduced.

[0034]

FIG. 2 shows an embodiment of a decelerating apparatus according to the present invention. This decelerating device is an ATM
ATM inputting ATM cell 20 from switch 60 (see FIG. 10)
UTOPIA (Universal Test and Op.) Including the switch interface unit 71 and the clock switch buffer 72 shown in FIG.
The SAR unit 7 performs deceleration processing corresponding to the deceleration unit 73 shown in FIG.
3, and HDLC (High level Data Link Control procedu
re) section 75, T1 framer section 76, LIU (Line Interface Unit)
The unit 77 and the STM interface control unit 74 (see FIG. 1) composed of the T1 interface unit 78 are cascaded in this order.

Further, a CPU interface unit 79 is connected to the SAR unit 73 and the HDLC unit 75 via the SAR bus 112, and is connected to the T1 framer unit 76.
The configuration is such that they are connected by the FR bus 113. Table 3 shows the function of each block.

[0036]

[Table 3]

FIG. 3 shows a specific embodiment of the UTOPIA section 72 shown in FIG. The UTOPIA section 72 supplies a cell read signal 101 to an ATM switch interface section 71 (see FIG. 11).
UTOPIA interface timing controller 81 for sending
And a byte number counter 82 in the cell for receiving the cell head display signal 103, and the ATM cell data 100
, The last cell reception monitoring unit 83, one cell buffer 84,
An AAL5 trailer extraction unit 85 and a CRC-32 inspection unit 86 are included.

Further, the UTOPIA unit 72 receives a data from the buffer 84, the trailer extraction unit 85, and the inspection unit 86, and receives the data from the switching control unit 87 and outputs the ATM cell data 120. In addition, a clock replacement buffer 88 for inputting a clock replacement buffer read signal 121 and a clock replacement buffer write controller 89 are included.

The write control unit 89 transmits / receives a clock replacement buffer write signal 111 and a buffer full display signal 110 to / from the buffer 88,
And cell buffer read signal 108 and buffer read request signal 1
07 is sent and received respectively. Further, the timing control unit 81 outputs the cell buffer write signal 102 to the counter 82, the monitoring unit 83,
And to the buffer 84. The counter 82 supplies a cell byte count signal 104 to the monitoring unit 83, the extraction unit 85, the inspection unit 86, and the write control unit 89. The monitoring unit 83 outputs the last cell display signal 10
6 is given to the extraction unit 85, the inspection unit 86, and the write control unit 89.

In operation, the timing control unit 81 sends a cell read signal 101 to the interface unit 71, and transfers the read ATM cell data 100 to the buffer 8 with a write signal 102.
Write to 4. That is, the timing control unit 81 controls the read flow control and the write timing control of the ATM cell data 100.

FIG. 4A shows a UNI (User-Network Interface:
ATM in user-network interface)
The format of the cell data 100 (20) is shown. The cell data 20 includes a 5-byte header section 21 and a 48-byte payload section 22, and the header section 21 has a 4-bit GF.
C field, 8 bit VPI field, 12 bit VC
I field, 3 bit PTI field, 1 bit CL
It consists of a P field and an 8-bit HEC field.

A virtual path identifier and a virtual channel identifier are written in the VPI and VCI fields, respectively. In the PTI field, the payload type is written.
This indicates that the M cell is the last cell. In the HEC field, a code for error detection and correction of the first 4 bytes is written.

HEC field, VPI field, and VCI
The field becomes unnecessary data (redundant bits) after the switching is performed by the ATM switch 60. Also, GFC
The field is a bit for general flow control, but no specific definition exists yet, and the NNI (Network-Network Interface
e: Inter-network interface), it is a part of the VPI field.

The counter 82 is initialized by the cell head display signal 103 from the interface unit 71, counts the write signal 102, and writes the data into the buffer 84 up to the present of the 53 bytes of the ATM cell data 100. A count signal 104 indicating the number of bytes (byte number) is output.

The monitoring unit 83 determines whether or not the ATM cell 20 currently written in the buffer 84 is the last cell based on the data value of the PTI field = “1xx”. It is displayed on the final cell display signal 106. The buffer 84 is a memory having a capacity of one ATM cell, and supplies a buffer full display signal 105 and a buffer read request signal 107 to the timing controller 81 and the write controller 89 when one cell is accumulated. At this time, the buffer 84 contains
This means that the cell data shown in FIG. 4A is stored.

The extraction unit 85 outputs the cell byte count signal 104
Then, the LI value of the 2-byte LI field is extracted based on the last cell display signal 106 and provided to the switching control unit 87. Inspection unit 86
Performs a CRC-32 inspection of the ATM cell based on the count signal 104 and the display signal 106, and when the inspection result is OK, “0x
00 (fixed value) ”, and“ 0xFF (fixed value) ”to the switching control unit 87 in the case of NG.

The write control unit 89 controls the buffer full display signal 11
Count signal 1 when 0 does not indicate "buffer full"
04, a display signal 106, and a data switching instruction signal 109 to the switching control unit 87 based on the request signal 107, and a write signal 1
11 is supplied to the clock transfer buffer 88.

The switching control unit 87, based on the data switching signal 109, stores the VCI portion of the third byte of the header portion 21 stored in the buffer 84, the VCI, PTI, CLP portion of the fourth byte, and the payload portion of 48 bytes. And outputs the upper byte and lower byte of the LI value (at timing) to the first byte GFC and VPI portions and the second byte VPI and VCI portions of the header portion 21 respectively. The calculation result of CRC-32 is output to the position of the HEC part of the fifth byte. Buffer 88
The data from the switching control unit 87 is stored based on the write signal.

As a result, the contents of the data written in the buffer 88 are as shown in FIG. 2B. The LI value which is the cell assembly information is mapped 47 bytes ahead, and the CRC which is also the cell assembly information. -32 data is calculated as
This means that it has been mapped 40 bytes forward.

The operation so far has been performed with a high-speed clock synchronized with the ATM switch 60. However, the ATM data 120 stored in the buffer 88 can be read out with a low-speed clock signal synchronized with the clock of the transmission line. Done. This read operation will be described in the next embodiment of the SAR unit 73.

FIG. 5 shows an embodiment of the SAR unit 73 shown in FIG. The SAR unit 73 includes an output buffer 92 that receives the ATM cell data 120 from the UTOPIA unit 72, an AAL5 trailer extraction unit 93, and a header information conversion interface unit 94, and a UTO that inputs a buffer full display signal 123 from the output buffer 92.
A PIA read control unit 91, a frame boundary detection unit 95 and a frame header insertion control unit 97 for inputting data from the output buffer 92, and an output buffer read control unit 96 for inputting a buffer empty display signal 128 from the output buffer 92
And is composed of

Further, the read control unit 91 outputs a buffer write signal
122 is provided to the output buffer 92, the extraction unit 93, and the interface unit 94. The extraction unit 93 supplies the valid byte length / CRC-32 inspection result signal 126 to the detection unit 95. Interface section 9
4 transmits / receives the ATM cell header information 125 and the frame header information 124 to / from the CPU interface unit 79 (see the same figure) via the SAR bus 112.

The detection unit 95 outputs a frame boundary detection signal
129 is given to the control unit 97. The read control unit 96 supplies the buffer empty display signal 128 to the output buffer 92 and the detection unit 95. In operation, the read control unit 91 outputs the display signal
When 123 does not indicate that the output buffer 92 is full, the read signal 121 is supplied to the buffer 88 of the UTOPIA section 72, and the write signal 122 is supplied to the output buffer 92, and the ATM cell is supplied from the buffer 88 to the output buffer 92. Transfer the data 120.

The output buffer 92 is a FIFO of 12 (= 7 + 5) bytes.
It has the function of temporarily storing the PAD bytes until the frame header output timing is received until the header information of the last cell is received.
FIG. 6 shows the data temporarily stored when the output buffer 92 receives the header of the last cell 20c. This data is the total of the 7-byte PAD of the intermediate cell 20b and the 5-byte header of the last cell 20c. 12 bytes.

The extraction unit 93 monitors the ATM cell data 120 written in the output buffer 92, and the effective byte length value mapped to the first and second bytes of the header portion of the last cell and the fifth byte to the UTOPIA unit 72. CRC-mapped
32 The test result is extracted and notified to the detection unit 95.

The interface unit 94 extracts the route information (for example, the VCI of the third and fourth bytes) in the header of the ATM cell data 120 to be written into the output buffer 92, and
The TM header information 125 is given to a predetermined table (not shown) via the SAR bus 112 and the CPU interface unit 79 (see FIG. 2), and the frame header information 124 of the frame relay linked to the route information is received. , As frame header information 130 to the control unit 97.

The detection unit 95 counts the number of bytes of data read from the output buffer 92 and compares the counted value with the effective byte length value from the extraction unit 93. And
When both match, it is determined that the frame is a boundary between frames, and a frame boundary detection signal 129 is notified to the insertion control unit 97.

When the buffer empty display signal 128 indicates that the output buffer 92 is not "empty" (there is data), the read control unit 96 waits until the detection signal 129 from the detection unit 95 is asserted. The read signal 127 synchronized with the low-speed clock synchronized with the transmission path is asserted.

After the detection unit 95 asserts the detection signal 129,
The read control unit 96 supplies a read signal 127 synchronized with the high-speed clock of the ATM switch 60 to the output buffer 92 until the cell boundary is read, and outputs the AT remaining in the output buffer 92.
The remaining bytes of the M cell are read and discarded (or discarded) (see FIG. 6).

The insertion control unit 97 receives the AT from the output buffer 92.
The data frame 131 is generated by combining the M cell data and the frame header information 130 from the interface unit 94. At this time, the insertion control unit 97 discards the header part of the ATM cell read from the output buffer 92.

That is, the insertion control section 97 regards the ATM cell to be received next after receiving the detection signal 129 from the detection section 95 as the head cell, and inserts the frame header information 130 given from the interface section 94 into the frame. And then ATM
The payload of the cell is sequentially output as frame data.

When receiving the frame boundary detection signal 129 from the detection unit 95, the insertion control unit 97 outputs an indicator indicating the boundary of the frame to notify the HDLC unit 74 at the subsequent stage of the end of the frame. FIG. 7 shows the cell reception timing of the SAR unit 73 when receiving the ATM cells 20a to 20c shown in FIG. 6 in comparison with the case where the present invention is not applied.

FIG. 7A shows an ATM switch interface unit.
FIG. 6 shows an example in which the UTOPIA unit 72 has received from FIG.
The case where ATM cells 20a to 20c are received is shown. Fig. 7 (2)
Is the ATM in the clock transfer buffer 88 of the UTOPIA section 72.
Cells 20a-20c are shown and these ATM cells 20a-20c
Is delayed by one cell time from the ATM cells 20a to 20c in FIG. Further, cell assembly information (trailer information) is mapped in the header portion of the ATM cell 20c (■
Department).

The transmission / reception and mapping of the ATM cells 20a to 20c in FIGS. 1A and 1B are performed by the ATM switch 60 (see FIG. 10).
High-speed processing in synchronization with the clock 155.52Mbps. FIG. 7 (3) shows the ATM cell 2 received by the SAR unit 73 to which the present invention is applied.
0a to 20c are shown. The ATM cells 20a and 20b, and the header of the ATM cell 20c including the effective byte length value and the CRC-32 inspection result as the cell assembly information, have a transmission line clock of 1.544 Mbps.
SAR processing is performed at low speed in synchronization with Remaining ATM cells 20
The payload portion c is discarded at high speed in synchronization with a clock of 155.52 Mbps.

FIG. 4D shows ATM cells 20a to 20c received by the SAR unit 73 to which the present invention is not applied. The ATM cells 20a to 20c input to the SAR unit 73 are ATM cells 20a to 20c obtained by delaying the ATM cells 20a to 20c shown in FIG. 1A by one cell, and are different from FIG. The cells 20a to 20c whose trailer information is not mapped in the header part.

The SAR unit 73 performs SAR processing on all ATM cells 20a to 20c at low speed in synchronization with a clock of 1.544 Mbps. This is because the SAR unit 73 has not yet read the effective byte length even after the data of the effective byte length has been read.
This is because the boundary between frame data cannot be determined, and the remaining bytes must be read at low speed.

Accordingly, the SAR unit 73 knows the effective byte length at the time when the reading of the trailer information is completed, and
A byte that is 55 bytes back is determined to be a boundary between frames.
Therefore, a buffer of at least 55 bytes is required. Further, the SAR unit 73 cannot read the next cell until the reading of the last byte is completed.

On the other hand, the SAR unit 73 to which the present invention is applied is configured such that the worst byte of the frame data is eight bytes back from the time when the effective byte length is determined (when the second byte of the header of the ATM cell 20c is read). At the boundary, focusing on the effective byte length, it is sufficient to provide a buffer of at least 8 bytes.

Since the remaining bytes of the cells remaining in the clock transfer buffer 88 are found to be invalid bytes, the SAR unit 73 discards the remaining bytes at a high speed, and It is possible to shorten the time interval for reading cells. This makes it possible to suppress a decrease in data throughput on the transmission path.

In the above-described embodiment, the trailer information included in the last cell is mapped to the redundant bits in the header of the last cell. However, the place where the trailer information is mapped to the payload of the cell is defined as a redundant bit. Alternatively, trailer information may be mapped here.

When the frame is divided into a plurality of cells, the trailer information may be mapped to the first cell or intermediate cell before the last cell. For example, in FIG. 6, the LI value of the LI field and the inspection result of the CRC-32 field 17 may be mapped to the header 21 of the intermediate cell 20b, whereby the transmission caused by the 7-byte PAD of the intermediate cell is performed. It is also possible to eliminate the delay.

[0072]

As described above, according to the decellularizing apparatus according to the present invention, the cell assembly information (valid byte length of frame data, error detection information, etc.) is converted into redundant bits ahead of the position at the time of cellification. By performing the mapping, it is possible to reduce the capacity of the buffer for temporarily storing the ATM cells, to shorten the frame assembling end time, and to reduce the transmission delay.

By discarding unnecessary bits at high speed except for rear data included in ATM cell data,
Immediately after receiving the frame data for the effective data length, the next ATM cell can be received, and a decrease in the data throughput of the transmission path can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of a decelerating apparatus according to the present invention.

FIG. 2 is a block diagram showing an embodiment of an STM interface adapter which is an example of a decellularization apparatus according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a UTOPIA section in the decelerating apparatus according to the present invention.

FIG. 4 is a diagram showing a format conversion example of a cell header in the decellularization apparatus according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a SAR unit in the decelerating apparatus according to the present invention.

FIG. 6 is a diagram showing an example of a transmission wait time of frame data in the decelerating apparatus according to the present invention.

FIG. 7 shows an AT in a conventional and decelerating apparatus according to the present invention.
FIG. 3 is a diagram illustrating M cell reception timing.

FIG. 8 is a format diagram of a general AAL5_CPCS_PDU frame.

FIG. 9 is a diagram in which a general AAL5_CPCS_PDU frame is converted into an ATM cell.

FIG. 10 is a block diagram showing a configuration example of a conventional ATM exchange.

FIG. 11 is a block diagram showing a configuration example of a conventional STM interface adapter.

FIG. 12 is a diagram illustrating an example of a conventional frame data transmission waiting state.

[Explanation of symbols]

 10 frame 11 CPCS_PDU payload field 12 PAD field 13 Trailer field 14 CPCS_UU field 15 CPI field 16 LI field 17 CRC-32 field 20, 20a, 20b, ..., 20n ATM cell 21 ATM header section 22 Payload section 30 Facing device 40 ATM switch 50 ATM interface adapter 60 ATM switch 70 STM interface adapter (built-in decelerator) 71 ATM switch interface 72 Clock reload buffer, UTOPIA 73 Decelerator, SAR 74 STM interface controller 75 HDLC 76 T1 framer 77 LIU section 78 T1 interface section 79 CPU interface section 80 Format conversion section 81 UTOPIA interface timing control section 82 Byte number counter in cell 83 Last cell reception monitoring section 84 1-cell buffer 85 AAL5 trailer extraction section 86 CRC-32 inspection section 87 Data switching Control unit 88 Clock transfer buffer 89 Clock replacement buffer write control unit 91 UTOPIA read control unit 92 Output buffer 93 AAL5 trailer extraction unit 94 Header information conversion interface unit 95 Frame boundary detection unit 96 Output buffer read control unit 97 Frame header insertion control unit 100 ATM cell data 101 cells Read signal 102 Cell buffer write signal 103 Cell head display signal 104 Cell byte count signal 105 Buffer full display signal 106 Last cell display signal 107 Buffer read request signal 108 Cell buffer read signal 109 Data switching instruction signal 110 Buffer full display signal 111 Clock Reload buffer write signal 112 SAR bus 113 FR bus 120 ATM cell data 121 Clock reload buffer read signal 122 Buffer write signal 123 Buffer full display signal 124 Frame header information 125 ATM cell header information 126 Valid byte length / CRC-32 inspection Result signal 127 Buffer read signal During 128 buffer empty indication signal 129 frame boundary detection signal 130 frame header information 131 frame data 132 frame data request signal diagram, the same reference numerals denote the same or corresponding parts.

Claims (8)

[Claims] 1. A decellularization apparatus for performing decellularization based on cell assembly information included in a cell, wherein the cell assembly information is decellularized by mapping the cell assembling information to redundant bits ahead of a position at the time of cellization. A decellularizing device comprising means. 2. An apparatus according to claim 1, wherein said cell assembly information is effective byte length information. 3. The apparatus according to claim 1, wherein said cell assembly information is error detection information. 4. The decellularization device according to claim 1, wherein said redundant bits are bits included in a cell including said cell assembly information. 5. The decellularization apparatus according to claim 1, wherein said redundant bits are bits included in a cell preceding said cell containing said cell assembly information. 6. An apparatus according to claim 1, wherein said redundant bits are bits in a cell header. 7. The decelerating apparatus according to claim 1, wherein bits excluding data subsequent to the position where the cell assembly information is mapped are discarded at a high speed. 8. The method according to claim 1, wherein the cell is a cell obtained by converting an AAL5 CPCS_PDU frame into cells, and the cell assembling information is effective byte length information of the frame and CRC-32 operation result information. The redundant bit is
A decellularization device characterized by being a header part of a last cell.