JP2001094102A - Power mos transistor - Google Patents
Power mos transistorInfo
- Publication number
- JP2001094102A JP2001094102A JP27037199A JP27037199A JP2001094102A JP 2001094102 A JP2001094102 A JP 2001094102A JP 27037199 A JP27037199 A JP 27037199A JP 27037199 A JP27037199 A JP 27037199A JP 2001094102 A JP2001094102 A JP 2001094102A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- mos transistor
- power mos
- drain
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 36
- 238000010586 diagram Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、双方向ポリシリコンツ
ェナーダイオードをドレイン・ゲート間に内蔵したパワ
ーＭＯＳトランジスタに関し、特に、パワーＭＯＳトラ
ンジスタのドレイン・ゲート間に接続される双方向ポリ
シリコンツェナーダイオードに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS transistor having a built-in bidirectional polysilicon Zener diode between a drain and a gate, and more particularly to a bidirectional polysilicon Zener diode connected between a drain and a gate of a power MOS transistor. It is about.
【０００２】[0002]
【従来の技術】図４は半導体集積回路を形成するチップ
３０の等価回路を示し、前記チップ３０はゲートが共通
に接続されると共に互いに並列接続された多数の縦型パ
ワーＭＯＳトランジスタ３１と、前記パワーＭＯＳトラ
ンジスタ３１のドレインＤ・ゲートＧ間に接続されると
共に、ポリシリコンからなり逆方向に直列接続された多
数のツェナーダイオード対からなる双方向ポリシリコン
ツェナーダイオード３２とから構成され、例えば、誘導
性負荷を駆動する駆動回路に用いられている。2. Description of the Related Art FIG. 4 shows an equivalent circuit of a chip 30 forming a semiconductor integrated circuit. The chip 30 has a number of vertical power MOS transistors 31 having gates connected in common and connected in parallel with each other. The power MOS transistor 31 is connected between the drain D and the gate G of the power MOS transistor 31 and includes a bidirectional polysilicon Zener diode 32 composed of a large number of Zener diode pairs made of polysilicon and connected in series in the reverse direction. It is used for a drive circuit for driving a conductive load.
【０００３】図５は前記チップ３０の平面図を模式的に
示し、図６乃至図８は図５の一部断面図を示している。
図５に示すように、前記チップ３０の中央部３３には前
記パワーＭＯＳトランジスタ３１が設けられ、また、前
記チップ３０を構成するＮ＋型半導体基板上に形成され
たＮ−型エピタキシャル層中には、前記中央部３３を順
次取り囲むように、Ｐ型ウエル３４、Ｐ型フィールドリ
ミットリング３５及び前記パワーＭＯＳトランジスタ３
１のドレインＤに接続されるＮ＋型領域３６とが形成さ
れ、また、後述するように、前記双方向ポリシリコンツ
ェナーダイオード３２は前記Ｐ型フィールドリミットリ
ング３５と前記Ｎ＋型領域３６との間の前記Ｎ−型エピ
タキシャル層上に周方向に沿いフィールド絶縁膜を介し
て設けられており、前記双方向ポリシリコンツェナーダ
イオード３２の一端部は配線層３７をとおして前記Ｎ＋
型領域３６に接続され、他端部は配線層３８を介して前
記中央部３３の外周に設けられたゲート配線層（図示し
ない）に接続されている。FIG. 5 schematically shows a plan view of the chip 30, and FIGS. 6 to 8 show partial sectional views of FIG.
As shown in FIG. 5, the power MOS transistor 31 is provided at a central portion 33 of the chip 30. The power MOS transistor 31 is provided in an N − type epitaxial layer formed on an N + type semiconductor substrate constituting the chip 30. A P-type well 34, a P-type field limit ring 35 and the power MOS transistor 3 so as to sequentially surround the central portion 33.
An N + -type region 36 connected to the drain D is formed. As will be described later, the bidirectional polysilicon Zener diode 32 is connected between the P-type field limit ring 35 and the N + -type region 36. One end of the bidirectional polysilicon Zener diode 32 is provided on the N − -type epitaxial layer between the N + -type epitaxial layers with a field insulating film interposed therebetween.
The other end is connected to a gate wiring layer (not shown) provided on the outer periphery of the central part 33 via a wiring layer 38.
【０００４】図６は図５のＣ−Ｃ断面図を示し、前記チ
ップ３０を構成するＮ＋型半導体基板４１に形成された
Ｎ−型エピタキシャル層４２上にフィールド絶縁膜４３
が設けられ、前記フィールド絶縁膜４３上にはＮ＋型領
域３２ａ、Ｐ型領域３２ｂ、Ｎ＋型領域３２ｃ、Ｐ型領
域３２ｄ及びＮ＋型領域３２ｅからなる前記双方向ポリ
シリコンツェナーダイオード３２が設けられている。な
お、図６においては便宜のために２個のツェナーダイオ
ード対を示している。前記双方向ポリシリコンツェナー
ダイオード３２の両端の前記Ｎ＋型領域３２ａ、３２ｅ
には層間絶縁膜４４を介して前記した配線層３７、３８
が設けられている。また、前記Ｎ＋型半導体基板４１の
裏面には前記パワーＭＯＳトランジスタ３１のドレイン
Ｄとなるドレイン電極４５が形成されている。FIG. 6 is a sectional view taken along the line CC of FIG. 5, in which a field insulating film 43 is formed on an N − type epitaxial layer 42 formed on an N + type semiconductor substrate 41 constituting the chip 30.
Is provided on the field insulating film 43. The bidirectional polysilicon Zener diode 32 including an N + type region 32a, a P type region 32b, an N + type region 32c, a P type region 32d and an N + type region 32e is provided on the field insulating film 43. Is provided. FIG. 6 shows two Zener diode pairs for convenience. The N + -type regions 32a and 32e at both ends of the bidirectional polysilicon Zener diode 32
The wiring layers 37 and 38 described above are interposed via an interlayer insulating film 44.
Is provided. A drain electrode 45 serving as a drain D of the power MOS transistor 31 is formed on the back surface of the N + type semiconductor substrate 41.
【０００５】図７は図５のＤ−Ｄ断面図を示し、前記双
方向ポリシリコンツェナーダイオード３２の前記一端
部、即ち、前記Ｎ＋型領域３２ｅが前記配線層３７をと
おして前記Ｎ＋型領域３６に接続される状態を示してい
る。FIG. 7 is a sectional view taken along the line DD of FIG. 5, in which the one end of the bidirectional polysilicon Zener diode 32, that is, the N + type region 32e is connected to the N + type through the wiring layer 37. This shows a state of being connected to the area 36.
【０００６】一方、図８は図５のＥ−Ｅ断面図を示し、
前記双方向ポリシリコンツェナーダイオード３２の前記
他端部、即ち、前記Ｎ＋型領域３２ａが前記配線層３８
を介して前記中央部３３の外周に設けられた前記ゲート
配線層に接続される状態を示している。FIG. 8 is a sectional view taken along the line EE of FIG.
The other end of the bidirectional polysilicon Zener diode 32, that is, the N + type region 32a is connected to the wiring layer 38.
3 shows a state in which the semiconductor device is connected to the gate wiring layer provided on the outer periphery of the central portion 33 through the gate.
【０００７】しかして、前記チップ３０において前記双
方向ポリシリコンツェナーダイオード３２は、図５及び
図６に示したように、前記Ｐ型フィールドリミットリン
グ３５と前記Ｎ＋型領域３６との間の前記Ｎ−型エピタ
キシャル層４２上に周方向に沿って前記フィールド絶縁
膜４３を介して設けられ、図８に示したように、前記双
方向ポリシリコンツェナーダイオード３２の他端部であ
る前記Ｎ＋型領域３２ａはその長さ方向とはほぼ垂直に
配置された前記配線層３８を介して前記中央部３３の外
周に設けられた前記ゲート配線層に接続されている。即
ち、前記配線層３８は前記フィールド絶縁膜４３を介し
て前記Ｐ型フィールドリミットリング３５を横切る、或
いは跨いでしまう。それ故、前記チップ３０が前記した
誘導性負荷を有する駆動回路に組み込まれて動作状態に
あるとき、前記Ｐ型フィールドリミットリング３５を横
切る前記配線層３８により、前記パワーＭＯＳトランジ
スタ３１において、前記Ｐ型ウエル３４から前記Ｐ型フ
ィールドリミットリング３５を包むように伸びる空乏層
の形状が変化して前記パワーＭＯＳトランジスタ３１の
ドレインＤ・ソースＳ間の耐圧が部分的に低下してしま
う。As shown in FIGS. 5 and 6, the bidirectional polysilicon Zener diode 32 in the chip 30 is provided between the P-type field limit ring 35 and the N + -type region 36. The N + -type epitaxial layer 42 is provided on the N − -type epitaxial layer 42 along the circumferential direction with the field insulating film 43 interposed therebetween, as shown in FIG. The region 32a is connected to the gate wiring layer provided on the outer periphery of the central portion 33 via the wiring layer 38 arranged substantially perpendicular to the length direction. That is, the wiring layer 38 crosses or straddles the P-type field limit ring 35 via the field insulating film 43. Therefore, when the chip 30 is incorporated in the driving circuit having the inductive load and is in the operating state, the wiring layer 38 traversing the P-type field limit ring 35 causes the power MOS transistor 31 The shape of the depletion layer extending from the mold well 34 so as to surround the P-type field limit ring 35 changes, and the breakdown voltage between the drain D and the source S of the power MOS transistor 31 partially decreases.
【０００８】[0008]
【発明が解決しようとする課題】それ故、本発明の目的
は、双方向ポリシリコンツェナーダイオードをドレイン
・ゲート間に内蔵したパワーＭＯＳトランジスタにおい
て、前記双方向ポリシリコンツェナーダイオードの配線
層がフィールドリミットリングを横切ることのない高耐
圧のパワーＭＯＳトランジスタを提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a power MOS transistor having a built-in bidirectional polysilicon Zener diode between the drain and the gate, wherein the wiring layer of the bidirectional polysilicon Zener diode has a field limit. It is an object of the present invention to provide a high-voltage power MOS transistor that does not cross a ring.
【０００９】[0009]
【課題を解決するための手段】本発明においては、双方
向ポリシリコンツェナーダイオードをパワーＭＯＳトラ
ンジスタの配置された半導体基体の中央部に隣接して設
けられたウエル上にフィールド絶縁膜を介して設け、前
記双方向ポリシリコンツェナーダイオードの一端部には
電極パッドを設けると共に、他端部には前記中央部の外
周に設けられたゲート配線層に接続される配線層を有し
ている。According to the present invention, a bidirectional polysilicon Zener diode is provided via a field insulating film on a well provided adjacent to the center of a semiconductor substrate on which a power MOS transistor is disposed. An electrode pad is provided at one end of the bidirectional polysilicon Zener diode, and the other end has a wiring layer connected to a gate wiring layer provided on the outer periphery of the central portion.
【００１０】[0010]
【発明の実施の形態】第１導電型半導体基体の中央部に
配置されたパワーＭＯＳトランジスタと、前記中央部を
順次取り囲むように、前記第１導電型半導体基体に形成
された第２導電型ウエル、第２導電型フィールドリミッ
トリング及び前記パワーＭＯＳトランジスタのドレイン
に接続される高不純物濃度を有する第１導電型領域とを
備え、前記パワーＭＯＳトランジスタのドレイン・ゲー
ト間に接続されて逆方向に直列接続された多数のツェナ
ーダイオード対からなる双方向ポリシリコンツェナーダ
イオードを前記第２導電型ウエルの周方向に沿ってフィ
ールド絶縁膜を介して設け、前記双方向ポリシリコンツ
ェナーダイオードの一端部には電極パッドを設けると共
に、他端部には前記中央部の外周に設けられたゲート配
線層に接続される配線層を有している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power MOS transistor disposed at a central portion of a first conductive type semiconductor substrate, and a second conductive type well formed on the first conductive type semiconductor substrate so as to sequentially surround the central portion. A second conductivity type field limit ring and a first conductivity type region having a high impurity concentration connected to the drain of the power MOS transistor, and connected between the drain and gate of the power MOS transistor and connected in series in the reverse direction. A bidirectional polysilicon Zener diode comprising a large number of connected Zener diode pairs is provided via a field insulating film along the circumferential direction of the second conductivity type well, and an electrode is provided at one end of the bidirectional polysilicon Zener diode. A pad is provided, and the other end is connected to a gate wiring layer provided on the outer periphery of the central portion. And a line layer.
【００１１】[0011]
【実施例】図１は本発明の実施例による縦型Ｎチャンネ
ルパワーＭＯＳトランジスタのドレイン・ゲート間に接
続されて逆方向に直列接続された多数のツェナーダイオ
ード対からなる双方向ポリシリコンツェナーダイオード
を有するチップ１０の平面図の一部を模式的に示す。な
お、この基本的な等価回路及び構造は先に示した図４及
び図５と同様である。FIG. 1 shows a bidirectional polysilicon Zener diode consisting of a number of Zener diode pairs connected in series in the reverse direction and connected between the drain and gate of a vertical N-channel power MOS transistor according to an embodiment of the present invention. A part of a plan view of a chip 10 having the same is schematically shown. The basic equivalent circuit and structure are the same as those shown in FIGS.
【００１２】図１に示すように、前記チップ１０の中央
部には前記パワーＭＯＳトランジスタ（図示しない）が
設けられ、また、前記チップ１０を構成する半導体基
体、即ち、Ｎ＋型半導体基板１１上に形成されたＮ−型
エピタキシャル層１２中には、前記中央部を順次取り囲
むように、Ｐ型ウエル１３、Ｐ型フィールドリミットリ
ング１４及び前記パワーＭＯＳトランジスタのドレイン
Ｄに接続されるＮ＋型領域１５とが形成され、後述する
ように、前記双方向ポリシリコンツェナーダイオード１
６は前記Ｐ型ウエル１３の周方向に沿いフィールド絶縁
膜１７を介して設けられている。As shown in FIG. 1, the power MOS transistor (not shown) is provided at a central portion of the chip 10, and a semiconductor substrate constituting the chip 10, that is, an N + type semiconductor substrate 11 is provided. In the N − -type epitaxial layer 12 formed in the above, an N + -type region connected to the P-type well 13, the P-type field limit ring 14 and the drain D of the power MOS transistor so as to sequentially surround the central portion. 15 are formed, and as described later, the bidirectional polysilicon Zener diode 1 is formed.
6 is provided along the circumferential direction of the P-type well 13 with a field insulating film 17 interposed therebetween.
【００１３】前記双方向ポリシリコンツェナーダイオー
ド１６が位置する前記Ｐ型ウエル１３は幅広に形成さ
れ、また、前記双方向ポリシリコンツェナーダイオード
１６の一端部には前記チップ１０のドレインにワイヤー
（図示しない）を介して接続される電極パッド１８が設
けられ、他端部には前記中央部の外周に設けられたゲー
ト配線層（図示しない）に接続される配線層１９が設け
られている。The P-type well 13 where the bidirectional polysilicon Zener diode 16 is located is formed wide, and one end of the bidirectional polysilicon Zener diode 16 has a wire (not shown) connected to the drain of the chip 10. ) Is provided, and a wiring layer 19 connected to a gate wiring layer (not shown) provided on the outer periphery of the central portion is provided at the other end.
【００１４】図２は図１のＡ−Ａ断面図を示し、前記チ
ップ１０を構成する前記Ｎ＋型半導体基板１１に形成さ
れた前記Ｎ−型エピタキシャル層１２上に前記フィール
ド絶縁膜１７が設けられ、前記フィールド絶縁膜１７上
にはＮ＋型領域１６ａ、Ｐ型領域１６ｂ、Ｎ＋型領域１
６ｃ、Ｐ型領域１６ｄ及びＮ＋型領域１６ｅからなる前
記双方向ポリシリコンツェナーダイオード１６が設けら
れている。なお、図２においては便宜のために２個のツ
ェナーダイオード対を示している。前記双方向ポリシリ
コンツェナーダイオード１６の両端の前記Ｎ＋型領域１
６ａ、１６ｅには層間絶縁膜２０を介して前記パッド１
８及び前記配線層１９がそれぞれ設けられている。ま
た、前記Ｎ＋型半導体基板１１の裏面には前記パワーＭ
ＯＳトランジスタのドレインＤとなるドレイン電極２１
が形成されている。FIG. 2 is a sectional view taken along the line AA of FIG. 1. The field insulating film 17 is provided on the N − type epitaxial layer 12 formed on the N + type semiconductor substrate 11 constituting the chip 10. On the field insulating film 17, an N + type region 16a, a P type region 16b, and an N + type region 1
6c, a P-type region 16d and an N + -type region 16e. FIG. 2 shows two Zener diode pairs for convenience. The N + type region 1 at both ends of the bidirectional polysilicon Zener diode 16
6a and 16e are connected to the pad 1 via an interlayer insulating film 20.
8 and the wiring layer 19 are provided. The power M is provided on the back surface of the N + type semiconductor substrate 11.
Drain electrode 21 serving as drain D of OS transistor
Are formed.
【００１５】図３は図１のＢ−Ｂ断面図を示し、前記双
方向ポリシリコンツェナーダイオード１６の前記他端部
である前記Ｎ＋型領域１６ｅが前記配線層１９を介して
前記中央部の外周に設けられたゲート配線層に接続され
る状態を示している。FIG. 3 is a cross-sectional view taken along the line BB of FIG. 1. The N + type region 16 e, which is the other end of the bidirectional polysilicon Zener diode 16, is located at the center of It shows a state where it is connected to a gate wiring layer provided on the outer periphery.
【００１６】上記したように本発明の構成によれば、前
記双方向ポリシリコンツェナーダイオード１６は前記パ
ワーＭＯＳトランジスタの配置された前記チップ１０、
即ち半導体基体の中央部に隣接して設けられた前記Ｐ型
ウエル１３上にフィールド絶縁膜１７を介して設けら
れ、しかも、前記双方向ポリシリコンツェナーダイオー
ド１６の一端部の前記Ｎ＋型領域１６ａには前記電極パ
ッド１８が設けられて、前記電極パッド１８からのワイ
ヤーにより前記チップ１０のドレインに電気的に接続さ
れるので、前記Ｐ型フィールドリミットリング１４を直
接横切る、或いは跨ぐことがない。さらに、前記双方向
ポリシリコンツェナーダイオード１６の配置に伴って、
前記双方向ポリシリコンツェナーダイオード１６の他端
部である前記Ｎ＋型領域１６ｅは前記配線層１９を介し
て前記中央部の外周に設けられたゲート配線層に接続さ
れ、同様に、前記Ｐ型フィールドリミットリング１４を
直接横切る、或いは跨ぐことがなく、空乏層に影響を与
えることがない。As described above, according to the configuration of the present invention, the bidirectional polysilicon Zener diode 16 is connected to the chip 10 on which the power MOS transistor is disposed,
That is, the N + -type region 16a is provided on the P-type well 13 provided adjacent to the center portion of the semiconductor substrate with the field insulating film 17 interposed therebetween and at one end of the bidirectional polysilicon Zener diode 16. The electrode pad 18 is provided, and is electrically connected to the drain of the chip 10 by a wire from the electrode pad 18. Therefore, the electrode pad 18 does not directly cross or straddle the P-type field limit ring 14. Further, with the arrangement of the bidirectional polysilicon Zener diode 16,
The N + type region 16 e, which is the other end of the bidirectional polysilicon Zener diode 16, is connected to a gate wiring layer provided on the outer periphery of the central portion via the wiring layer 19, and similarly, the P + It does not directly cross or straddle the field limit ring 14 and does not affect the depletion layer.
【００１７】前記実施例において縦型Ｎチャンネルパワ
ーＭＯＳトランジスタについて説明したが、同様に、縦
型ＰチャンネルパワーＭＯＳトランジスタだけでなく横
型のパワーＭＯＳトランジスタにも適用できることは当
業者には明らかである。Although a vertical N-channel power MOS transistor has been described in the above embodiment, it is apparent to those skilled in the art that the present invention can be similarly applied to a horizontal power MOS transistor as well as a vertical P-channel power MOS transistor.
【００１８】[0018]
【発明の効果】本発明によれば、逆方向に直列接続され
た多数のツェナーダイオード対からなる双方向ポリシリ
コンツェナーダイオードをドレイン・ゲート間に内蔵し
たパワーＭＯＳトランジスタにおいて、前記双方向ポリ
シリコンツェナーダイオードはパワーＭＯＳトランジス
タの配置された半導体基体の中央部に隣接して設けられ
たウエル上にフィールド絶縁膜を介して設けられ、前記
双方向ポリシリコンツェナーダイオードの一端部には電
極パッドが設けらると共に、他端部には前記中央部の外
周に形成されたゲート配線層に接続される配線層を有し
ている。即ち、前記電極パッドはワイヤーを介してドレ
インにワイヤーを介して接続されているので、フィール
ドリミットリングを直接横切ることがなく、同様に前記
配線層も前記フィールドリミットリングを横切ることが
ない。それ故、前記パワーＭＯＳトランジスタのドレイ
ンＤ・ソースＳ間の部分的な耐圧の低下を防止すること
ができる。According to the present invention, there is provided a power MOS transistor in which a bidirectional polysilicon Zener diode comprising a large number of Zener diode pairs connected in series in a reverse direction is built in between a drain and a gate. The diode is provided via a field insulating film on a well provided adjacent to the center of the semiconductor substrate on which the power MOS transistor is disposed, and an electrode pad is provided at one end of the bidirectional polysilicon Zener diode. In addition, the other end has a wiring layer connected to a gate wiring layer formed on the outer periphery of the central portion. That is, since the electrode pad is connected to the drain via the wire via the wire, the electrode pad does not directly cross the field limit ring, and similarly, the wiring layer does not cross the field limit ring. Therefore, it is possible to prevent a partial decrease in withstand voltage between the drain D and the source S of the power MOS transistor.
【図１】本発明の実施例によるパワーＭＯＳトランジス
タのドレイン・ゲート間に接続されて逆方向に直列接続
された多数のツェナーダイオード対からなる双方向ポリ
シリコンツェナーダイオードを有するチップの平面図の
一部を模式的に示す図である。FIG. 1 is a plan view of a chip having a bidirectional polysilicon Zener diode including a large number of Zener diode pairs connected between a drain and a gate of a power MOS transistor and connected in series in a reverse direction according to an embodiment of the present invention; It is a figure which shows a part typically.
【図２】図１のＡ−Ａ断面図を示す図である。FIG. 2 is a diagram showing a cross-sectional view taken along line AA of FIG. 1;
【図３】図１のＢ−Ｂ断面図を示す図である。FIG. 3 is a diagram showing a BB cross-sectional view of FIG. 1;
【図４】従来のパワーＭＯＳトランジスタのドレイン・
ゲート間に接続されて逆方向に直列接続された多数のツ
ェナーダイオード対からなる双方向ポリシリコンツェナ
ーダイオードを有するチップの等価回路を示す図であ
る。FIG. 4 shows the drain of a conventional power MOS transistor;
It is a figure showing the equivalent circuit of a chip which has a bidirectional polysilicon Zener diode consisting of many Zener diode pairs connected between gates and connected in series in the reverse direction.
【図５】図４におけるチップの平面図を模式的に示す図
である。FIG. 5 is a diagram schematically showing a plan view of a chip in FIG. 4;
【図６】図５のＣ−Ｃ断面図を示す図である。6 is a diagram showing a cross-sectional view taken along the line CC of FIG. 5;
【図７】図５のＤ−Ｄ断面図を示す図である。FIG. 7 is a diagram showing a cross-sectional view taken along line DD of FIG. 5;
【図８】図５のＥ−Ｅ断面図を示す図である。FIG. 8 is a diagram showing a cross-sectional view taken along the line EE of FIG. 5;
１０…チップ、１１…Ｎ＋型半導体基板、１２…Ｎ−型
エピタキシャル層、１３…Ｐ型ウエル、１４…Ｐ型フィ
ールドリミットリング、１５…Ｎ＋型領域、１６…双方
向ポリシリコンツェナーダイオード、１６ａ、１６ｃ、
１６ｅ…Ｎ＋型領域、１６ｂ、１６ｄ…Ｐ型領域、１７
…フィールド絶縁膜、１８…電極パッド、１９…配線
層、２０…層間絶縁膜、２１…ドレイン電極10 ... chip, 11 ... N + type semiconductor substrate, 12 ... N - type epitaxial layer, 13 ... P type well, 14 ... P type field limit ring, 15 ... N + type region, 16 ... bidirectional polysilicon Zener diode, 16a, 16c,
16e ... N + type region, 16b, 16d ... P type region, 17
... field insulating film, 18 ... electrode pad, 19 ... wiring layer, 20 ... interlayer insulating film, 21 ... drain electrode
Claims (2)
れたパワーＭＯＳトランジスタと、前記中央部を順次取
り囲むように、前記第１導電型半導体基体に形成された
第２導電型ウエル、第２導電型フィールドリミットリン
グ及び前記パワーＭＯＳトランジスタのドレインに接続
される高不純物濃度を有する第１導電型領域とを備え、
前記パワーＭＯＳトランジスタのドレイン・ゲート間に
接続されて逆方向に直列接続された多数のツェナーダイ
オード対からなる双方向ポリシリコンツェナーダイオー
ドを前記第２導電型ウエルの周方向に沿って設け、前記
双方向ポリシリコンツェナーダイオードの一端部には電
極パッドを設けると共に、他端部には前記中央部の外周
に設けられたゲート配線層に接続される配線層を有する
ことを特徴とする双方向ポリシリコンツェナーダイオー
ドをドレイン・ゲート間に内蔵したパワーＭＯＳトラン
ジスタ。A power MOS transistor disposed at a central portion of the first conductive type semiconductor substrate; a second conductive type well formed on the first conductive type semiconductor substrate so as to sequentially surround the central portion; A first conductivity type region having a high impurity concentration connected to a two conductivity type field limit ring and a drain of the power MOS transistor;
A bidirectional polysilicon Zener diode comprising a large number of Zener diode pairs connected between the drain and the gate of the power MOS transistor and connected in series in the reverse direction is provided along the circumferential direction of the second conductivity type well. Bidirectional polysilicon, characterized in that an electrode pad is provided at one end of a directional polysilicon Zener diode and a wiring layer connected to a gate wiring layer provided on an outer periphery of the center is provided at the other end. Power MOS transistor with a built-in Zener diode between drain and gate.
純物濃度を有する前記第１導電型領域に接続されること
を特徴とする請求項１記載の双方向ポリシリコンツェナ
ーダイオードをドレイン・ゲート間に内蔵したパワーＭ
ＯＳトランジスタ。2. The bidirectional polysilicon Zener diode according to claim 1, wherein said electrode pad is connected to said first conductivity type region having a high impurity concentration via a wire. Built-in power M
OS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27037199A JP4389303B2 (en) | 1999-09-24 | 1999-09-24 | Power MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27037199A JP4389303B2 (en) | 1999-09-24 | 1999-09-24 | Power MOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001094102A true JP2001094102A (en) | 2001-04-06 |
| JP4389303B2 JP4389303B2 (en) | 2009-12-24 |
Family
ID=17485340
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27037199A Expired - Fee Related JP4389303B2 (en) | 1999-09-24 | 1999-09-24 | Power MOS transistor |
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| Country | Link |
|---|---|
| JP (1) | JP4389303B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005236224A (en) * | 2004-02-23 | 2005-09-02 | Sanken Electric Co Ltd | Semiconductor device |
-
1999
- 1999-09-24 JP JP27037199A patent/JP4389303B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005236224A (en) * | 2004-02-23 | 2005-09-02 | Sanken Electric Co Ltd | Semiconductor device |
| JP4547934B2 (en) * | 2004-02-23 | 2010-09-22 | サンケン電気株式会社 | Insulated gate field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4389303B2 (en) | 2009-12-24 |
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