JP2001094068A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which prevents the structure of a capacitor from becoming complicated, even when the semiconudctor device is integrated highly by a method where the permittivity of a BST thin film is increased. SOLUTION: A thin film, which has a compressive film stress is formed in the upper part of a BST thin film, tensile stress is loaded inside the BST thin film, and thereby, the permittivity of the BST thin film is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure and a manufacturing method of a semiconductor memory with improved integration and reliability.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device such as a DRAM, a memory cell structure has been complicated and a film thickness of a dielectric thin film has been reduced in order to prevent a decrease in accumulated charge capacity due to high integration. . However, with the further increase in integration, it has become difficult to obtain a sufficient amount of accumulated charges by these methods alone.

Therefore, efforts have been made to use a dielectric material having a large dielectric constant. As one of these dielectric materials having a large dielectric constant, BST, that is, (Ba, Sr) TiO ₃ is mentioned. The relative permittivity of this BST is 1500 in bulk value.
It is known that when the thickness is reduced for application to a semiconductor device, it is reduced to about 150, and how to increase the relative permittivity is a problem in application.

[0004]

If the relative dielectric constant of a dielectric film can be increased, a device with higher integration can be manufactured with high reliability. That is, by increasing the relative dielectric constant, the amount of accumulated charge per unit area increases, so that a highly integrated device can be realized without using a complicated capacitor structure. As a result, the cost can be reduced and the reliability can be improved.

That is, an object of the present invention is to improve the yield and product reliability by increasing the relative dielectric constant of a BST film and avoiding a complicated three-dimensional structure of a capacitor of a semiconductor device.

[0006]

Means for Solving the Problems The present inventor has conducted various experiments using a BST capacitor manufactured by a thin film process with the aim of improving the relative dielectric constant by positively applying a stress to the BST film. Was done. As a result, BST
By compressing the residual stress of the upper electrode in contact with the thin film and pulling the stress of the BST film in a direction parallel to the film surface,
It became clear that this problem could be solved. That is,
By forming the upper electrode in the upper layer of the BST film so as to have a compressive stress at room temperature, it was possible to obtain a dielectric constant 2.5 times or more the relative dielectric constant of the conventional BST thin film.

In addition, even when a thin film used for the upper electrode has a tensile residual stress in a single film state, a film having a large compressive residual stress is formed thereon to similarly increase the relative dielectric constant. I found that it can be raised.

[0008] The object of the present invention is solved by providing a semiconductor device having a capacitor comprising a first electrode, a dielectric film having a perovskite structure, and a second electrode, having the following configuration.

(A): The lattice spacing of the second electrode is smaller than the lattice spacing of the second electrode in the unstressed state. For example, when the material forming the second electrode is ruthenium, the lattice spacing of the second electrode may be smaller than 2.706 ° on the a-axis and smaller than 4.282 ° on the c-axis.

(B): The lattice spacing of the dielectric film is larger than the lattice spacing of the dielectric film in a non-stress state. For example, when the material constituting the dielectric film is (Ba, Sr) TiO3, the lattice spacing of the dielectric film may be larger than 3.95 °.

As a result, a tensile stress acts on the dielectric film in a direction parallel to the surface of the dielectric film, so that the dielectric constant of the dielectric film can be increased.

The object of the present invention is attained by providing the following structure in a semiconductor device having a capacitor composed of a lower electrode, a dielectric film having a perovskite structure, and an upper electrode.

(C): The upper electrode has a compressive residual stress in the direction along the surface of the dielectric film at room temperature. Further, the room temperature is 20 ° C., and the upper electrode has a compressive residual stress in a direction parallel to the surface of the dielectric film.

(D): The dielectric film has a compressive residual stress in a direction along the surface of the dielectric film at room temperature. Further, the room temperature is 20 ° C., and the dielectric film has a tensile residual strain in a direction parallel to the surface of the dielectric film.

Thus, a tensile stress acts on the dielectric film in a direction parallel to the surface of the dielectric film, so that the dielectric constant of the dielectric film can be increased.

The object of the present invention is attained by providing a semiconductor device having a capacitor comprising a first electrode, a dielectric film having a perovskite structure, and a second electrode, having the following configuration.

(E): An insulating film is formed so as to be in contact with the second electrode, and the insulating film has a compressive residual stress at room temperature.

Thus, a tensile stress can be applied to the dielectric film in a direction parallel to the surface of the dielectric film, so that the dielectric constant of the dielectric film can be increased. In addition, since the insulating film has a compressive residual stress, it also has a function of preventing a crack from entering the interlayer film.

(F): deforming the semiconductor substrate so as to be convex toward the one main surface by removing the second electrode.

The object of the present invention is attained by providing the following structure in a method of manufacturing a semiconductor device having a capacitor comprising a lower electrode, a dielectric film having a perovskite structure, and an upper electrode.

(G): a step of forming a dielectric having a perovskite structure; and a step of forming an upper electrode along the surface of the dielectric. In the step of forming the upper electrode, the upper electrode is formed. Should be formed to have compressive stress near room temperature.

(H): forming a dielectric having a perovskite structure, forming an upper electrode along the surface of the dielectric, and forming an interlayer insulating film on the upper electrode. In the step of forming the interlayer insulating film, the interlayer insulating film is formed so as to have a compressive stress near room temperature.

The present applicant has conducted a prior art search based on the results of the invention, but has found nothing that discloses the present invention or suggests the present invention.

From the viewpoint of increasing the relative permittivity by applying stress to the BST capacitor, the following two prior arts have been extracted, but none of the documents suggests the present invention.

(1) JP-A-10-270662:
This is intended to reduce the dielectric constant drop due to the deformation of the lower electrode during the formation of the BST film due to the device structure by changing the electrode deposition conditions. There is no suggestion about making the stress of the electrode a compressive stress or applying a stress to the BST film in a direction parallel to the film surface.

(2) JP-A-10-144883:
This refers to the handling of the lower electrode, and attempts to extend the BST film in the film thickness direction by crystallizing the BST film on a ruthenium film formed at room temperature. There is no description suggesting handling or making the stress of the electrode a compressive stress.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. In this example, BST was used as a dielectric material.However, it has been confirmed that a ferroelectric film having a perovskite structure and a high dielectric film have the same effect. The present invention may be applied to body film materials.

FIG. 1 shows a sectional structure of a semiconductor device 1 according to a first embodiment of the present invention. In the first embodiment of the present invention shown in FIG. 1, an element isolation film 13 is formed on a silicon substrate 2.
The gate oxide film 7 and the gate electrode 3 are formed to form a transistor. Above them, a capacitor lower electrode 8, a dielectric film 9, and a capacitor upper electrode 10 are formed to accumulate charges. Further around and above the interlayer insulating film 4,
6 and 11 are formed, and wirings 5a and 5b are formed on and around the top.

The semiconductor device 1 of FIG. 1 is formed by the following manufacturing method. First, in order to electrically insulate and isolate each transistor, the silicon substrate is locally thermally oxidized to form an element isolation film 13. Further, a gate oxide film 7 is formed in a region where a transistor is to be formed by a thermal oxidation method, and a gate electrode 3 is formed thereon by a CVD method and a subsequent photolithography technique. Ion implantation is performed to form a pn junction inside the silicon substrate 2, and an ion implantation layer is formed. An interlayer insulating film 4 is formed on the gate electrode 3 so as to cover the gate electrode 3 by using a CVD method. At this time, in order to make the surface of the interlayer insulating film 4 as flat as possible, reflow of the interlayer insulating film 4 by annealing or etching back by depositing a thick interlayer insulating film is performed. Furthermore, interlayer insulating film 4
A lower wiring 5a is formed on the upper surface of the substrate by using a sputtering method and a subsequent photolithography technique. Above this, an interlayer insulating film 6 mainly composed of a silicon nitride film or a silicon oxide film is formed. Further, a lower electrode 8 of the capacitor is formed thereabove, and a dielectric film 9 is formed along the side wall thereof.
Is formed. Further, an upper electrode 10 is formed on the upper surface. At this time, the upper electrode 10 is formed to have a compressive stress near room temperature. The interlayer insulating film 11, the wirings 5b, and through holes for electrically connecting the wirings are formed in the periphery and above using photolithography and etching techniques. In the present embodiment, by making the upper electrode film have a compressive stress, it is possible to apply a tensile stress to the BST film in a direction parallel to the film surface, so that the relative dielectric constant of the dielectric film 9 can be improved. Can be.
For this reason, the height of the capacitor portion composed of the lower electrode 8, the dielectric film 9, and the upper electrode 10 can be reduced, and defects due to insufficient coverage of the upper electrode film can be prevented. In addition, it is not necessary to make the structure of the capacitor section complicated, and the reliability and yield of the semiconductor device 1 can be improved. Further, the present embodiment is also applicable to a flat capacitor structure as shown in FIG. 2, a crown capacitor structure as shown in FIG. 7, or a fin structure as shown in FIG.

FIG. 3 shows the relationship between the accumulated charge amount and the applied voltage when the stress of the upper electrode changes. Upper electrode 1
-300MPa compared to the case where 0 stress is 0MPa (○ in the figure)
In the case of (compression stress) (● in the figure), the slope of the graph is large, and it is clear that the amount of accumulated charge is significantly increased when the upper electrode 10 is formed of a thin film having compressive stress. In summarizing this, FIG. 4 shows the relationship between the relative permittivity of the dielectric and the stress when the stress of the upper electrode is changed. When the stress of the upper electrode is -300 MPa, as compared with the case of 0 MPa, Achieves an increase in dielectric constant of 2.5 times or more.

On the other hand, when the upper electrode 10 is formed of a film having a tensile stress, a decrease in the dielectric constant of the dielectric film 9 is observed, and the effectiveness of this embodiment is apparent. In addition,
The stress value of the film at this time was determined by the X-ray residual stress measurement method.
It was obtained by determining the stress component in the direction parallel to the substrate.
Further, in this example, it was confirmed that the same effect was naturally obtained even when the upper electrode had a fiber orientation, but it was difficult to separate the stress components when measuring the residual stress. The sign and magnitude of the residual stress can be obtained from the shift. For example, when the upper electrode 10 is formed of ruthenium (Ru), the Ru film (0001)
In the fiber orientation state, the lattice spacing d in the no-stress state is 2.706 ° on the a-axis and 4.282 ° on the c-axis, but if it is smaller than this, the effect described in this embodiment is exhibited. Even in the case of taking other orientations, the lattice spacing of the film used in the same manner may be smaller than the lattice spacing in the non-stress state. At this time, the lattice spacing determined by X-ray diffraction of the BST film, which is one kind of the dielectric film 9, is 3.9 in a stress-free state.
Although it is 5 °, if the value is larger than this, the effect described in the present embodiment is exhibited.

The film stress at this time can be roughly estimated from the warpage of the chip. The sign of the stress and the magnitude of the stress can be roughly estimated from the direction of change in the warpage of the chip before and after the process of removing the upper electrode 10 by etching. For example, when the warpage of the chip after etching the upper electrode 10 changes so as to be convex upward with the device forming surface facing upward as compared to before the etching, the upper electrode has tensile stress. Will be. Further, the magnitude of the stress can be roughly estimated from the change amount.

In this embodiment, Ru is used for the upper electrode 10. However, platinum-based metals such as Pt, Pd, and Ir, or mixtures and oxides thereof, and any one of silicide, TiN, WN, and TaN are used. Then a similar effect can be expected. The dielectric film 9 is made of a perovskite-based high dielectric material such as BST or SrTiO ₃ .

The present inventors separately confirmed the effect using a flat capacitor as shown in FIG. 5, and confirmed that the dielectric constant increased when the film stress of the upper electrode 10 was changed to a compressive stress. are doing. In this case, since the upper part of the capacitor is the open end, no stress is applied in the thickness direction of the dielectric film 9 and the stress applied to the dielectric film 9 is only the stress in the direction parallel to the film surface. Has become. In other words, the relative permittivity can be increased by forming the upper electrode 10 from a thin film having a compressive residual stress at room temperature and applying a tensile stress to the dielectric film 9 in a direction parallel to the surface thereof. It is clear. As described above, in the semiconductor device according to the present invention using the BST capacitor, the relative dielectric constant of the BST film can be improved by using a thin film having a compressive stress at room temperature (around 20 ° C.) as the upper electrode. As a result, it is not necessary to process the capacitor into a complicated shape as in the related art, and the reliability and yield of the semiconductor device can be improved.

For reference, the conventional material Ta ₂ O
_{The case where five} films are used as a dielectric material is also shown. FIG. 6 shows the case where the stress of the upper electrode at room temperature is 0 MPa, and -30.
The relationship between the stress and the relative dielectric constant when the pressure is 0 MPa is shown. It can be seen that the relationship between the applied voltage and the accumulated charge is constant regardless of the stress of the upper electrode. That is, in the conventional dielectric material, the relative dielectric constant does not change due to the stress of the upper electrode, and the present invention, which attempts to improve the relative dielectric constant of the dielectric film by the stress, uses a perovskite-based high dielectric It can be said that this utilizes a new phenomenon applicable to a capacitor using a thin film.

FIG. 9 shows a second embodiment of the present invention. In this embodiment, a stress load film 12 having a compressive stress is disposed above the capacitor portion. Since the stress load 12 has a compressive stress, a tensile force acts on the dielectric film 9 in a direction parallel to the film surface, so that the dielectric constant can be increased. As a result, it is not necessary to process the capacitor into a complicated shape as in the related art, and the reliability and yield of the semiconductor device can be improved. Stress loading film 1
2 may have the same insulating effect and barrier effect as the interlayer insulating film. In this case, there is an added advantage that a crack is not easily formed in the film even when stress is applied from a wiring or the like.

In this case, the effect becomes larger as the area where the stress load film 12 and the dielectric film 9 are parallel to each other is larger. In addition, the effect increases as the distance between the upper electrode 10 and the stress load film 12 decreases. Or upper electrode 1
0 and the stress load film 12 may be in contact with each other as shown in FIG. In this case, the stress load film 12 is preferably an oxide film, a nitride film, or a semiconductor film.

Further, the interlayer insulating film 11 existing above or around the capacitor may be subjected to a compressive stress at room temperature. In this case, not only the advantage of increasing the dielectric constant of the dielectric film 9 of the capacitor but also the effect of preventing cracks in the interlayer film by compressing the stress in the interlayer insulating film. There is also.

At this time, the film stress can be measured using X-rays, but can be roughly estimated from the warpage of the chip as shown in the first embodiment. Stress load film 12 and interlayer insulating film 1
The sign and magnitude of the stress can be roughly estimated from the direction of change in the warpage of the chip before and after the process of removing 1 by etching. In particular, this method is optimal for estimating the stress of an oxide film or a nitride film having no crystal structure.

[0040]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

According to the present invention, the relative dielectric constant of the dielectric film of the capacitor can be increased, so that the capacitor does not need to have a complicated shape, and the reliability and manufacturing of the semiconductor device can be improved even when the integration is high. It is possible to improve the yield.

Further, according to the present invention, the relative permittivity of the dielectric film of the capacitor can be increased, so that the height of the capacitor does not need to be increased, and poor filling due to insufficient coverage at the time of film formation can be prevented. There is an advantage that you can.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing the relationship between the amount of storage electrode and the applied voltage of a dielectric film according to the present invention when the stress of an upper electrode in a dielectric material is changed.

FIG. 4 is a diagram showing the relationship between the relative dielectric constant and the stress of the dielectric film according to the present invention when the stress of the upper electrode is changed.

FIG. 5 is a schematic cross-sectional view of the semiconductor device in a state where no film is formed on the upper electrode according to the first embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the relative dielectric constant of a conventional dielectric film and the stress when the stress of the upper electrode is changed.

FIG. 7 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a schematic sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Silicon substrate, 3 ... Gate electrode,
4 interlayer insulating film, 5a, 5b lower wiring, 6 interlayer insulating film, 7 gate oxide film, 8 lower electrode, 9 dielectric film,
Reference numeral 10 denotes an upper electrode, 11 denotes an interlayer insulating film, 12 denotes a stress load film, and 13 denotes an element isolation film.

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Joe Yoji 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Isamu 6-16-16 Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi, Ltd. Device Development Center (reference) 5F038 AC05 AC15 EZ20 5F083 AD14 AD23 AD24 AD56 JA13 JA14 JA38 MA06 MA17

Claims (12)

[Claims] A semiconductor substrate, a first electrode electrically connected to the semiconductor substrate, and a second electrode provided on the first electrode via a dielectric film having a perovskite structure. The first electrode, the dielectric film, and the second
A semiconductor device, wherein a capacitor is formed by the electrodes and the lattice spacing of the second electrode is smaller than the lattice spacing of the second electrode in an unstressed state. 2. A material forming the second electrode is ruthenium, and the lattice spacing of the second electrode is 2.70 on the a-axis.
2. The semiconductor device according to claim 1, wherein the angle is smaller than 6 ° and smaller than 4.282 ° on the c-axis. 3. A semiconductor substrate, a first electrode electrically connected to the semiconductor substrate, and a second electrode provided on the first electrode via a dielectric film having a perovskite structure. The first electrode, the dielectric film, and the second
A semiconductor device in which a capacitor is formed by the electrodes and the lattice spacing of the dielectric film is larger than the lattice spacing of the dielectric film in an unstressed state. 4. The material constituting said dielectric film is (Ba, Sr) TiO.
Is _3, the lattice spacing of the dielectric film semiconductor device according to claim 3, wherein even greater than 3.95A. 5. A semiconductor substrate, a lower electrode electrically connected to the semiconductor substrate, and an upper electrode provided on the lower electrode via a dielectric film having a perovskite structure.
A semiconductor device comprising: a capacitor formed of the lower electrode, the dielectric film, and the upper electrode, wherein the upper electrode has a compressive residual stress in a direction along a surface of the dielectric film at room temperature. 6. The semiconductor device according to claim 5, wherein the room temperature is 20 ° C., and the upper electrode has a compressive residual stress in a direction parallel to a surface of the dielectric film. 7. A semiconductor substrate, a lower electrode electrically connected to the semiconductor substrate, and an upper electrode provided on the lower electrode via a dielectric film having a perovskite structure.
A semiconductor device comprising: a capacitor formed by the lower electrode, the dielectric film, and the upper electrode, wherein the dielectric film has a compressive residual stress in a direction along a surface of the dielectric film at room temperature. 8. The semiconductor device according to claim 7, wherein said room temperature is 20 ° C., and said dielectric film has a tensile residual strain in a direction parallel to a surface of said dielectric film. 9. A semiconductor substrate, a first electrode electrically connected to the semiconductor substrate, and a second electrode provided on the first electrode via a dielectric film having a perovskite structure. And an insulating film formed in contact with the second electrode, wherein the insulating film has a compressive residual stress at room temperature. 10. A semiconductor substrate, a first electrode electrically connected to the semiconductor substrate, and a second electrode provided on the first electrode via a dielectric film having a perovskite structure. Wherein the semiconductor substrate is deformed so as to be convex toward the one main surface by removing the second electrode. 11. A step of supplying a semiconductor substrate having an element isolation film, a gate insulating film, and a gate electrode formed on one main surface;
Forming an interlayer insulating film on one main surface side of the semiconductor substrate, forming a lower electrode on the opposite side of the interlayer insulating film from the semiconductor substrate, and forming a perovskite structure along a surface of the lower electrode. Forming a dielectric having: and forming an upper electrode along the surface of the dielectric, wherein the upper electrode has a compressive stress near room temperature in the step of forming the upper electrode. Of manufacturing a semiconductor device formed in a semiconductor device. 12. A step of supplying a semiconductor substrate having an element isolation film, a gate insulating film, and a gate electrode formed on one main surface;
Forming an interlayer insulating film on one main surface side of the semiconductor substrate, forming a lower electrode above the interlayer insulating film, and forming a dielectric having a perovskite structure along the surface of the lower electrode Forming an upper electrode along the surface of the dielectric; and forming an interlayer insulating film on the upper electrode. A method for manufacturing a semiconductor device, wherein an insulating film is formed to have a compressive stress near room temperature.