JP2001092868A - Device and method for designing circuit and computer- readable recording medium storing circuit design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the labor and time required for manufacturing an integrated circuit. SOLUTION: A circuit designing device is provided with a power supply wiring generating means 111 which generates power supply wiring in an integrated circuit based on circuit design information, a power system network extracting means 112 which extracts a power system network composed of the power supply wiring and the RLC component of a power system in the integrated circuit, and a power system noise characteristic extracting means 113 which extracts the noise characteristic of the power system related to a power supply network. The device is also provided with an optimizing means 114 which arranges cells in the integrated circuit so that the power supply noise may become the optimum by using the noise characteristic of the power system and an automatic wiring means 115 which perform an automatic wiring process on the cell arrangement and generates and outputs mask pattern information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit design apparatus for designing a mask pattern for manufacturing an integrated circuit such as an ASIC, a circuit design method, and a computer-readable recording medium storing a circuit design program.
By designing a layout mask pattern that reduces EMI noise caused by the integrated circuit and power supply voltage drop inside the integrated circuit, the chip area of the integrated circuit is prevented from increasing,
The present invention relates to a technique for greatly reducing labor and time required for an integrated circuit manufacturing process.

[0002]

2. Description of the Related Art Generally, an ASIC (Application Specif
When a large number of circuit elements arranged in an integrated circuit such as an ic IC) are simultaneously switched, a large current instantaneously flows through the power supply wiring of the integrated circuit. When the current thus generated leaks from the power supply terminal of the integrated circuit to the power supply wiring outside the integrated circuit, electromagnetic waves are radiated around the power supply wiring as an antenna, and electromagnetic interference (ElectroMagnetic Interferenc) is generated.
e: EMI (hereinafter referred to as EMI) adversely affects the operation of other electronic devices as noise. Against this background, how to suppress the generation of EMI noise due to the power supply current of an integrated circuit has recently become one of the important issues in manufacturing an integrated circuit with high speed operation and high integration density. EM
In order to suppress the generation of I noise, a noise reduction RLC element such as a bypass capacitor (hereinafter referred to as "pass capacitor") or a resistor is inserted into the power supply system in the integrated circuit, and the power supply system is connected to the internal circuit for input / output. Measures have been taken to separate them for circuits.

On the other hand, the power supply wiring usually has a parasitic resistance, and a power supply voltage drop occurs when a current flows in the power supply wiring. However, a large current flows in the power supply wiring due to the high integration of the integrated circuit. In addition, since the allowable value of the power supply voltage drop has been reduced with the reduction in the voltage of the integrated circuit, the control of the noise related to the power supply voltage drop is now also performed by EMI.
Like noise control, it is one of the issues that cannot be ignored in manufacturing integrated circuits. For this reason, in order to reduce the noise related to the power supply voltage drop, for example, a method of inserting a decap in an integrated circuit to reinforce the power supply (Japanese Patent Application Laid-Open No. 10-242283) or a method of adding a power supply wiring (Japanese Patent Application Laid-Open No. 11-87518).

As described above, control of noise derived from a power supply system, such as EMI noise and noise related to a power supply voltage drop, is one of the tasks that are indispensable for manufacturing an integrated circuit with a high speed operation and a high integration density. It is one.

[0005]

However, the conventional integrated circuit manufacturing process aimed at controlling noise originating from the power supply system has the following technical problems to be solved.

First, since noise characteristics generally vary depending on the position of a power supply system, it is possible to control the generation of noise by considering the arrangement of cells that are noise sources. In the processing of (1), without considering the cell arrangement in the integrated circuit at all, take measures against noise that may be unnecessary if the cell arrangement is optimized, such as reinforcement of power supply wiring and insertion of decaps. As a result, the chip area of the integrated circuit is increased, which leads to an increase in costs required for manufacturing the integrated circuit.

Second, in the conventional processing, only one of EMI noise and power supply voltage drop can be controlled, and both EMI noise and power supply voltage drop control are simultaneously performed. A mask pattern in which both noises are controlled cannot be generated. For this reason, in the conventional processing, it is very difficult to efficiently control noise originating in the power supply system.

Third, in the conventional processing, in order to estimate the noise originating from the power supply system before arranging the cells in the integrated circuit and to design the circuit, actual cell arrangement is performed to manufacture an integrated circuit. Depending on the location, decaps may be insufficient or unnecessary decaps may be arranged, which is very inefficient.

Fourthly, conventional processing generally eliminates noise problem areas while sequentially executing automatic arrangement, power supply system analysis, and logic cell movement processing. In addition to requiring a great deal of effort and time to manufacture, these operations are performed by trial and error, which makes the entire integrated circuit manufacturing process very inefficient.

[0010] The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a circuit design apparatus that greatly reduces the labor and time required for manufacturing an integrated circuit.

It is another object of the present invention to provide a circuit design method which greatly reduces the labor and time required for manufacturing an integrated circuit.

Still another object of the present invention is to provide a computer-readable recording medium storing a circuit design program for greatly reducing the labor and time required for manufacturing an integrated circuit.

[0013]

In order to solve the above-mentioned technical problems, the present inventors have optimized a noise derived from a power supply system, such as EMI noise and power supply voltage drop, in a mask pattern designing stage. By performing the cell arrangement processing in the direction of the above, the increase of the chip area due to the insertion of the RLC element for noise reduction and the reinforcing power supply line can be minimized, and the labor and time required for the integrated circuit manufacturing processing can be greatly reduced. I came to the idea that I can do it.

A first feature of the present invention based on the above idea is that a power supply wiring in an integrated circuit is generated based on circuit design information in a circuit design apparatus for designing a mask pattern for manufacturing an integrated circuit. Power supply wiring generation means, power supply network extraction means for extracting a power supply network composed of power supply wiring and RLC components of the power supply system in the integrated circuit, and power supply system noise for extracting power supply system noise characteristics related to the power supply network Characteristic extracting means, optimizing processing means for arranging cells in an integrated circuit so that power supply system noise is optimized by using power supply system noise characteristics, and automatic wiring processing for the cell arrangements to obtain mask pattern information. Another object of the present invention is to provide a circuit design device including automatic wiring means for generating and outputting.

According to the above configuration, it is possible to manufacture an integrated circuit in which the noise derived from the power supply system is reduced, and to minimize the increase in the chip area due to the insertion of the noise reduction RLC element and the reinforcing power supply line. Thus, the labor and time required for the integrated circuit manufacturing process can be significantly reduced.

According to a second feature of the present invention, in a circuit design method for designing a mask pattern for manufacturing an integrated circuit, a power supply wiring generating step for generating a power supply wiring in the integrated circuit based on the circuit design information A power supply network extraction step for extracting a power supply network composed of power supply wiring and a power supply RLC component in the integrated circuit; and a power supply noise characteristic extraction step for extracting a power supply noise characteristic relating to the power supply network. An optimization processing step of arranging cells in an integrated circuit so as to optimize power supply system noise using power supply system noise characteristics, and performing automatic wiring processing on the cell arrangement to generate and output mask pattern information Another object of the present invention is to provide a circuit design method having an automatic wiring step.

According to the above configuration, it is possible to manufacture an integrated circuit in which noise derived from the power supply system is reduced, and to minimize the increase in chip area due to the insertion of RLC elements for noise reduction and reinforcing power supply lines. Thus, the labor and time required for the integrated circuit manufacturing process can be significantly reduced.

Further, a third feature of the present invention is that a computer readable recording medium storing a circuit design program for designing a mask pattern for manufacturing an integrated circuit, stores the program in the integrated circuit based on the circuit design information. A power supply line generation process for generating a power supply line, a power supply network extraction process for extracting a power supply network composed of power supply lines and a power supply RLC component in the integrated circuit, and a power supply system noise characteristic related to the power supply network. The power supply system noise characteristic extraction processing to be extracted, the optimization processing for arranging cells in the integrated circuit so that the power supply system is optimized using the power supply system noise characteristics, and the automatic wiring processing for the cell arrangement are performed. Automatic wiring processing for generating and outputting mask pattern information, and a circuit design program for causing a computer to execute these processings. Lies in a computer-readable recording medium storing.

According to the above configuration, it is possible to manufacture an integrated circuit in which the noise derived from the power supply system is reduced, and to minimize the increase in the chip area due to the insertion of the noise reduction RLC element and the reinforcing power supply line. Thus, the labor and time required for the integrated circuit manufacturing process can be significantly reduced.

Here, as the computer-readable recording medium, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, a magnetic tape, or the like is preferably used.

It is preferable to extract electromagnetic interference noise characteristics and power supply voltage drop noise characteristics as power supply system noise characteristics.

This makes it possible to manufacture an integrated circuit in which EMI noise and noise related to power supply voltage drop are reduced.

Further, it is preferable to determine an error in the cell capacity of the integrated circuit that has not been switched in the optimization processing, and to return to the power supply network extraction processing if the error exceeds an allowable value.

As a result, it is possible to suppress the extraction error of the power supply system noise characteristic to be constant, and to improve the accuracy of the optimization processing.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
A circuit design apparatus, a circuit design method, and a computer-readable recording medium storing a circuit design program according to an embodiment of the present invention will be described in detail.

First, the configuration of a circuit design apparatus according to an embodiment of the present invention will be described with reference to FIG.

Circuit design apparatus 11 according to an embodiment of the present invention
0 is generated by generating a mask pattern of a layout that optimizes noise derived from a power supply system (hereinafter, abbreviated as power supply system noise) such as EMI noise due to an integrated circuit and power supply voltage drop in the integrated circuit. In order to enable an integrated circuit to be manufactured immediately using a mask pattern, a circuit manufacturing system 100 is constructed in combination with a circuit manufacturing apparatus 150 such as an exposure apparatus, and power supply wiring for generating power supply wiring in the integrated circuit is provided. A generating unit 111, a power system network extracting unit 112 for extracting a power system network from the generated power wiring and a power system RLC component in the integrated circuit, and a noise characteristic extraction for extracting a power system noise characteristic from the extracted power system network Unit 113, an optimization process for arranging cells so that power supply system noise is optimized using the extracted power supply system noise characteristics 114, automatically includes the automatic wiring unit 115 to execute the wiring process among the cells based on the arranged cell arrangement information.

Here, the noise characteristic extraction unit 113
An EMI noise characteristic extracting unit 113a for extracting a noise characteristic relating to the I noise and a power supply voltage drop characteristic extracting unit 113b for extracting a noise characteristic relating to the power supply voltage drop. A cell placement processing unit 114a that executes processing, a cost calculation unit 114b that calculates the cost of the cell placement (definition will be described later) based on the cell placement result, and a cell capacity at the time of the cell placement ( A cell capacity calculation unit 114c that calculates the definition (to be described later), a determination unit 114d that controls whether to determine whether to re-execute the cell arrangement based on the calculated cost and the cell capacity (optimization processing), and satisfies the noise constraint. An analysis unit 114e for analyzing and correcting a defective portion in the integrated circuit, such as not being provided.

The circuit design apparatus 110 according to the embodiment of the present invention includes the circuit design apparatus 110 and the circuit manufacturing apparatus 1.
An input unit 130 for inputting various control parameters and input data according to 50, an output unit 140 for outputting various output information such as generated mask pattern information and error output, and cell switching in a circuit. It is connected to a cell switching library 160 that stores information.

Next, the processing procedure of the circuit design processing according to the embodiment of the present invention will be described with reference to FIG.

When performing a circuit design process by the circuit design method according to the embodiment of the present invention, the following processing steps are executed.

(1) Circuit design information necessary for generating a mask pattern, such as function information and structure information of a circuit to be designed, is input into the circuit design apparatus 110 via the input unit 130 (design information input step, S201). ).

(2) The power supply wiring generation section 111 generates a power supply wiring in the integrated circuit based on the input circuit design information (power supply wiring generation step, S202). Here, if it is known in advance that a noise reducing RLC element such as a decap, a power supply resistor, and an inductor is required in the integrated circuit, the noise reducing RLC element is laid together with the power supply wiring in advance. It is good to do.

(3) After the power supply system network extraction unit 112 derives the RLC component parasitic on the power supply system, the power supply network extracted from the power supply wiring, the noise reduction RLC element, and the RLC component parasitic on the power supply system is extracted. Extract (power system network extraction step, S203).
Here, in the circuit design processing according to the embodiment of the present invention, the power supply network is extracted in consideration of the RLC component parasitic on the power supply system. Among the parasitic RLC components,
In particular, it is preferable to accurately extract the capacitance between the power supply and the ground. In the circuit design processing according to the embodiment of the present invention, the capacity between the power supply and the ground is
Although the capacitance of the decaps, the capacitance of the power supply wiring, the capacitance of the well, and the cell capacitance that has not been switched are extracted, switching is performed because the previous cell arrangement information does not exist, as in the first cell arrangement processing. If it is not possible to extract the cell capacity that has not been switched, the total value of the cell capacity that has not been switched in the integrated circuit is obtained, the total value of the cell capacity is evenly distributed in the integrated circuit, and the value is switched. It is desirable to use as no cell capacity.

(4) In the noise characteristic extracting unit 113,
Power system noise characteristics (= noise transfer characteristics, frequency response Hij (jw) and impulse response hij related to EMI noise and power supply voltage drop) related to the extracted power system network
(T), a calculation method will be described later) (power system noise characteristic extraction step, S204).

(5) The optimization processing unit 114 arranges cells in the integrated circuit so as to optimize the power supply system noise using the extracted noise characteristics (optimization processing step, S205).

(6) The determining unit 114d determines whether or not the power supply system noise generated by the cell arrangement processing satisfies the noise constraint (noise constraint violation determining step,
S206). As a result of the determination, if the noise limit is not satisfied (power wiring correction step, S207), and if the noise restriction is satisfied (automatic wiring step, S20).
Go to 8).

(7) In the analysis section 114e, processing such as correction of power supply wiring and insertion of RLC elements for noise reduction is performed on a circuit area that does not satisfy the noise constraint. After the correction, the power supply network extraction step S203 The subsequent processing is executed again (power wiring correction step, S20
7).

(8) The automatic wiring unit 115 performs an automatic wiring process on the cell arrangement to generate and output mask pattern information (automatic wiring step, S208).

Here, in the power supply system noise characteristic extraction step in the circuit design processing according to the embodiment of the present invention, EM
I noise characteristics and noise characteristics related to power supply voltage drop (=
To extract the transfer characteristic), the frequency response Hij (j
w) and the impulse response hij (t) are calculated. Any method may be used as long as the respective noise characteristics can be obtained, and only EMI noise and noise related to power supply voltage drop are used as power supply noise characteristics. However, other power supply system noise characteristics such as noise related to electron migration (ElectroMigration) may be extracted and considered. That is, the circuit design processing of the present invention is characterized by optimizing power supply noise by cell arrangement using power supply noise characteristics. It may be extracted with.

Next, the details of the optimization processing step S205 will be described with reference to FIG. The optimization processing step according to the embodiment of the present invention is performed by the following sub-steps.

(5-1) The cells arranged in the integrated circuit are moved (cell moving step, S401).

(5-2) The cost related to the new cell arrangement obtained as a result of the cell movement step is calculated (cost calculation step, S402). Here, the definition of “cost” used in the circuit design processing according to the embodiment of the present invention will be described. The “cost” is one of optimization parameters for optimal mask pattern design as seen in the conventional circuit design processing, and the total wiring length estimated from the cell arrangement is used. That is, when the cost is defined as the total wiring length, cells are optimally arranged in a direction in which the cost decreases (= the total wiring length decreases), and a mask pattern is designed. This time, the “cost” used in the circuit design processing according to the embodiment of the present invention refers to the “cost”
However, the optimization parameters take into account the cost of EMI noise and noise related to power supply voltage drop in addition to the conditions of the conventional total wiring length and the like.
This makes it possible to optimize I noise and noise related to power supply voltage drop. Here, the definition of “cost” regarding EMI noise and noise related to power supply voltage drop will be described in more detail.

First, the definition of the cost related to the EMI noise will be described.

Now, the noise constraint on the EMI noise is as follows:
Assuming that the current spectrum intensity Imax (ω) of the power supply terminal allowed at the frequency ω is given as shown in FIG.
_EMI is the power supply current spectrum I 'at each power supply terminal.
By comparing the magnitude of _j (jω) with the magnitude of the current spectrum intensity Imax (ω), it is defined as (Equation 1).

[0046]

(Equation 1) Here, w _jn is a weight coefficient for considering the noise constraint, and is defined as ( _Equation 2).

[0047]

(Equation 2) α is a value larger than 1 of about 100 to 1000.

Thus, the noise constraint violation (I ′ _j (j
ω)> Imax (ω)), the value of the cost C _EMI related to EMI noise becomes very large.
By arranging cells in a direction to reduce C _EMI , E
The optimum cell arrangement with reduced MI noise can be easily generated, and the labor and time required for manufacturing an integrated circuit can be significantly reduced.

Here, a method of calculating the power supply current spectrum I ′ _j (jω) at the power supply terminal j will be described. In the circuit design processing according to the embodiment of the present invention, when calculating the power supply current spectrum I ′ _j (jω), first, the circuit region is divided into a plurality of regions having appropriate sizes as shown in FIG. divided into i, after extracting the power supply current waveform i _i for each region i (t), the power supply current waveform i _i (t) is Fourier transformed by a technique such as fast Fourier transform power current spectrum I _i (jω) Ask for. After that, since the power supply network is a linear circuit including only the RLC element, it is assumed that the principle of superposition of currents in each region i holds, and the power supply current spectrum I _i (jω) and the frequency response equation H shown in (Equation 3) _{From ij} (jω) (= calculated in the power supply noise characteristic extraction step), a power supply current spectrum I ′ _j (jω) at the power supply terminal j shown in (Equation 4) is extracted.

[0050]

(Equation 3)

(Equation 4) Here, the expression of the frequency response H _ij (jω) shown in (Equation 3) is obtained when the power supply current I _i in the region _i is input and the power supply current I ′ _j in the power supply terminal _j is output. It is determined for each combination of the region i and the power supply terminal j in the system network. Therefore, when there are m divided circuit regions and n power terminals of the integrated circuit,
M × n frequency responses described by (Expression 3) are obtained.

As described above, in the circuit design processing according to the embodiment of the present invention, the power supply current waveform i _i (t) of each divided circuit region and the frequency response H described by (Equation 3) are used.
The power supply current spectrum I ′ _j (jω) at each power supply terminal j is calculated from _ij (jω).

The power supply current spectrum I ′ _j (jω)
Power supply current waveform i _i (t) used in calculating the may determined by the following method. That is, first, after generating a switching waveform in each cell from the cell switching library 160, based on the cell switching event information, by combining the switching current waveform of the cell at the time when the switching event of the cell occurs, The power supply current waveform i _i (t) in the region is obtained. Here, it is assumed that the current waveform flowing when the cell is switched is stored in the cell switching library 160. In addition, since the switching waveform changes depending on the input slew and the output load, the current waveform for some combination of the typical values of the input slew and the output load is stored, and the intermediate input slew and the output load value are stored. On the other hand, each current waveform is obtained by interpolation processing or the like. Note that information on the wiring capacity is required to obtain the input through and output load, but there is no information on the wiring at the time of the placement processing. Therefore, the wiring capacity is estimated by estimating the approximate wiring length from the cell placement information. It is better to ask for Further, the cell switching event information may be obtained by processing such as logic simulation.

Next, the definition of the cost related to the power supply voltage drop will be described.

The cost C _vdrop relating to the power supply voltage drop is:
The power supply voltage drop value vdrop _j in each region _j is calculated from the peak value of the power supply voltage waveform v _j (t), and the power supply voltage drop value vdrop _j and the power supply voltage drop allowable value vdrop_
By comparing the magnitudes of max, they are defined as (Equation 5).

[0055]

(Equation 5) Here, w _j is a weight coefficient for considering the noise constraint, and is defined as (Equation 6).

[0056]

(Equation 6) α is a value larger than 1 such as about 100 to 1000.

As a result, there is a noise constraint violation (vd
In the case of (rop _j > vdrop_max), the value of the cost cost C _vdrop relating to the power supply voltage drop becomes very large. _Therefore , the cells are arranged in a direction to reduce the cost C _vdrop, thereby reducing the influence of the power supply voltage drop. An optimal cell arrangement can be easily generated, and the labor and time required for integrated circuit manufacturing can be significantly reduced.

Here, a method of calculating the power supply voltage waveform v _j (t) in each circuit region j will be described. In the circuit design processing according to the embodiment of the present invention, when calculating the power supply voltage waveform v _j (t) in each circuit region j, first,
The inside of the chip is divided into a plurality of regions of an appropriate size, and the power supply current waveform i _i (t) of each region i is Fourier-transformed to obtain a power supply current spectrum I _i (jω).
As in the case of extracting the I noise characteristic, the power supply voltage spectrum V _j (j
ω) is calculated, and the calculated power supply voltage spectrum V _j (j
ω) is subjected to an inverse Fourier transform using a fast inverse Fourier transform technique or the like, so that the power supply voltage waveform v _j (t)
Is extracted.

[0059]

(Equation 7)

(Equation 8) Here, the frequency response H _ij (jω) (= calculated in the power supply system noise characteristic extraction step) shown in (Equation 7) is the region i
Input supply current I _i in are those of when the output power supply voltage V _j in the region j, and request for each combination of region i and region j of the power supply system in the network. Therefore, when there are m divided circuit regions and n power terminals of the integrated circuit, m × n frequency responses described by (Equation 7) are obtained.

As described above, in the circuit design processing according to the embodiment of the present invention, the power supply current waveform i _i (t) of each divided circuit region and the frequency response H described by (Equation 7)
_ij (jω), the power supply voltage waveform v in each circuit region j
_j (t) shall be extracted.

The power supply voltage waveform v _j (t) in each circuit region j may be extracted as follows. That is,
First, the transfer function H when the power supply current Ii in the region _i is input and the power supply voltage Vj in the region _j is output
_ij (s) is calculated for each combination of the region i and the region j using (Equation 9), and the calculated transfer function H _ij (s)
Is subjected to an inverse Labrath transform as shown in (Equation 10) to obtain an impulse response h _ij (t). When there are m regions, m × m impulse responses are obtained.

[0062]

(Equation 9)

(Equation 10) Subsequently, the impulse response h calculated by (Equation 10)
_ij (t) and the power supply current waveform i _i (t) in the region i are introduced into (Equation 11), whereby the power supply voltage waveform v
_j (t) is extracted.

[0063]

[Equation 11] Here, h _ij (t) * i _i (t) in ( _Equation 10)
Denotes the convolution integral described by (Equation 12).

[0064]

(Equation 12) (5-3) It is determined whether the calculated cost decreases before and after the cell movement (cost determination step, S40)
3). As a result of the determination, if the cost is reduced, the process proceeds to (cell arrangement determining step, S404), and if not, the process proceeds to (end condition determining step, S405).

(5-4) The cell arrangement information after the cell movement step S401 is determined and stored (cell arrangement determination step, S404).

(5-5) It is determined whether or not an end condition is satisfied, such as whether or not the total cost in consideration of the total wiring length and power supply noise is equal to or less than a predetermined value (end condition determination). Step, S405). As a result of the discrimination, if the condition is satisfied, the optimization process is completed. If the condition is not satisfied, the processes after (cell movement step, S401) are executed again.

As described above, in the circuit design processing according to the embodiment of the present invention, the cell arrangement processing is performed in a direction to optimize the power supply system noise, and a mask pattern required for circuit manufacture is generated. Circuit manufacturing with reduced system noise becomes easier, and correction processing such as correction of power supply wiring and insertion of RLC elements for noise reduction can be minimized, greatly reducing the labor and time required for circuit manufacturing. It can be reduced.

As a modification of the above-described optimization processing step, as shown in FIG. 5, a cell capacity error determination step S505 may be added to one of the optimization processing steps.
That is, the total value of the unswitched cell capacity of each area when the power supply network is extracted is represented by Cce
ll _i , and the total value of the cell capacity that has not been switched in each area i after the cell moving step S501 is Ccell ′
_i , the error tolerance of the non-switched cell capacitance is Δ
In order to determine whether or not the cell capacity that has not been switched is equal to or less than the allowable value, it is determined whether or not the following conditional expression is satisfied in all the circuit areas i in the cell capacity error determination step S505.

(Conditional expression) | Cell _i −Cell ′ _i | ≦ ΔCell_max and | Cell _i −Cell ′ _i |> ΔCell
If there is a circuit area of l_max, the power supply network extraction step S is performed again in order to extract the power supply network using a more accurate cell capacity value.
The process returns to step 203, and if not, the process returns to the end condition determination step S506 similar to the process illustrated in FIG. As a result, while maintaining the accuracy of the power system noise characteristics,
Cell placement processing can be executed in a direction that optimizes power supply system noise.

Finally, the circuit design system 100 of the present invention
Has, for example, an appearance like the configuration shown in FIG. That is, the circuit design device 110 according to the embodiment of the present invention is configured by incorporating each element of the circuit design device 110 in the computer system 80. The computer system 80 includes a floppy disk drive 81 and an optical disk drive 83. Then, by inserting the floppy disk 82 into the floppy disk drive 81 and the optical disk 84 into the optical disk drive 83 and performing a predetermined read operation,
The manufacturing process control programs stored in these recording media can be installed in the system. Further, by connecting a predetermined drive device, for example, installation and reading / writing of data can be executed using a ROM 85 serving as a memory device and a cartridge 86 serving as a magnetic tape device.

Further, the circuit design apparatus 110 of the present invention
It may be programmed and stored in a computer-readable recording medium. When the process is evaluated, the recording medium is read into a computer system, the program is stored in a storage unit such as a memory in the computer system, and the circuit design program is executed by an arithmetic unit. A design device and a method thereof can be realized. Here, the recording medium includes, for example, a computer-readable medium capable of recording a program such as a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape.

As described above, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention must be limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0073]

As described above, according to the circuit designing apparatus of the present invention, the cell arrangement processing is performed in a direction for optimizing power supply system noise such as EMI noise and noise related to power supply voltage drop. In addition, it is possible to manufacture integrated circuits that reduce the occurrence of power supply system noise, minimize the increase in chip area due to the insertion of RLC elements for noise reduction and reinforcing power supply lines, and significantly increase the labor and time required for circuit manufacture. It is possible to achieve a reduction.

According to the circuit design method of the present invention,
Executing the cell arrangement processing in a direction that optimizes power supply noise such as MI noise and noise related to power supply voltage drop makes it possible to manufacture an integrated circuit with reduced power supply noise generation. The increase in the chip area due to the insertion of the RLC element and the reinforcing power supply line can be minimized, and the labor and time required for circuit manufacture can be significantly reduced.

Further, according to the computer-readable recording medium storing the circuit design program of the present invention,
Executing the cell arrangement processing in a direction that optimizes power supply noise such as MI noise and noise related to power supply voltage drop makes it possible to manufacture an integrated circuit with reduced power supply noise generation. The increase in the chip area due to the insertion of the RLC element and the reinforcing power supply line can be minimized, and the labor and time required for circuit manufacture can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a circuit design device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a circuit design method according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an optimization process according to the embodiment of the present invention.

FIG. 4 is a flowchart illustrating an application example of the optimization processing according to the embodiment of the present invention.

FIG. 5 is a diagram for explaining a method of extracting EMI noise characteristics and noise characteristics related to power supply voltage drop.

FIG. 6 is a diagram for explaining a method for calculating a cost related to EMI noise.

FIG. 7 is a diagram illustrating an overview of a circuit design apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 80 computer system 81 floppy drive 82 floppy disk 83 optical disk drive 84 optical disk 85 ROM 86 cartridge 100 circuit manufacturing system 110 circuit design device 111 power supply wiring generation unit 112 power supply system network extraction unit 113 noise characteristic extraction unit 113a EMI noise characteristic extraction unit 113b power supply Voltage drop characteristic extraction unit 114 Optimization processing unit 114a Cell position processing unit 114b Cost calculation unit 114c Cell capacity calculation unit 114d Judgment unit 114e Analysis unit 115 Automatic wiring unit 130 Input unit 140 Output unit 150 Integrated circuit manufacturing device 160 Cell switching library

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 15/60 666V H01L 21/82 C

Claims (9)

[Claims] 1. A circuit design apparatus for designing a mask pattern for manufacturing an integrated circuit, comprising: power supply wiring generation means for generating power supply wiring in an integrated circuit based on circuit design information; Power supply network extraction means for extracting a power supply network composed of RLC components of the power supply system, power supply noise characteristic extraction means for extracting a power supply noise characteristic relating to the power supply network, Optimization processing means for arranging cells in an integrated circuit so that power supply system noise is optimized by using the automatic wiring means for performing automatic wiring processing on the cell arrangement to generate and output mask pattern information. A circuit design apparatus comprising: 2. The circuit design apparatus according to claim 1, wherein an electromagnetic interference noise characteristic and / or a noise characteristic relating to a power supply voltage drop are extracted as the power supply system noise characteristic. 3. The optimization processing means according to claim 1, further comprising a cell capacity error determination means for determining an error of a non-switched cell capacity in the integrated circuit. Circuit design equipment. 4. A circuit design method for designing a mask pattern for manufacturing an integrated circuit, comprising: a power supply wiring generation step of generating a power supply wiring in an integrated circuit based on circuit design information; A power system network extracting step of extracting a power system network composed of RLC components of the power system, a power system noise characteristic extracting step of extracting a power system noise characteristic of the power system network, An optimization processing step of arranging cells in an integrated circuit so that power supply system noise is optimized by using an automatic wiring step of performing automatic wiring processing on the cell arrangement to generate and output mask pattern information. A circuit design method comprising: 5. The circuit design method according to claim 4, wherein an electromagnetic interference noise characteristic and / or a noise characteristic relating to a power supply voltage drop are extracted as the power supply system noise characteristic. 6. The cell processing method according to claim 4, wherein the optimization processing step includes a cell capacitance error determining step of determining an error of a cell capacitance that is not switched in the integrated circuit. Circuit design method. 7. A power supply line generating process for generating a power supply line in an integrated circuit based on circuit design information in a computer-readable recording medium storing a circuit design program for designing a mask pattern for manufacturing an integrated circuit. Power supply network extraction processing for extracting a power supply network composed of power supply wiring and RLC components of a power supply in an integrated circuit; and power supply noise characteristic extraction for extracting a power supply noise characteristic related to the power supply network. Processing, optimization processing for arranging cells in an integrated circuit so that power supply system noise is optimized using the power supply system noise characteristics, and automatic wiring processing for the cell arrangement to generate mask pattern information A circuit design characterized by having automatic wiring processing for outputting and causing a computer to execute these processings Computer readable recording medium storing programs. 8. A computer-readable recording storing a circuit design program according to claim 7, wherein an electromagnetic interference noise characteristic and / or a noise characteristic relating to a power supply voltage drop are extracted as the power supply system noise characteristic. Medium. 9. The method according to claim 7, wherein the optimizing process includes a cell capacity error discriminating process for discriminating an error of a non-switched cell capacity in the integrated circuit, and causes the computer to execute this process. A computer-readable recording medium storing the circuit design program according to claim 8.