JP2001086237A - Device and method for measuring loop impedance for subscriber loop impedance circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure subscriber loop impedance in the inside by generating first and second currents proportional to sensed loop voltage and loop currents and generating a third current by adding second current to the first current. SOLUTION: A loop voltage sensing circuit 20 measures the voltage between subscriber lines. This voltage is scaled by a scaling circuit 14 and passed through a resistor 18 to yield the first current. A loop current sensing circuit 10 measures the voltage applied to a resistor. This voltage is passed through a resistor 16, lead to a first current mirror 24 and scaled to yield the second current. A second current mirror 26 gives the first current to a third current mirror 28. The third current mirror 28 generates the reproductions of the first current on two lines. One of the reproductions of the first current is added to the second current to yield the third current. A fourth current mirror 30 generates reproduction of the third current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a subscriber loop interface circuit, and more particularly, to a method and apparatus for measuring loop impedance in a subscriber loop interface.

[0002]

2. Description of the Related Art A subscriber loop interface circuit ("S
LIC ") is commonly used as an interface between a subscriber network and a subscriber terminal (such as a home telephone). SLIC is a two-wire to four-wire converter, battery supply, line. Monitoring, or common mode exclusion.

[0003] A subscriber loop has a SLIC, a subscriber terminal (eg, a telephone), and a pair of subscriber lines connecting the SLIC to the subscriber terminal. When the subscriber terminal is off-hook, the subscriber line, subscriber terminal, and SLIC together form a continuous circuit to establish two-way communication between the SLIC and the subscriber terminal. May be.

[0004] The SLIC includes circuitry for obtaining information about the voltage level across the subscriber line (loop voltage) and about the current flowing through the subscriber loop (loop current). Generally, the information obtained is scaled and compared to a reference to evaluate loop voltage and / or loop current.

[0005] SLICs can detect off-hook conditions using loop voltage and / or loop current. For example, when the loop current and / or loop voltage reaches a predetermined threshold, the SLIC may be used to indicate the detection of an off-hook condition.
May send a logic signal to the SLIC controller. Further, by way of example, information about loop current and loop voltage can be used to control the power supply to the subscriber loop by the SLIC.

[0006] Measurement loop impedance and test subscriber loop continuity require invasive subscriber loop access relays and expensive test equipment.

In a known technique for measuring the subscriber loop voltage, the voltage across a pair of subscriber lines is measured and converted to a single narrow pulse indicative of the magnitude of the voltage. This technique is
Variations in capacitance values and manufacturing intersections can be inaccurate and require high frequency clocks to provide the required measurement resolution.

[0008]

Accordingly, the present invention provides a method and apparatus for measuring subscriber loop impedance, and a method and apparatus for internally measuring subscriber loop impedance in a semiconductor SLIC circuit. With the goal.

Another object of the present invention is to provide a method and apparatus for testing the continuity of a subscriber loop in an SLIC formed from semiconductor material.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a semiconductor circuit which is a subscriber loop interface circuit, the subscriber loop interface circuit comprising: a loop voltage sensor for sensing a loop voltage; A first current generator for generating a first current proportional to a voltage, a loop current sensor for detecting a loop current, and a second current for generating a second current proportional to the sensed loop current A generator; means for adding the second current to the first current to generate a third current; determining a loop impedance from the first current and the third current; And a loop impedance measuring device.

The present invention further includes a method for determining loop impedance, the method comprising: sensing a loop voltage; generating a first current proportional to the sensed loop voltage; Directing the first current through the capacitor to charge the capacitor, and sensing a loop current, the method comprising: determining a loop impedance that is proportional to the sensed loop current. And adding the second current to the first current to generate a third current greater than the first current and having a reverse polarity;
Directing the third current to the capacitor to discharge the capacitor, determining a discharge time of the capacitor, and determining a loop impedance as a function of the discharge time. I do.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS The invention is illustrated by way of example with reference to the accompanying drawings, in which: FIG.

FIG. 1 shows a circuit for measuring the SLIC, ie, the subscriber loop impedance, which comprises a loop current sensing circuit 10 and a loop voltage sensing circuit 2.
0, the scale circuit 14, and the four resistance elements 16, 1
8, 22, and 40; a first current mirror 24; a second current mirror 26; a third current mirror 28;
Current mirror 30, comparator 32, and capacitor 34
, Control switch 36, ringing trip detector 38
And

[0014] Conventional SLICs operate from a negative reference. FIG. 1 shows a circuit in an SLIC operating from a negative reference.

In operation, the loop voltage sensing circuit 20 transmits information about the loop voltage to a pair of subscriber lines (eg, a TIP).
And RING). Loop voltage sensing circuit 20 may generate a voltage that is proportional to the voltage between the subscriber lines. The voltage may be scaled (N to 1) by scale circuit 14. The scaled voltage may pass through a resistive element 18 having a resistance of R1 'ohms to provide a first current Iv.

The loop current sensing circuit 10 can obtain information about the loop current by measuring the voltage applied to the resistance element 40. The resistance element 40 may be a predetermined value resistor arranged in series with one of the subscriber lines (for example, TIP or RING). Loop current circuit 10
Produces a voltage that is proportional to the measured loop current.
The generated voltage passes through the resistance element 16 and is guided to the first current mirror 24. The first current mirror 24 may implement a scale of K1 to 1 to provide a second current Ii.

The loop voltage circuit measurement and the loop current circuit measurement can change in proportion to the temperature change of the on-chip type device and the lot-to-lot change, respectively. It can be chosen to ensure that the changes in the measurements follow each other.

The first current Iv is applied to the second current mirror 28
Can be given to The second current mirror 26 may provide a first current Iv to a third current mirror 28. The third current mirror 28 may generate two signals on separate lines, each of which is a reproduction of the first current Iv. One of the reproductions of the first current Iv to give a third current may be added to the second current Ii. This addition of the first current and the second current to provide a third current may be realized by a node connection. The fourth current mirror 30 may generate a third current reproduction.

The control switch 36 can have three states. In the first state, the control switch 36 may connect the capacitor 34 to the third current mirror 28, which directs the first current Iv to the capacitor. In the second state, switch 36 may connect capacitor 34 to a fourth current mirror. The fourth current mirror 30 outputs a third current (Iv + I
Generate i). In the third state, the control switch 36
May connect a capacitor to a fixed reference voltage, such as ground 42.

While control switch 36 is in the first state, capacitor 34 is charged. While switch 36 is in the second state, capacitor 34 is discharged. While switch 36 is in the third state, capacitor 34 is clamped to a predetermined level, such as ground.

The state of the switch 36 is determined by the timing signal T
1, can be activated using T2 and T3. Ringing trip detector 38 uses a square wave signal in combination with the output signal of comparator 32 to provide timing signal T
1, T2 and T3 may be generated. The operation of the ringing trip detector is described further below.

During the first half cycle of the square wave signal, a timing signal T1 is generated to activate the first state of the switch so that the capacitor can be charged as a source of current. During the second half cycle, a current timing signal T2 is generated to activate the second state of the switch so that the capacitor can be discharged as a sink to reduce current.

As long as the measured loop current is not zero, the discharge period will always be shorter than the charge cycle. To ensure that the loop current is not zero, charging and discharging of the capacitor 34 may be performed when a subscriber off-hook condition is detected by the SLIC.

During the remainder of the second half cycle of the square wave signal, and after the capacitor 34 is fully discharged or discharged to a predetermined level, the voltage on the capacitor is maintained at a reference potential, such as ground. A timing signal T3 may be generated to activate a third state of the switch. The comparator 32 converts the voltage applied to the capacitor 34 into a resistor R
Compare with the reference voltage applied to ref22. If the voltage applied to capacitor 34 is higher than the reference voltage, the comparator may generate a high output signal. If the voltage applied to capacitor 34 is less than or equal to the reference voltage, the comparator may generate a low output signal. The reference voltage applied to the resistor Rref22 can be changed. The reference voltage applied to Rref 22 may be varied using control switch 36 to direct a reference current from ringing trip detector 38 to resistor Rref22. The reference voltage may be set to zero by deactivating control switch 36 and preventing reference current from flowing to resistor Rref22. The reference current is connected to the resistor Rref
Switching to 22 may be a function of the control switch 36 other than the three states described above.

The timing signal T1 has a predetermined length. While T1 is generated, the capacitor 34 can be charged (the first state of the switch) and the control switch 36 directs a reference current to the resistor Rref22. The magnitude of the reference current is such that the voltage applied to the capacitor is always lower than the voltage applied to resistor Rref. Maintaining the reference voltage at a higher level than the voltage applied to the capacitor causes the comparator 32 to generate a higher output signal during the timing signal T1.

At the end of the duration of T1, a timing signal T2 is generated. The duration of T2 is not predetermined. During the duration of the T2 signal, the reference voltage may be set to zero (eg, deactivate the switch to prevent reference current from flowing further through resistor Rref22). Further, during the duration of the T2 signal, the capacitor is discharged (control switch 36 conducts a third current [Ii + Iv] to the capacitor). When the capacitor 34 is discharged, the output signal of the comparator 32 is a low signal. When the capacitor is discharged to a predetermined level of the reference voltage, such as zero, the output signal of comparator 32 transitions to a high signal. The high output signal of comparator 32 may be provided to ringing trip detector 38. In response, ringing trip detector 38 activates the third state of the switch, clamping the capacitor to a predetermined voltage level (eg, shorting capacitor 34 by grounding capacitor 34). A timing signal T3 may be generated.

Capacitor 34 is clamped during timing signal T3 because current leakage during T3 triggers the comparator and results in an invalid measurement. Further, the ability to clamp capacitor 34 is convenient in other unringed and untested conditions. Capacitor 34 can be used in a ringing trip function when not used for line impedance measurement.

During the timing signal T3, the output signal of the comparator 32 indicates that the voltage applied to the capacitor 34 is a resistor Rr
It remains high because it is below the voltage applied to ef22.

The time interval between changes in the output signal level of the comparator can be measured using a counting technique, where the output of the comparator gates a high frequency clock signal to a counter. The time interval of the timing signal T2 is an interval of interest. During the time interval for T2, the output of comparator 32 is low. To measure the duration of the interval, the output of comparator 32 may be received by NAND gate 46, which reverses the received signal to provide a high output signal. The high output signal obtained from NAND gate 46 may be directed to an N-bit binary counter 48 controlled by the gate with a high frequency clock signal. Using the high frequency clock signal, N-bit counter 58 counts the duration of the high output signal from NAND gate 46 (time interval of T2).

This count can be used as an address pointer to identify a location in memory (N ²ⁿ XM bits) 50. Each location in the memory 50 may store a predetermined loop impedance value corresponding to the duration of the timing signal T2 as measured by the N-bit counter 48.

Referring to FIGS. 1 and 2, a square wave signal 52 having a one-to-one mark-to-space ratio (eg, assuming that the first half of square wave signal 52 is the duration of timing signal T1). May be used to define the duration of the timing signal T1. The last part of the first half of the square wave signal 52 can be used to initialize the timing signal T2 and set the comparator output signal 54 to a low signal. As described above, the output signal 54 of the comparator is set low by setting the voltage applied to the resistor Rref22 to a predetermined level (for example, zero volt) equal to or lower than the voltage applied to the capacitor 34. When the capacitor 34 is discharged to a predetermined level, the output signal 54 of the comparator goes high. The transition to a high signal is determined by the timing signal T
3, which is received by the ringing trip detector 38. Timing signal T3 lasts for the remainder of the second half duration of square wave signal 52. The charge and discharge cycle is repeated again in the first part of the first half of the square wave signal.

[0032] Ringing trip detector 38 may receive a control signal to control the state of the ringing trip detector. For example, the control signal may instruct the ringing trip detector to perform a ringing detection function or an impedance measurement function.

Referring to FIG. 3, trip detector 38 includes:
A pair of terminals, a switch 74, a current adder 76, a current mirror 78, a zero-crossing comparator 80, a ringing trip comparator 82, a capacitor 84, and a combinational logic circuit 8.
6. The circuit outside the ringing trip detector 38 includes a ringing relay switch 88, a ringing signal supplier 90, and three resistors 92, 94, and 96.

In operation, the ringing supply generates a periodic signal which is routed to three resistors 92, 94 and 96. When the ringing relay switch 88 is closed, a signal is directed to the subscriber terminal (not shown) to ring the subscriber terminal. Ringing relay switch 8
Loop impedance measurements are made while 8 is disconnected. When the ringing relay switch 88 is disconnected, a ringing supply 90 and three resistors 92, 94, and
The entire signal generated by 96 is directed through terminal 72 to ringing trip detector 38. The current (I1 or I2) passing through each terminal is supplied to the ringing relay switch 88.
Are generally equal, or generally equal, unless connected. Currents I1 and I2 correspond to the ringing shown in FIG.

With further reference to FIG. 3, switch 74 may be activated in the loop impedance measurement state of ringing trip detector 38. During the loop impedance measurement state, the switch 74 may be connected to a reference value, such as ground, to imbalance the currents I1 and I2. Currents I1 and I2 may be received by current adder 76 to generate output current I2-I1. Generally, when the ringing trip detector is not in the loop impedance measurement state, the output current of the current adder 76 will be (I2 and I1
Are approximately equal). During the loop impedance measurement state, the switch imbalances I2 and I1 so that the output of current adder 76 is similar to the periodic signal generated by ringing supply 90.

In the loop impedance measurement state,
The mirror produces a mirror of the current signal I2-I1. I2
The -I1 mirror signal may be directed to a zero crossing comparator 80. Zero crossing comparator 80 may compare the mirror signal to a constant current reference. For example, a zero-crossing comparator can be used to control the mirror signal I
The mirror signal I2-I1 may be compared to a zero reference to detect when 2-I1 crosses zero.

The zero-crossing comparator 80 is connected to the ringing supply 9
A square wave signal (one-to-one mark-to-space ratio) may be generated as a function of the zero periodic signal. The output of zero-crossing comparator 80 may transition between two states in detecting the respective zero-crossings of mirror signals I2-I1. The periodic transition may generate a square wave signal (see FIG. 2) to generate timing signals T1, T2, and T3.

The square wave signal generated by zero crossing comparator 80 may be directed to combinational logic unit 86. The output of combinational logic unit 86 may be timing signals T1, T2, and T3. The timing signals T1, T2, and T3 may be provided to a control switch (see FIG. 1, control switch 36). Combinational logic signal unit 86 may generate timing signal T1 during the first half of the square wave signal. In the last portion of the first half of the square wave signal, combinational logic unit 86 may generate timing signal T2. In response to the transition of the output signal of the comparator, the combinational logic unit 86 operates at timing T2.
To terminate and generate a timing signal T3 for the remainder of the second half of the square wave signal. In the last part of the second half of the square wave signal, the cycle repeats again. The timing signals T1, T2, and T3 may be placed only on a single line led to the control switch.

Generally, the ringing trip comparator 8
2 and the capacitor are part of the ringing trip detector. Ringing trip comparator 82 and capacitor 8
4 is used to detect the state of the subscriber who is off-hook while the ringing relay switch 88 is connected.

The capacitor 84 can have one or more functions. The capacitor 84 is used to perform a ringing trip detection function, and may be a capacitor (eg, the capacitor 34 of FIG. 1) that is charged and discharged to perform a loop impedance measurement function.

Using the contents of a counter (eg, the N-bit binary counter of FIG. 1), the subscriber loop impedance can be determined by solving a charge conservation law equation for the capacitor. In the following description, symbols T, T
1, T2, and T3 should be understood as indicating the duration of time. Therefore, in the following description, T1 is the duration of the timing signal T1, and T2 is the timing signal T
2, T3 indicates the duration of the timing signal T3. The formula for the law of conservation of charge for a capacitor is

[0042]

(Equation 1) It is.

By equalizing the charge during charging and discharging of the capacitor,

[0044]

(Equation 2) Where Iv is the first current, Ii is the second current, T1 is the charging time, T2 is the discharging time, and C is the capacitance of the capacitor 34. Equation (2) is

[0045]

(Equation 3) Can be simplified as Equation (3) is

[0046]

(Equation 4) At this time, T3 is a period during which the capacitor is clamped (that is, T1-T2) and is maintained at a constant voltage.

Information on loop impedance "Rl
oop "can be obtained from the ratio in equation (4). If T2 is equal to zero, then Iv is zero and Rloop is also zero.
If T3 is equal to zero, Ii is zero and Rloop is infinite. To avoid zeroing the Ii value, an impedance measurement may be performed when an off-hook condition is detected.

In obtaining impedance measurements, as T2 increases, T3 becomes very small and the resolution becomes very coarse. It is preferable that the time interval T2 is suppressed so as not to exceed 80% of a half cycle of the square wave signal.
For example, when T2 is measured as four times T3, T2 may be defined as four times T3 or less so that the loop impedance may be considered to be a maximum (eg, 2000 ohms). Many loop impedance values are between zero and 20.
It is in the range of 00 ohms.

The first current Iv is equal to the loop voltage “Vloop”
p ″ may be equal to the value obtained by dividing (N ^* R1 ′).
The second current Ii is obtained by setting the loop current “Iloop” to K1.
(The scaling factor in the first current mirror). By subtracting Iv and Ii from equation (4) using their scale equations,

[0050]

(Equation 5) Is given.

By subtracting T2 by 4 ^* T3,

[0052]

(Equation 6) Is obtained.

Thus, the loop impedance measure does not depend on the capacitance of the capacitor, which can change due to manufacturing intersections and excessive temperature changes.

The maximum loop voltage to be measured is 50V
And if the maximum loop current to be measured is 25 mA, and if the second current Ii is set to 1 mA, then K1 can be determined to be 25 from the above equation, and R1 is 12.
It can be determined as 5K ohm. Prior to use, K1 and R1 may be further scaled. R1 and K1 are S
It may be distributed in the LIC.

Generally, the loop voltage Vloop is 20
(That is, the value of N in the scale circuit 14), and the voltage applied to the capacitor is 1.25.
V. Capacitor 34 has a capacitance of 0.1 uF and the square wave signal is 20 Hz (T1 = 1/2
^{* At} a frequency of 1/20), the scaling factors R1 and K1 are

[0056]

(Equation 7) Can be determined by

The value of R1 includes 20 scaling factors. Therefore, the physical resistor is 2.5 M / 20 = 125 l
It may have an ohmic resistance. The value of R1 may be further reduced to the actual on-chip value by scaling the resulting current.

The signal information indicating the line impedance is represented by SL
It may be on a single lead of the IC. One such lead may be a lead that detects a ground key. One reason for using the ground key sensing lead as the output lead is that the central office may incorrectly measure the output signal waveform at the ringing frequency for loop break dial pulses using fast dialing (20 pps). Because.

If the lead detecting the grounding key is not available, the information may be placed on the lead detecting the switching hook. In general, using a lead that senses a switching hook does not interfere with conventional off-hook sensing signals (continuous active low signal). The pulsed output generated from measuring the impedance can be clearly recognized from the continuous low off-hook signal. Pulsed output can be ensured that the subscriber is only measured during the off-hook state.

The Maintenance Termination Unit (MT
In a subscriber network using U), a consumer may have a remote loopback switch at home activated for continuity testing. In such a network, activating the remote loopback switch may not generate a continuous off-hook signal. Information on the loop impedance can be obtained by taking measurements while the subscriber is on-hook.

For subscriber loops having a loop resistance in excess of 2000 ohms, a higher resistance range can be selected by selecting an appropriate scaling factor.

The appendage interval T2 can be measured by generating a signal, while the capacitor is discharged into the counter to gate the high frequency clock signal. The contents of the counter may be converted to an impedance value, preferably by using the contents of the counter as an address for retrieving information from memory. The address may point to an entry in a look-up table that has been previously loaded with an impedance value.

The impedance value is

[0064]

(Equation 8) Can be obtained from In a one-to-one mark-to-space ratio square wave timing signal, T3 is equal to T1-T2;
The impedance value is

[0065]

(Equation 9) May be.

The time interval T1 may be a predetermined interval (for example, the first half cycle of a square wave signal). R1 and K1
May be predetermined such that a lookup table is generated by calculating Rloop for possible values of T2. The dimensions in the table generally depend on the clock speed. 2
A clock frequency of 0 Hz ^* 250 or 2.5 kHz is
The loop resistance range may be divided into 100 unequal increments, with the longest loop length having the least resolution. Resolution for longer loop lengths can be achieved by increasing the clock speed and dividing the measurement period (T2) into two or more intervals, or using higher frequencies as the measurement period is extended from interval to interval Can increase it.

The look-up table is only valid for the square wave signal frequency used to calculate the impedance value. The square wave signal frequency may be associated with a ringing frequency that varies from country to country or even within a country. Further, specific ringing may require several different frequencies. If the frequency of the square wave signal is different from the frequency used to generate the lookup table of impedance values, the clock frequency must be scaled or the lookup table must be recalculated.

The frequencies selected for the square wave signal are:
Preferably, it is long enough so that variations in the loop voltage and loop current are averaged out and filtered by the capacitor.

The capacitor 34 and the comparator 32 may be used for a ring trip detector 38.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a circuit in a subscriber loop interface circuit for measuring loop impedance of the present invention.

FIG. 2 is a timing chart showing output signals of a circuit of an embodiment of the subscriber loop interface circuit of the present invention.

FIG. 3 is a block diagram showing a ringing trip detector according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Loop current sensing circuit 14 Scale circuit 16 8, 20, 40, 92, 94, 96 Resistance element 20 Loop voltage sensing circuit 24 6, 28, 30, 78 Current mirror 32 Comparator 34, 84 Capacitor 36 Control switch 38 Ringing Trip detector 42 Ground 46 NAND gate 48 Counter 50 Memory 54 Comparator output signal 72 Terminal 74 Switch 76 Current adder 80 Zero crossing comparator 82 Ringing trip comparator 86 Combination logic circuit 88 Ringing relay switch 90 Ringing supply vessel

Claims (10)

[Claims] A loop voltage detector for detecting a loop voltage; a first current generator for generating a first current proportional to the detected loop voltage; and a loop current sensor for detecting a loop current. A second current generator for generating a second current proportional to the sensed loop current; and a second current generator for generating the third current.
And a means for determining a loop impedance from the first current and the third current, and a loop impedance measuring device including a capacitor. 2. The loop impedance measuring device comprises: means for directing the first current to the capacitor to charge the capacitor, and directing the third current to the capacitor to discharge the capacitor; Means for determining a discharge time of said capacitor; means for determining a loop impedance as a function of said determined discharge time; and said means for directing comprises a switch connected to said capacitor. The circuit according to 1. 3. The loop impedance measuring device includes a square wave signal generator connected to the switch, and periodically generating a square wave signal to periodically activate the switch. Means for detecting the discharge level of the capacitor and a clamp for holding the capacitor at or below the detected discharge level, wherein the square wave signal generated by the generation of the square wave signal shifts to enable charging of the capacitor. 3. The circuit of claim 2, including means for deactivating said clamp. 4. The loop impedance measuring device shares a circuit with another part of the subscriber loop interface circuit, and the other part of the subscriber loop interface circuit and the capacitor, the square wave generator, and 4. The circuit according to claim 3, wherein said switch is shared. 5. The circuit of claim 3, wherein the loop impedance measuring device has a look-up table that provides an impedance corresponding to the determined discharge time. 6. A method for sensing a loop voltage, generating a first current proportional to the sensed loop voltage, and providing the first current to the capacitor to charge the capacitor.
Deriving a current; and detecting a loop current, the method comprising: determining a loop impedance; generating a second current proportional to the sensed loop current; Adding the second current to the first current to generate a third current that is greater than the current and has the opposite polarity; and applying the third current to discharge the capacitor. Leading to a capacitor; determining a discharge time of the capacitor; and determining a loop impedance as a function of the discharge time. 7. The method of claim 6, wherein substantially all of the steps are performed within a subscriber loop interface circuit, wherein the subscriber loop interface circuit is an integrated semiconductor circuit. 8. The subscriber loop interface circuit including a switch for switching the capacitor from a charged state to a discharged state, and generating a square wave signal for periodically activating the switch. The method of claim 7, wherein: 9. A clamp for detecting a discharge level of the capacitor, activating the clamp to maintain the capacitor at the detected discharge level, and causing the capacitor to transition to the next transition of the square wave signal. 9. The method of claim 8 including the step of deactivating said clamp to allow for responsive charging. 10. The step of providing an impedance from a look-up table as a function of the predetermined time between the discharge time of the capacitor and the loop impedance determined only during an off-hook condition. 9. The method according to 9.